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| revision date: jan. 15, 2007 16 h8s/2199r group , h8s/2199r f-ztat? hardware manual renesas 16-bit single-chip microcomputer h8s family/h8s/2100 series h8s/2199r HD6432199R hd64f2199r h8s/2198r hd6432198r h8s/2197r hd6432197r h8s/2197s hd6432197s h8s/2196r hd6432196r h8s/2196s hd6432196s rev.2.00 rej09b0329-0200
rev.2.00 jan. 15, 2007 page ii of xliv rej09b0329-0200 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor g rants any license to any intellectual property ri g hts or any other ri g hts of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for dama g es or infrin g ement of any intellectual property or other ri g hts arisin g out of the use of any information in this document, includin g , but not limited to, product data, dia g rams, charts, pro g rams, al g orithms, and application circuit examples. 3. you should not use the products or the technolo g y described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exportin g the products or technolo g y described herein, you should follow the applicable export control laws and re g ulations, and procedures required by such laws and re g ulations. 4. all information included in this document such as product data, dia g rams, charts, pro g rams, al g orithms, and application circuit examples, is current as of the date this document is issued. such information, however, is subject to chan g e without any prior notice. before purchasin g or usin g any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay re g ular and careful attention to additional and different information to be disclosed by renesas such as that disclosed throu g h our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compilin g the information included in this document, but renesas assumes no liability whatsoever for any dama g es incurred as a result of errors or omissions in the information included in this document. 6. when usin g or otherwise relyin g on the information in this document, you should evaluate the information in li g ht of the total system before decidin g about the applicability of such information to the intended application. renesas makes no representations, warranties or g uaranties re g ardin g the suitability of its products for any particular application and specifically disclaims any liability arisin g out of the application and use of the information in this document or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not desi g ned, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially hi g h quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considerin g the use of our products for such purposes, please contact a renesas sales office beforehand. renesas shall have no liability for dama g es arisin g out of the uses set forth above. 8. notwithstandin g the precedin g para g raph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) sur g ical implantations (3) healthcare intervention (e. g ., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for dama g es arisin g out of the uses set forth in the above and purchasers who elect to use renesas products in any of the fore g oin g applications shall indemnify and hold harmless renesas technolo g y corp., its affiliated companies and their officers, directors, and employees a g ainst any and all dama g es arisin g out of such applications. 9. you should use the products described herein within the ran g e specified by renesas, especially with respect to the maximum ratin g , operatin g supply volta g e ran g e, movement power volta g e ran g e, heat radiation characteristics, installation and other product characteristics. renesas shall have no liability for malfunctions or dama g es arisin g out of the use of renesas products beyond such specified ran g es. 10. althou g h renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to g uard a g ainst the possibility of physical injury, and injury or dama g e caused by fire in the event of the failure of a renesas product, such as safety desi g n for hardware and software includin g but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for a g in g de g radation or any other applicable measures. amon g others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowin g by infants and small children is very hi g h. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for dama g es arisin g out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from renesas. 13. please contact a renesas sales office if you have any questions re g ardin g the information contained in this document, renesas semiconductor products, or if you have any other inquiries. notes re g ardin g these materials rev.2.00 jan. 15, 2007 page iii of xliv rej09b0329-0200 general precautions in the ha ndling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, re fer to the relevant sections of the manual. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are generally in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the possible future expansion of functions. do not access these addresses; the correct operation of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different type numbers, implement a system-evaluation test for each of the products. rev.2.00 jan. 15, 2007 page iv of xliv rej09b0329-0200 rev.2.00 jan. 15, 2007 page v of xliv rej09b0329-0200 preface this lsi is a single-chip microcomputer made up of the h8s/2000 cpu with an internal 32-bit architecture as its core, and the peripheral functions required to configure a system. this lsi is equipped with rom, ram, digital servo circuits, a sync separator, an osd, a data slicer, seven types of timers, three types of pw ms, two types of serial communication interfaces (scis), an i 2 c bus interface (iic), a d/a converter, an a/d converter, and i/o ports as on-chip supporting modules. this lsi is suitable for use as an embedded processor for high-level control systems. its on-chip rom is flash memory (f-ztat tm *) that provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. this is particularly applicable to application devices with specifications that will most probably change. note: * f-ztat is a trademark of renesas technology corp. target users: this manual was written for us ers who will be using the h8s/2199r group and h8s/2199r f-ztat tm in the design of application systems. members of this audience are expected to understand the fu ndamentals of electri cal circuits, logical circuits, and microcomputers. objective: this manual was written to explain the hardware functions and electrical characteristics of the h8s/2199r group and h8s/2199r f-ztat tm to the above audience. refer to the h8s/2600 series, h8s/2000 series software manual for a detailed description of the instruction set. notes on reading this manual: ? in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, peripher al functions and elect rical characteristics. ? in order to understand the details of the cpu?s functions read the h8s/2600 series, h8s/2000 series software manual. ? in order to understand the details of a register when its name is known the addresses, bits, and initial values of the registers are summarized in appendix b, internal i/o registers. rev.2.00 jan. 15, 2007 page vi of xliv rej09b0329-0200 examples: register name: the following notatio n is used for cases when the same or a similar function, e.g. 16-bit timer pulse unit or serial communication, is implemente d on more than one channel: xxx_n (xxx is the register name and n is the channel number) bit order: the msb is on the left and the lsb is on the right. number notation: binary is b'xxxx, hexadecimal is h'xxxx, decimal is xxxx signal notation: an overbar is added to a low-active signal: xxxx related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. http://www.renesas.com/ rev.2.00 jan. 15, 2007 page vii of xliv rej09b0329-0200 h8s/2199r gruop and h8s/2199r f-ztat tm manuals: document title document no. h8s/2199r gruop, h8s/2199r f-ztat tm hardware manual this manual h8s/2600 series, h8s/2000 series software manual rej09b0139 user?s manuals for development tools: document title document no. h8s, h8s/300 series c/c++ compiler, assembler, optimizing linkage editor user?s manual rej10b0058 h8s, h8s/300 series simulator/debugger user?s manual ade-702-037 high-performance embedded workshop user?s manual ade-702-201 application notes: document title document no. h8s series technical q&a application note rej05b0397 rev.2.00 jan. 15, 2007 page viii of xliv rej09b0329-0200 rev.2.00 jan. 15, 2007 page ix of xliv rej09b0329-0200 main revisions in this edition item page revision (see manual for details) all ? ? notification of change in company name amended (before) hitachi, ltd. (after) renesas technology corp. ? product naming convention amended (before) h8s/2199r series (after) h8s/2199r group ? package code amended (before) fp-112 (after) prqp0112ja-a 2.1.3 difference from h8s/300 cpu 21 expanded address space note * added normal mode * supports the same 64-kbytee address space ... note: * normal mode is not available in this lsi. 2.2 cpu operating modes 22 note * added h8s/2000 cpu has two operating modes: normal * and advanced. normal mode * supports a maximum 64-mbyte address space. note: * normal mode is not available in this lsi. 2.3 address space 27 note * added ... 64-kbyte address space in normal mode * , and maximum ... note: * normal mode is not available in this lsi. 2.6.1 overview table 2.1 instruction classification 36 table 2.1 amended bit manipulation (before) rset (after) bset 2.6.3 table of instructions classified by function table 2.4 arithmetic instruction 41 size description amended adds, subs (before) b (after) l daa, das (before) b/w (after) b rev.2.00 jan. 15, 2007 page x of xliv rej09b0329-0200 item page revision (see manual for details) 2.6.3 table of instructions classified by function table 2.10 block data transfer instructions 48 table 2.10 amended instruction size * function eepmov.b ? if if r4l 0 then repeat @er5+ @er6+ r4l ? 1 r4l until r4l = 0 else nex t; eepmov.w ? r4 0 then repeat @er5+ er6+ r4 ? 1 r4 until r4 = 0 else next; transfers a data block accordin g to parameters set in g eneral re g isters r4l or r4, er5, and er6 r4l or r4: size of block (bytes ) 2.7.1 addressing mode table 2.11 addressing modes 51 table 2.11 amended symbol of absolute address amended (before) @aa:8/#@aa:16/@aa:24//@aa:32 (after) @aa:8/@aa:16/@aa:24//@aa:32 table 2.12 absolute address access ranges 53 table 2.12 amended absolute address normal mode advanced mode 8 bits (@aa:8) h'ff00 to h'ffff h'ffff00 to h'ffff ff 16 bits (@aa:16) h'000000 to h'007fff, h'ff8000 to h'ffff ff data address h'0000 to h'ffff 2.8.1 overview figure 2.16 state transitions 59 figure 2.16 amended res = high sleep instruction with lson = 0, ssby = 1, tma3 = 0 7.3.3 erase block register 1 (ebr1) 141 bit figure amended 7 eb7 0 r/w bit initial value r/w : : 7.3.4 erase block register 2 (ebr2) 142 bit figure amended 7 eb15 0 r/w bit initial value r/w : : : 10.3.2 register configuration 193 port mode register 1 (pmr1) description amended when the pin functions of p16/ ic and p15/irq5 to p10/irq0 are switched by pmr1, ... 10.4.3 pin functions 200 p27/sysci bit table amended (before) pcr (after) pcr27 rev.2.00 jan. 15, 2007 page xi of xliv rej09b0329-0200 item page revision (see manual for details) 10.5.3 pin functions 209 description amended p34/pwm2: p34/pwm2 is switched as shown below ... 10.6.1 overview 211 description amended ... it is switched by port mode register 4 (pmr4), timer output ... 10.8 overview 226 description amended port 7 consists of pins that are used both as standard i/o ports (p77 to p70), hsw timing generation circuit ... outputs (ppg7 to ppg0), and realtime output port (rpb to rp8). ... 10.8.3 pin functions 231 description amended p73/ppg3 to p70/ppg0: p73/ppg3 to p70/ppg0 are switched as shown below ... 10.9.2 register configuration 235 description amended ... when reset, pmr8 is initialized to h'00. ... 10.9.3 pin functions 241 description amended p84/h.amp sw/g: ... according to the pmr84 bit in pmr8, pmrc4 bit in pmrc, and pcr84 bit in pcr8. 13.2.5 timer counter k (tck) 267 description amended ... the inputting clock can be selected by the exn and ps22 bits of the tmj, and the ps21 and ps20 bits of the tmj. ... 15.2.1 timer r mode register 1 (tmrm1) 294 description amended bit 0 ? capture signals of the tmru-1 (cps): in combination with the lat bit (bit 7) of the tmrm2, this bit works ... 16.6 exemplary uses of timer x1 338 description amended 2. each time a comparing match occurs, the olvla bit and the olvlb bit are reserved by use of the software. 17.2.1 watchdog timer counter (wtcnt) 347 description amended wtcnt is an 8-bit readable/writable * up-counter. ... 18.2.2 8-bit pwm control register (pw8cr) 360 description amended ... pw8cr is initialized to h'f0 by a reset. 18.2.3 port mode register 3 (pmr3) 361 description amended bits 5 to 2 ? p35/pwm3 to p32/pwm0 pin switching (pmr35 to pmr32): these bits set whether the p3n/pwmm pin is used as i/o pin or it is used as 8-bit pwm output pwmm pin. 20.2.2 pwm data registers u and l (pwdru, pwdrl) 376 description amended pwm data registers u and l ...in one pwm waveform cycle. ... rev.2.00 jan. 15, 2007 page xii of xliv rej09b0329-0200 item page revision (see manual for details) 22.2.4 transmit data register 1 (tdr1) 394 description amended ... when the sci detects that tsr1 is empty, ... 22.2.7 serial status register 1 (ssr1) 402 bit 7 description amended [setting condition] 1. when the te bit in scr1 is 0 403 bit 6 description amended [setting condition] when serial reception ... is transferred from rsr1 to rdr1 405 bit 1 description amended bit 1 mpb 0 [clearin g condition] (initial value) when data with a 0 multiprocessor bit is received * description 22.2.8 bit rate register 1 (brr1) 406 description amended brr1 is an 8-bit register ... by bits cks1 and cks0 in smr1. ... rev.2.00 jan. 15, 2007 page xiii of xliv rej09b0329-0200 item page revision (see manual for details) 22.2.8 bit rate register 1 (brr1) table 22.3 brr1 settings for various bit rates (asynchronous mode) 407, 408 table 22.3 amended operating frequecy (mhz) 2 2.4576 3 bit rate (bits/ s) 1200 0 51 0.16 0 54 ? 0.71 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.12 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 ? 2.54 0 15 0.00 0 19 ? 2.40 9600 ? ? ? 6 0 ? 2.54 0 7 0.00 0 9 ? 2.40 19200 ? ? ? ? ? ? 0 3 0.00 0 4 ? 2.40 110 2 64 0.69 2 70 0.03 2 86 0.31 2 88 0.25 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ? 1.38 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.70 19200 0 5 0.00 ? ? ? 0 7 0.00 0 7 1.70 31250 ? ? ? 0 3 0.00 0 4 ? 1.73 0 4 0.00 38400 0 2 0.00 ? ? ? 0 3 0.00 0 3 1.70 n n error (%) n n error (%) n n error (%) n n error (%) 2.097152 operating frequecy (mhz) 3.6864 4.9152 5 bit rate (bits/ s) n n error (%) n n error (%) n n error (%) n n error (%) 4 operating frequecy (mhz) 6 7.3728 8 bit rate (bits/ s) n n error (%) n n error (%) n n error (%) n n error (%) 6.144 operating frequecy (mhz) 9.8304 bit rate (bits/ s) n n error (%) n n error (%) 10 9600 0 19 ? 2.40 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 ? 2.40 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.34 ? ? ? 0 7 0.00 38400 0 4 ? 2.40 0 4 0.00 0 5 0.00 ? ? ? 9600 0 31 0.00 0 32 ? 1.38 19200 0 15 0.00 0 15 1.70 31250 0 9 ? 1.73 0 9 0.00 38400 0 7 0.00 0 7 1.70 22.2.9 serial interface mode register 1 (scmr1) 413 bit 3 description amended tdr1 contents are transmitted ... 22.3.2 operation in asynchronous mode figure 22.7 sample serial reception data flowchart (1) 424 figure 22.7 amended [2] [3] receive error handling and break detection: ... and fer flags in ssr1 to identify the error. after performing the appropriate error handling, ensure that the orer, per, and fer flags are all cleared to 0. ... [4] sci status check and receive data read: read ssr1 and check that rdrf = 1, then ... rev.2.00 jan. 15, 2007 page xiv of xliv rej09b0329-0200 item page revision (see manual for details) 22.3.3 multiprocessor communication function figure 22.11 sample multiprocessor serial transmission flowchart 429 figure 22.11 amended [2] sci status check and transmit data write: read ssr1 and check that the tdre flag is set to 1, then ... figure 22.13 sample multiprocessor serial reception flowchart (1) 432 figure 22.13 amended [3] sci status check, id reception and comparison: read ssr1 and check that the rdrf flag is set to 1, then ... 22.3.4 operation in synchronous mode figure 22.17 sample sci initialization flowchart 437 figure 22.17 amended set data transfer format in smr1 and scmr1 figure 22.22 sample flowchart of simultaneous serial transmit and receive operations 443 figure 22.22 amended rdrf = 1 23.2.5 i 2 c bus control register (iccr) 464 bit 7 description amended bit 7 ice 1 2 c bus interface module enabled for transfer operations (pins scl and sda are drivin g the bus) icmr and icdr can be acce ssed i description 23.3.2 master transmit operation 482 description amended [11] ... when there is data to be transmitted, go to the step [9] to continue next transmission. ... 23.3.4 slave receive operation 485 description amended 5. ... at this time, rdrf flag is cleared to 0. 23.4 usage note 499 description amended 6. ... the i 2 c bus interface scl and sda output timing is prescribed by t cyc , as shown in table 23.5. ... rev.2.00 jan. 15, 2007 page xv of xliv rej09b0329-0200 item page revision (see manual for details) 23.4 usage note 504 to 511 10. notes on wait function 11. notes on icdr reads and iccr access in slave transmit mode 12. notes on trs bit setting in slave mode 13. notes on arbitration lost in master mode 14. notes on interrupt occurrence after ackb reception 15. notes on trs bit setting and icdr register access description added 26.2.1 overview 556 description amended this lsi is equipped with ... and twenty-nine pins multiplexed with general-purpose ports. ... 26.4.5 register description 601 fifo output pattern register 2 (fpdrb) description amended bit 13 ? s-trigb bit (strigb): ... when the strigb is selected by the isel, ... 26.4.6 operation figure 26.23 example of timing waveform of hsw (for 12 dfg pulses) 608 figure 26.23 amended example of setting: dfcra = h'02, dfcrb = h'08, ... 26.7.4 register description 632 drum pulse preset data registers (dppr1, dppr2) description amended ... the preset data can be calculated from the following equation by using h'8000 as the reference value. 26.13.5 register description 698 bit 0 description amended ? asm mark direct mode: ... the duty i/o flag is 1 when the duty cycle of the pb-ctl signal is below 65% (when an asm mark is not detected). 26.13.6 operation figure 26.50 example of ctlm switchover timing (when phase control is performed by ref30p and dvcfg2 in rec mode) 701 note 1 amended note: 1. ta is the interval calculated from rcdr3. rev.2.00 jan. 15, 2007 page xvi of xliv rej09b0329-0200 item page revision (see manual for details) 26.13.6 operation figure 26.51 example of ctlm switchover timing (when phase control is performed by cref and dvcfg2 in rec mode) 702 note 1 amended note: 1. ta is the interval calculated from rcdr3. 26.15.5 register description 736 horizontal sync signal threshold register (htr) description amended ... thus, if s = 5 mhz, ntsc system is used, ... (hvth - 2) 0.4 s 2.35 s < (hvth - 1) 0.4 s hvth h'7 26.15.6 noise detection 741 description amended example of setting: ... accordingly, ... (value of hpwr3 - 0) + 1) 0.4 ( s) = 4.7 ( s) hpwr3 - 0 = h'b ... 27.1.2 block diagram figure 27.1 sync separator block diagram 753 figure 27.1 amended afcosc afcpc afclpf afc oscillator 27.2.1 sync separation input mode register (sepimr) 755 description amended bits order than bit 5 ccmpsl are cleared to 0 ... 27.2.2 sync separation control register (sepcr) 762 bit 2 description amended ... forcibly operates the half hsync killer (hhk) * function when ... note * added note: * hhk: half hsync killer rev.2.00 jan. 15, 2007 page xvii of xliv rej09b0329-0200 item page revision (see manual for details) 27.2.4 horizontal sync signal threshold register (hvthr) figure 27.3 hvth value and seph generation timing when equalization pulses are detected 765 figure 27.3 title amended 766 description amended in general, ... , set the hvth value so that 2.35- s equalizing pulses can be detected. figure 27.8 timing of hsync-vsync phase- difference error due to noise occurrence after equalizing pulse is lost at hsync pulse position 768 "hc" deleted from figure 27.8 figure 27.9 timing of forcible hhk operation in v blanking period when equalizating pulse is not detected 769 "hc" deleted from figure 27.9 27.2.5 vertical sync signal threshold register (vvthr) figure 27.10 vvth value and sepv generation timing 770 figure 27.10 title amended figure 27.11 vvth value and sepv generation timing when digital lpf is enabled 771 figure 27.11 title amended 27.2.6 field detection window register (fwidr) 772 (1) bit 0 of sepcr register bit 0 table amended (before) ld (after) fld 27.3.5 noise detection 789 description amended ... the noise detection window signal is se to 1 ... at the hhk clearing timing specified by bits hm6 to hm0 of the hcmmr. ... rev.2.00 jan. 15, 2007 page xviii of xliv rej09b0329-0200 item page revision (see manual for details) 28.2.1 slice even- (odd-) fields mode register (sevfd, sodfd) 1004 bits 4 to 0 notes amended notes: 1. 576 when bit 0 (frqsel) of sepimr in the sync separator is 0, and 448 when frqsel is 1. 2. fh: horizontal sync signal frequency 28.2.5 module stop control register (mstpcr) 811 bit figure amended 7 1 r/w mstp 15 mstp 14 mstp 13 mstp 12 mstp 11 mstp 10 mstp 9 mstp 8 mstp 7 mstp 6 mstp 5 mstp 4 mstp 3 mstp 2 mstp 1 mstp 0 6 1 r/w 54 1 r/w mstpcrh mstpcrl 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w bit: initial value: r/w: 28.4 32-bit slice operation figure 28.13 sampling clock when bit dsl32b is 1 819 note * amended note: * 576 when ... is set to 0. 448 when bit frqsel (bit 0) in sepimr (synchronization separator) is set to 1. 29.2.3 on-screen display configuration figure 29.4 correspondence between display data ram and on-screen display 829 note amended note: d800 to dafe indicate the lower 16 bits of addresses in the on-screen display ram. 29.3.6 character data rom (osdrom) figure 29.7 osd rom map 834 figure 29.7 amended bit data for character code h'000 (blank character display) * 1 045fff * 2 notes: 1. character code h'000 is reserved for blank character display and ... 040000 :h'f0 040001 :h'00 040002 :h'f0 040003 :h'00 ... 040022 :h'f0 040023 :h'00 040024 :h'ff 04003f :h'ff 2. these addresses represent the h8s/2199r group addresses. rev.2.00 jan. 15, 2007 page xix of xliv rej09b0329-0200 item page revision (see manual for details) 29.3.7 display data ram (osdram) 839 bits 11 to 9 bit table amended osdram character color bit 11 bit 10 bit 9 c.video output cr cg cb ntsc pal r,g,b output s 0 black black black 0 1 blue 07 /4 3 /2 7 /4 3 /2 green 0 1 1 cyan 29.4.5 row registers (clinen, n = rows 1 to 12) 842 bit figure amended bit 4 (before) clun2 (after) clun0 846 bit 0 ? cursor brightness/halftone levels specification bit (klun, n = 1 to 12) ? cursor brightness in text display mode ? halftone levels in superimposed mode bit table amended (before) klu (after) klun 29.6.5 osdv interrupt 858 bit figure amended r/w description in bit 10 (before) r/w (after) ? 31.4.8 flash memory characteristics table 31.32 flash memory characteristics 950 table 31.32 amended item symbol min typ max unit notes pro g rammin g time * 1 * 2 * 4 t p ? 10 200 ms/128 bytes erase time * 1 * 3 * 5 t t e ? 100 1200 ms/block repro g rammin g count n wec 100 * 8 10000 * 9 ? times data retention time * 10 drp 10 ? ? years 951 notes 6 to 8 added notes: 6. minimum number of times for which all characteristics are guaranteed after rewriting (guarantee range is 1 to minimum value). 7. reference value for 25c (as a guide line, rewriting should normally function up to this value). 8. data retention characteristics when rewriting is performed within the specification range, including the minimum value. b.2 function list 1022 h'd029: cfic: digital filter figure amended capstan phase system z -1 initialization bit 0 phase system z -1 does not reflect cz p value. (initial value) 1 phase system z -1 reflects cz p value. rev.2.00 jan. 15, 2007 page xx of xliv rej09b0329-0200 item page revision (see manual for details) b.2 function list 1071 h'd106: tcrx: timer x1 figure amended icrd is not used as buffer re g ister for icrb (initial value) icrd is used as buffer re g ister for icrb 0 1 buffer enable b 1103 h'd200 to h'd20b: cline1 to cline12: osd figure amended bit 4 (before) clun2 (after) clun0 (cursor colors in text display mode) cursor color specification bits bit 3 bit 2 bit 1 character bri g htness level krn kgn kbn cursor color (c.video output) cursor color (r, g, b output) ntsc pal 0 0 0 black black black (initial value) 1 blue 1 0 7 /4 7 /4 1 3 /2 3 /2 1 0 0 /2 /2 1 3 /4 3 /4 1 0 same phase 0 green cyan red ma g enta yellow white 1 white white 1112 h'd222: sodfd: data slicer figure amended 0 1 2 3 4 5 7 dlyo4 dlyo3 dlyo2 dlyo1 dlyo0 slvlo2 6 slvlo1 slvlo0 : bit bit 4 (before) dlyo3 (after) dlyo4 1115 h'd240: sepimr: sync separator figure amended bit 5 (before) ccmpsl (after) ccmpsl * 1128 h'ffcd: pmr0: i/o port figure amended (before) p07/an7 to p00/irq0 rin function select bits (after) p07/an7 to p00/an0 pin switching 1137 h'ffe3: pur3: i/o port figure amended 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 0 r/w r/w r/w r/w 6 pur34 pur33 pur32 pur31 pur30 pur37 pur36 pur35 p3n pin has no pull-up mos transistor (initial value) p3n pin has pull-up mos transistor 0 1 bit initial value r/w : : : note: n = 7 to 0 rev.2.00 jan. 15, 2007 page xxi of xliv rej09b0329-0200 item page revision (see manual for details) b.2 function list 1138 h'ffe5: real time output trigger select register 1 rtpsr1: i/o port figure amended 0 1 2 3 4 5 6 7 rtpsr14 rtpsr13 rtpsr12 rtpsr11 rtpsr10 rtpsr17 rtpsr16 rtpsr15 bit : subheading amended h'ffe6: real time output trigger select register 2 rtpsr2: i/o port 1141 h'ffeb: lpwrcr: system control note * deleted from dton description (before) ? ... to subactive mode * , or transition is made directly to sleep mode or standby mode (after) ? ... to subactive mode, or transition is made directly to sleep mode or standby mode 1142 h'ffee: stcr: system control note * added to i 2 c control description used combined with cks2 to cks0 in icmr0 * e.1 power supply rise and fall order figure e.1 power supply rise and fall order 1163 figure e.1 amended v cc , av cc sv cc , ov cc vin appendix g package dimensions figure g.1 package dimensions (prqp0112ja-a) 1173 figure g.1 replaced rev.2.00 jan. 15, 2007 page xxii of xliv rej09b0329-0200 all trademarks and registered trademarks are the property of their respective owners. rev.2.00 jan. 15, 2007 page xxiii of xliv rej09b0329-0200 contents section 1 overview ............................................................................................................. 1 1.1 overview....................................................................................................................... .... 1 1.2 internal block diagram..................................................................................................... 7 1.3 pin arrangement and functions........................................................................................ 9 1.3.1 pin arrangement .................................................................................................. 9 1.3.2 pin functions ....................................................................................................... 11 section 2 cpu ...................................................................................................................... 19 2.1 overview....................................................................................................................... .... 19 2.1.1 features................................................................................................................ 19 2.1.2 differences between h8s/2600 cpu and h8s/2000 cpu .................................. 20 2.1.3 differences from h8/300 cpu............................................................................. 21 2.1.4 differences from h8/300h cpu.......................................................................... 21 2.2 cpu operating modes ...................................................................................................... 22 2.2.1 normal mode (not availa ble for this lsi)........................................................... 22 2.2.2 advanced mode ................................................................................................... 24 2.3 address space .................................................................................................................. . 27 2.4 register configuration...................................................................................................... 28 2.4.1 overview.............................................................................................................. 28 2.4.2 general registers ................................................................................................. 29 2.4.3 control registers ................................................................................................. 30 2.4.4 initial register values.......................................................................................... 32 2.5 data formats ................................................................................................................... .. 33 2.5.1 general register data formats ............................................................................ 33 2.5.2 memory data formats ......................................................................................... 35 2.6 instruction set ................................................................................................................ ... 36 2.6.1 overview.............................................................................................................. 36 2.6.2 instructions and a ddressing m odes ..................................................................... 38 2.6.3 table of instructions classified by function ....................................................... 39 2.6.4 basic instruction formats .................................................................................... 49 2.6.5 notes on use of bit-manipulation instructions ................................................... 50 2.7 addressing modes and effective address calculation ..................................................... 51 2.7.1 addressing mode ................................................................................................. 51 2.7.2 effective address calculation.............................................................................. 54 2.8 processing states.............................................................................................................. . 58 2.8.1 overview.............................................................................................................. 58 2.8.2 reset state............................................................................................................ 59 rev.2.00 jan. 15, 2007 page xxiv of xliv rej09b0329-0200 2.8.3 exception-handling state .................................................................................... 60 2.8.4 program execution state...................................................................................... 61 2.8.5 power-down state ............................................................................................... 62 2.9 basic timing................................................................................................................... .. 63 2.9.1 overview.............................................................................................................. 63 2.9.2 on-chip memory (rom, ram) ......................................................................... 63 2.9.3 on-chip supporting modul e access timing ...................................................... 63 2.10 usage note..................................................................................................................... ... 64 2.10.1 tas instruction.................................................................................................... 64 2.10.2 stm/ldm instruction ......................................................................................... 64 section 3 mcu operating modes .................................................................................. 65 3.1 overview....................................................................................................................... .... 65 3.1.1 operating mode selection ................................................................................... 65 3.1.2 register configuration......................................................................................... 65 3.2 register descriptions ........................................................................................................ 6 6 3.2.1 mode control register (mdcr) ......................................................................... 66 3.2.2 system control register (syscr) ...................................................................... 66 3.3 operating mode (mode 1) ................................................................................................ 67 3.4 address map in each operating mode............................................................................. 68 section 4 power-down state ............................................................................................ 71 4.1 overview....................................................................................................................... .... 71 4.1.1 register configuration......................................................................................... 76 4.2 register descriptions ........................................................................................................ 7 6 4.2.1 standby control regist er (sbycr) .................................................................... 76 4.2.2 low-power control register (lpwrcr) ........................................................... 78 4.2.3 timer register a (tma) ..................................................................................... 80 4.2.4 module stop control regi ster (mstpcr) .......................................................... 81 4.3 medium-speed mode........................................................................................................ 82 4.4 sleep mode ..................................................................................................................... .. 83 4.4.1 sleep mode .......................................................................................................... 83 4.4.2 clearing sleep mode............................................................................................ 83 4.5 module stop mode ........................................................................................................... 84 4.5.1 module stop mode .............................................................................................. 84 4.6 standby mode ................................................................................................................... 85 4.6.1 standby mo de ...................................................................................................... 85 4.6.2 clearing sta ndby mode ....................................................................................... 85 4.6.3 setting oscillation settling time af ter clearing standby mode.......................... 85 4.7 watch mode..................................................................................................................... . 87 rev.2.00 jan. 15, 2007 page xxv of xliv rej09b0329-0200 4.7.1 watch mode......................................................................................................... 87 4.7.2 clearing watch mode .......................................................................................... 87 4.8 subsleep mode.................................................................................................................. 88 4.8.1 subsleep mode..................................................................................................... 88 4.8.2 clearing subsleep mode ...................................................................................... 88 4.9 subactive mode................................................................................................................. 89 4.9.1 subactive mode ................................................................................................... 89 4.9.2 clearing subactive mode..................................................................................... 89 4.10 direct tr ansition .............................................................................................................. . 90 4.10.1 overview of direct transition ............................................................................. 90 section 5 exception handling ......................................................................................... 91 5.1 overview....................................................................................................................... .... 91 5.1.1 exception handling types and priority............................................................... 91 5.1.2 exception handling operation............................................................................. 92 5.1.3 exception sources and vector table ................................................................... 92 5.2 reset.......................................................................................................................... ........ 94 5.2.1 overview.............................................................................................................. 94 5.2.2 reset sequence .................................................................................................... 94 5.2.3 interrupts after reset............................................................................................ 95 5.3 interrupts ..................................................................................................................... ...... 96 5.4 trap instruction............................................................................................................... .. 97 5.5 stack status after exception handling.............................................................................. 98 5.6 notes on use of the stack ................................................................................................. 99 section 6 interrupt controller .......................................................................................... 101 6.1 overview....................................................................................................................... .... 101 6.1.1 features................................................................................................................ 101 6.1.2 block diagram ..................................................................................................... 102 6.1.3 pin configuration................................................................................................. 103 6.1.4 register configuration......................................................................................... 103 6.2 register descriptions ........................................................................................................ 1 04 6.2.1 system control register (syscr) ...................................................................... 104 6.2.2 interrupt control registers a to d (icra to icrd) ........................................... 105 6.2.3 irq enable register (ienr) ............................................................................... 106 6.2.4 irq edge select registers (iegr) ...................................................................... 107 6.2.5 irq status register (irqr) ................................................................................ 108 6.2.6 port mode register 1 (pmr1) ............................................................................. 109 6.3 interrupt sources .............................................................................................................. . 110 6.3.1 external interrupts ............................................................................................... 110 rev.2.00 jan. 15, 2007 page xxvi of xliv rej09b0329-0200 6.3.2 internal interrupts ................................................................................................ 112 6.3.3 interrupt exception vector table ........................................................................ 113 6.4 interrupt operation............................................................................................................ 116 6.4.1 interrupt control modes and interrupt operation................................................ 116 6.4.2 interrupt control mode 0 ..................................................................................... 118 6.4.3 interrupt control mode 1 ..................................................................................... 120 6.4.4 interrupt exception handling sequence .............................................................. 123 6.4.5 interrupt respons e times .................................................................................... 124 6.5 usage notes .................................................................................................................... .. 125 6.5.1 contention between interrupt ge neration and disabling..................................... 125 6.5.2 instructions that di sable interrupts..................................................................... 126 6.5.3 interrupts during execution of eepmov instruction.......................................... 126 section 7 rom ..................................................................................................................... 127 7.1 overview....................................................................................................................... .... 127 7.1.1 block diagram..................................................................................................... 127 7.2 overview of flash memory .............................................................................................. 128 7.2.1 features................................................................................................................ 128 7.2.2 block diagram..................................................................................................... 129 7.2.3 flash memory operating modes ......................................................................... 130 7.2.4 pin configuration................................................................................................. 134 7.2.5 register configuration......................................................................................... 134 7.3 flash memory register descriptions................................................................................ 135 7.3.1 flash memory control register 1 (flmcr1)..................................................... 135 7.3.2 flash memory control register 2 (flmcr2)..................................................... 138 7.3.3 erase block register 1 (ebr1) ........................................................................... 141 7.3.4 erase block register 2 (ebr2) ........................................................................... 142 7.3.5 serial/timer control register (stcr) ................................................................ 143 7.4 on-board programming modes........................................................................................ 144 7.4.1 boot m ode ........................................................................................................... 145 7.4.2 user program mode............................................................................................. 150 7.5 programming/erasing flash memory ............................................................................... 151 7.5.1 program mode (n = 1 when the target address range is h'00000 to h'3ffff and n = 2 when the target addre ss range is h'40000 to h'47fff)................... 151 7.5.2 program-verify mode (n = 1 when the target address range is h'00000 to h'3ffff and n = 2 when the target address ra nge is h'40000 to h'47fff) .... 152 7.5.3 erase mode (n = 1 when the target address range is h'00000 to h'3ffff and n = 2 when the target address range is h'40000 to h'47fff).................... 154 7.5.4 erase-verify mode (n = 1 when the target address range is h'00000 to h'3ffff and n = 2 when the target address ra nge is h'40000 to h'47fff) .... 156 rev.2.00 jan. 15, 2007 page xxvii of xliv rej09b0329-0200 7.6 flash memory protection.................................................................................................. 157 7.6.1 hardware protection ............................................................................................ 157 7.6.2 software protection.............................................................................................. 158 7.6.3 error protection.................................................................................................... 158 7.7 interrupt handling when progra mming/erasing flash memory....................................... 159 7.8 flash memory prog rammer mode .................................................................................... 160 7.8.1 programmer mode setting ................................................................................... 160 7.8.2 socket adapters and memory map...................................................................... 160 7.8.3 programmer mode operation .............................................................................. 161 7.8.4 memory read mode ............................................................................................ 162 7.8.5 auto-program mode ............................................................................................ 165 7.8.6 auto-erase mode ................................................................................................. 167 7.8.7 status read mode ................................................................................................ 168 7.8.8 status po lling ....................................................................................................... 170 7.8.9 programmer mode transition time..................................................................... 170 7.8.10 notes on memory programmi ng.......................................................................... 171 7.9 note on switching from f?ztat version to mask-rom version ................................. 172 section 8 ram ..................................................................................................................... 173 8.1 overview....................................................................................................................... .... 173 8.1.1 block diagram ..................................................................................................... 173 section 9 clock pulse generator ..................................................................................... 175 9.1 overview....................................................................................................................... .... 175 9.1.1 block diagram ..................................................................................................... 175 9.1.2 register configuration......................................................................................... 175 9.2 register descriptions ........................................................................................................ 1 76 9.2.1 standby control regist er (sbycr) .................................................................... 176 9.2.2 low-power control register (lpwrcr) ........................................................... 176 9.3 oscilla tor..................................................................................................................... ...... 177 9.3.1 connecting a crystal resonator........................................................................... 177 9.3.2 external clock input ............................................................................................ 179 9.4 duty adjustment circuit ................................................................................................... 182 9.5 medium-speed clock divider .......................................................................................... 182 9.6 bus master clock sel ection circuit .................................................................................. 182 9.7 subclock oscillator circuit ............................................................................................... 182 9.7.1 connecting 32.768 khz crystal resonator .......................................................... 182 9.7.2 when subclock is not needed ............................................................................ 183 9.8 subclock waveform shaping circuit................................................................................ 183 9.9 notes on the resonator ..................................................................................................... 184 rev.2.00 jan. 15, 2007 page xxviii of xliv rej09b0329-0200 section 10 i/o port .............................................................................................................. 185 10.1 overview....................................................................................................................... .... 185 10.1.1 port functions ...................................................................................................... 185 10.1.2 port i nput ............................................................................................................. 185 10.1.3 mos pull-up transistors .................................................................................... 188 10.2 port 0......................................................................................................................... ........ 189 10.2.1 overview.............................................................................................................. 189 10.2.2 register configuration......................................................................................... 189 10.2.3 pin functions ....................................................................................................... 191 10.2.4 pin states ............................................................................................................. 191 10.3 port 1......................................................................................................................... ........ 192 10.3.1 overview.............................................................................................................. 192 10.3.2 register configuration......................................................................................... 192 10.3.3 pin functions ....................................................................................................... 196 10.3.4 pin states ............................................................................................................. 197 10.4 port 2......................................................................................................................... ........ 198 10.4.1 overview.............................................................................................................. 198 10.4.2 register configuration......................................................................................... 198 10.4.3 pin functions ....................................................................................................... 200 10.4.4 pin states ............................................................................................................. 203 10.5 port 3......................................................................................................................... ........ 204 10.5.1 overview.............................................................................................................. 204 10.5.2 register configuration......................................................................................... 204 10.5.3 pin functions ....................................................................................................... 208 10.5.4 pin states ............................................................................................................. 210 10.6 port 4......................................................................................................................... ........ 211 10.6.1 overview.............................................................................................................. 211 10.6.2 register configuration......................................................................................... 211 10.6.3 pin functions ....................................................................................................... 214 10.6.4 pin states ............................................................................................................. 216 10.7 port 6......................................................................................................................... ........ 217 10.7.1 overview.............................................................................................................. 217 10.7.2 register configuration......................................................................................... 218 10.7.3 pin functions ....................................................................................................... 222 10.7.4 operation ............................................................................................................. 224 10.7.5 pin states ............................................................................................................. 225 10.8 port 7......................................................................................................................... ........ 226 10.8.1 overview.............................................................................................................. 226 10.8.2 register configuration......................................................................................... 227 10.8.3 pin functions ....................................................................................................... 231 rev.2.00 jan. 15, 2007 page xxix of xliv rej09b0329-0200 10.8.4 operation ............................................................................................................. 232 10.8.5 pin states.............................................................................................................. 233 10.9 port 8......................................................................................................................... ........ 234 10.9.1 overview.............................................................................................................. 234 10.9.2 register configuration......................................................................................... 235 10.9.3 pin functions ....................................................................................................... 240 10.9.4 pin states.............................................................................................................. 242 section 11 timer a ............................................................................................................. 243 11.1 overview....................................................................................................................... .... 243 11.1.1 features................................................................................................................ 243 11.1.2 block diagram ..................................................................................................... 244 11.1.3 register configuration......................................................................................... 244 11.2 register descriptions ........................................................................................................ 2 45 11.2.1 timer mode register a (tma)........................................................................... 245 11.2.2 timer counter a (tca) ...................................................................................... 247 11.2.3 module stop control regi ster (mstpcr) .......................................................... 247 11.3 operation...................................................................................................................... ..... 248 11.3.1 operation as the interval timer ........................................................................... 248 11.3.2 operation as clock timer .................................................................................... 248 11.3.3 initializing the counts.......................................................................................... 248 section 12 timer b ............................................................................................................. 249 12.1 overview....................................................................................................................... .... 249 12.1.1 features................................................................................................................ 249 12.1.2 block diagram ..................................................................................................... 249 12.1.3 pin configuration................................................................................................. 250 12.1.4 register configuration......................................................................................... 250 12.2 register descriptions ........................................................................................................ 2 51 12.2.1 timer mode register b (tmb) ........................................................................... 251 12.2.2 timer counter b (tcb)....................................................................................... 253 12.2.3 timer load register b (tlb) ............................................................................. 253 12.2.4 port mode register a (pmra) ........................................................................... 254 12.2.5 module stop control regi ster (mstpcr) .......................................................... 255 12.3 operation...................................................................................................................... ..... 256 12.3.1 operation as the interval timer ........................................................................... 256 12.3.2 operation as the auto reload timer ................................................................... 256 12.3.3 event count er ...................................................................................................... 256 rev.2.00 jan. 15, 2007 page xxx of xliv rej09b0329-0200 section 13 timer j ............................................................................................................... 257 13.1 overview....................................................................................................................... .... 257 13.1.1 features................................................................................................................ 257 13.1.2 block diagram..................................................................................................... 257 13.1.3 pin configuration................................................................................................. 259 13.1.4 register configuration......................................................................................... 259 13.2 register descriptions ........................................................................................................ 2 60 13.2.1 timer mode register j (tmj) ............................................................................. 260 13.2.2 timer j control register (tmjc)........................................................................ 263 13.2.3 timer j status register (tmjs)........................................................................... 266 13.2.4 timer counter j (tcj) ......................................................................................... 267 13.2.5 timer counter k (tck) ...................................................................................... 267 13.2.6 timer load register j (tlj)................................................................................ 268 13.2.7 timer load register k (tlk)............................................................................. 268 13.2.8 module stop control regi ster (mstpcr) .......................................................... 269 13.3 operation ...................................................................................................................... .... 270 13.3.1 8-bit reload timer (tmj-1) ................................................................................ 270 13.3.2 8-bit reload timer (tmj-2) ................................................................................ 270 13.3.3 remote controlled data transmission ................................................................ 271 13.3.4 tmj-2 expansion function.................................................................................. 275 section 14 timer l ............................................................................................................. 277 14.1 overview....................................................................................................................... .... 277 14.1.1 features................................................................................................................ 277 14.1.2 block diagram..................................................................................................... 278 14.1.3 register configuration......................................................................................... 279 14.2 register descriptions ........................................................................................................ 2 80 14.2.1 timer l mode register (lmr) ........................................................................... 280 14.2.2 linear time counter (ltc)................................................................................. 282 14.2.3 reload/compare match register (rcr) ............................................................. 282 14.2.4 module stop control regi ster (mstpcr) .......................................................... 283 14.3 operation ...................................................................................................................... .... 284 14.3.1 compare match clear operation ......................................................................... 284 14.3.2 auto-reload operation........................................................................................ 285 14.3.3 interval timer operation ..................................................................................... 286 14.3.4 interrupt request.................................................................................................. 286 14.4 typical usage .................................................................................................................. . 287 14.5 reload timer interrupt request signal............................................................................. 287 rev.2.00 jan. 15, 2007 page xxxi of xliv rej09b0329-0200 section 15 timer r ............................................................................................................. 289 15.1 overview....................................................................................................................... .... 289 15.1.1 features................................................................................................................ 289 15.1.2 block diagram ..................................................................................................... 289 15.1.3 pin configuration................................................................................................. 291 15.1.4 register configuration......................................................................................... 291 15.2 register descriptions ........................................................................................................ 2 92 15.2.1 timer r mode register 1 (tmrm1)................................................................... 292 15.2.2 timer r mode regist er 2 (tmrm2)................................................................... 294 15.2.3 timer r control/status register (tmrcs)......................................................... 297 15.2.4 timer r capture register 1 (tmrcp1) .............................................................. 299 15.2.5 timer r capture register 2 (tmrcp2) .............................................................. 299 15.2.6 timer r load regist er 1 (tmr l1) ..................................................................... 300 15.2.7 timer r load regist er 2 (tmr l2) ..................................................................... 300 15.2.8 timer r load regist er 3 (tmr l3) ..................................................................... 301 15.2.9 module stop control regi ster (mstpcr) .......................................................... 301 15.3 operation...................................................................................................................... ..... 302 15.3.1 reload timer counter equipped w ith capturing func tion tmru-1.................. 302 15.3.2 reload timer counter equipped w ith capturing func tion tmru-2.................. 302 15.3.3 reload counter ti mer tmru-3.......................................................................... 303 15.3.4 mode identification.............................................................................................. 304 15.3.5 reeling controls .................................................................................................. 304 15.3.6 acceleration and braking processes of the capstan motor ................................. 304 15.3.7 slow tracking mono-multi function .................................................................. 305 15.4 interrupt cause................................................................................................................ .. 307 15.5 settings for respective functions ..................................................................................... 308 15.5.1 mode identification.............................................................................................. 308 15.5.2 reeling controls .................................................................................................. 309 15.5.3 slow tracking mono-multi function .................................................................. 310 15.5.4 acceleration and braking processes of the capstan motor ................................. 311 section 16 timer x1 ........................................................................................................... 313 16.1 overview....................................................................................................................... .... 313 16.1.1 features................................................................................................................ 313 16.1.2 block diagram ..................................................................................................... 314 16.1.3 pin configuration................................................................................................. 315 16.1.4 register configuration......................................................................................... 316 16.2 register descriptions ........................................................................................................ 3 17 16.2.1 free running coun ter (frc)............................................................................... 317 16.2.2 output comparing registers a and b (ocra and ocrb) ................................ 317 rev.2.00 jan. 15, 2007 page xxxii of xliv rej09b0329-0200 16.2.3 input capture registers a thr ough d (icra throug h icrd).............................. 318 16.2.4 timer interrupt enabling register (tier)........................................................... 319 16.2.5 timer control/status register x (tcsrx) ......................................................... 322 16.2.6 timer control register x (tcrx) ...................................................................... 326 16.2.7 timer output comparing cont rol register (tocr) ........................................... 328 16.2.8 module stop control regi ster (mstpcr) .......................................................... 330 16.3 operation ...................................................................................................................... .... 331 16.3.1 operation of timer x1......................................................................................... 331 16.3.2 counting timing of the frc ............................................................................... 332 16.3.3 output comparing signal outputting timing ..................................................... 333 16.3.4 frc clearing timing .......................................................................................... 333 16.3.5 input capture signal inputting timing................................................................ 334 16.3.6 input capture flag (icfa thro ugh icfd) setting up timing ............................ 335 16.3.7 output comparing flag (ocfa a nd ocfb) setting up timing ........................ 336 16.3.8 overflow flag (cvf) setting up timing............................................................ 336 16.4 operation mode of timer x1 ........................................................................................... 337 16.5 interrupt causes ............................................................................................................... . 337 16.6 exemplary uses of timer x1 ........................................................................................... 338 16.7 precautions when using timer x1 ................................................................................... 339 16.7.1 competition between writing and clearing with the frc .................................. 339 16.7.2 competition between writing and counting up with the frc ........................... 340 16.7.3 competition between writing and comparing match with the ocr .................. 341 16.7.4 changing over the internal clocks and counter operations............................... 342 section 17 watchdog timer (wdt) .............................................................................. 345 17.1 overview....................................................................................................................... .... 345 17.1.1 features................................................................................................................ 345 17.1.2 block diagram..................................................................................................... 346 17.1.3 register configuration......................................................................................... 347 17.2 register descriptions ........................................................................................................ 3 47 17.2.1 watchdog timer counte r (wtcnt)................................................................... 347 17.2.2 watchdog timer control/status register (wtcsr)........................................... 348 17.2.3 system control register (syscr) ...................................................................... 350 17.2.4 notes on register access..................................................................................... 351 17.3 operation ...................................................................................................................... .... 352 17.3.1 watchdog timer op eration ................................................................................. 352 17.3.2 interval timer operation ..................................................................................... 353 17.3.3 timing of setting of over flow flag (ovf)......................................................... 354 17.4 interrupts..................................................................................................................... ...... 354 17.5 usage notes .................................................................................................................... .. 355 rev.2.00 jan. 15, 2007 page xxxiii of xliv rej09b0329-0200 17.5.1 contention between watchdog timer counter (wtcnt) write and increment 355 17.5.2 changing value of cks2 to cks0...................................................................... 355 17.5.3 switching between watchdog timer mode and interval timer mode................ 356 section 18 8-bit pwm ....................................................................................................... 357 18.1 overview....................................................................................................................... .... 357 18.1.1 features................................................................................................................ 357 18.1.2 block diagram ..................................................................................................... 357 18.1.3 pin configuration................................................................................................. 358 18.1.4 register configuration......................................................................................... 358 18.2 register descriptions ........................................................................................................ 3 59 18.2.1 8-bit pwm data registers 0, 1, 2 and 3 (pwr0, pwr1, pwr2, pwr3)........... 359 18.2.2 8-bit pwm control register (pw8cr) ............................................................... 360 18.2.3 port mode register 3 (pmr3) ............................................................................. 360 18.2.4 module stop control regi ster (mstpcr) .......................................................... 361 18.3 8-bit pwm operation ....................................................................................................... 362 section 19 12-bit pwm ..................................................................................................... 363 19.1 overview....................................................................................................................... .... 363 19.1.1 features................................................................................................................ 363 19.1.2 block diagram ..................................................................................................... 364 19.1.3 pin configuration................................................................................................. 365 19.1.4 register configuration......................................................................................... 365 19.2 register descriptions ........................................................................................................ 3 66 19.2.1 12-bit pwm control registers (cpwcr, dpwcr) .......................................... 366 19.2.2 12-bit pwm data registers (dpwdr, cpwdr) .............................................. 368 19.2.3 module stop control regi ster (mstpcr) .......................................................... 369 19.3 operation...................................................................................................................... ..... 370 19.3.1 output waveform ................................................................................................ 370 section 20 14-bit pwm ..................................................................................................... 373 20.1 overview....................................................................................................................... .... 373 20.1.1 features................................................................................................................ 373 20.1.2 block diagram ..................................................................................................... 374 20.1.3 pin configuration................................................................................................. 374 20.1.4 register configuration......................................................................................... 375 20.2 register descriptions ........................................................................................................ 3 75 20.2.1 pwm control register (pwcr).......................................................................... 375 20.2.2 pwm data registers u and l (pwdru, pwdrl)............................................ 376 20.2.3 module stop control regi ster (mstpcr) .......................................................... 377 rev.2.00 jan. 15, 2007 page xxxiv of xliv rej09b0329-0200 20.3 14-bit pwm operation..................................................................................................... 378 section 21 prescalar unit .................................................................................................. 379 21.1 overview....................................................................................................................... .... 379 21.1.1 features................................................................................................................ 379 21.1.2 block diagram..................................................................................................... 380 21.1.3 pin configuration................................................................................................. 381 21.1.4 register configuration......................................................................................... 381 21.2 registers...................................................................................................................... ...... 382 21.2.1 input capture regist er 1 (icr 1).......................................................................... 382 21.2.2 prescalar unit control/statu s register (pcsr) ................................................... 382 21.2.3 port mode register 1 (pmr1) ............................................................................. 384 21.3 noise cancel circuit ......................................................................................................... 3 85 21.4 operation ...................................................................................................................... .... 385 21.4.1 prescalar s (pss) ................................................................................................. 385 21.4.2 prescalar w (psw) .............................................................................................. 386 21.4.3 stable oscillation wait time count .................................................................... 386 21.4.4 8-bit pwm ........................................................................................................... 387 21.4.5 8-bit input capture using ic pin ......................................................................... 387 21.4.6 frequency division clock output ....................................................................... 387 section 22 serial communication interface 1 (sci1) .............................................. 389 22.1 overview....................................................................................................................... .... 389 22.1.1 features................................................................................................................ 389 22.1.2 block diagram..................................................................................................... 391 22.1.3 pin configuration................................................................................................. 392 22.1.4 register configuration......................................................................................... 392 22.2 register descriptions ........................................................................................................ 3 93 22.2.1 receive shift register 1 (rsr1) ......................................................................... 393 22.2.2 receive data register 1 (rdr1) ......................................................................... 393 22.2.3 transmit shift register 1 (tsr1) ........................................................................ 394 22.2.4 transmit data register 1 (tdr1)........................................................................ 394 22.2.5 serial mode register 1 (smr1)........................................................................... 395 22.2.6 serial control regi ster 1 (s cr1)......................................................................... 398 22.2.7 serial status register 1 (ssr1) ........................................................................... 402 22.2.8 bit rate register 1 (brr1) ................................................................................. 406 22.2.9 serial interface mode register 1 (scmr1)......................................................... 413 22.2.10 module stop control regi ster (mstpcr) .......................................................... 414 22.3 operation ...................................................................................................................... .... 415 22.3.1 overview.............................................................................................................. 415 rev.2.00 jan. 15, 2007 page xxxv of xliv rej09b0329-0200 22.3.2 operation in async hronous m ode ....................................................................... 417 22.3.3 multiprocessor communication function............................................................ 427 22.3.4 operation in sync hronous mo de ......................................................................... 435 22.4 sci interrupts................................................................................................................. ... 444 22.5 usage notes .................................................................................................................... .. 445 section 23 i 2 c bus interface (iic) ................................................................................. 451 23.1 overview....................................................................................................................... .... 451 23.1.1 features................................................................................................................ 451 23.1.2 block diagram ..................................................................................................... 452 23.1.3 pin configuration................................................................................................. 453 23.1.4 register configuration......................................................................................... 454 23.2 register descriptions ........................................................................................................ 4 55 23.2.1 i 2 c bus data register (icdr) ............................................................................. 455 23.2.2 slave address register (sar) ............................................................................. 457 23.2.3 second slave address register (sarx) ............................................................. 459 23.2.4 i 2 c bus mode register (icmr) ........................................................................... 460 23.2.5 i 2 c bus control register (iccr) ......................................................................... 464 23.2.6 i 2 c bus status register (icsr)............................................................................ 471 23.2.7 serial/timer control register (stcr) ................................................................ 475 23.2.8 ddc switch register (ddcswr) ...................................................................... 476 23.2.9 module stop control regi ster (mstpcr) .......................................................... 478 23.3 operation...................................................................................................................... ..... 479 23.3.1 i 2 c bus data format ............................................................................................ 479 23.3.2 master transmit operation .................................................................................. 481 23.3.3 master receive operation.................................................................................... 483 23.3.4 slave receive operation...................................................................................... 485 23.3.5 slave transmit operation .................................................................................... 488 23.3.6 iric setting timing and scl control ................................................................ 489 23.3.7 automatic switching from formatless transfer to i 2 c bus format transfer...... 491 23.3.8 noise canceler ..................................................................................................... 492 23.3.9 sample flowcharts............................................................................................... 492 23.3.10 initializing internal status.................................................................................... 496 23.4 usage notes .................................................................................................................... .. 498 section 24 a/d converter ................................................................................................. 513 24.1 overview....................................................................................................................... .... 513 24.1.1 features................................................................................................................ 513 24.1.2 block diagram ..................................................................................................... 514 24.1.3 pin configuration................................................................................................. 515 rev.2.00 jan. 15, 2007 page xxxvi of xliv rej09b0329-0200 24.1.4 register configuration......................................................................................... 516 24.2 register descriptions ........................................................................................................ 5 17 24.2.1 software-triggered a/d result register (adr)................................................. 517 24.2.2 hardware-triggered a/d result register (ahr) ............................................... 517 24.2.3 a/d control register (adcr) ............................................................................ 518 24.2.4 a/d control/status register (adcsr) ............................................................... 521 24.2.5 trigger select register (adtsr)........................................................................ 524 24.2.6 port mode register 0 (pmr0) ............................................................................. 524 24.2.7 module stop control regi ster (mstpcr) .......................................................... 525 24.3 interface to bus master ..................................................................................................... 52 6 24.4 operation ...................................................................................................................... .... 527 24.4.1 software-triggered a/d conversion................................................................... 527 24.4.2 hardware- or external-tri ggered a/d conversion ............................................. 528 24.5 interrupt sources.............................................................................................................. . 529 section 25 address trap controller (atc) ................................................................. 531 25.1 overview....................................................................................................................... .... 531 25.1.1 features................................................................................................................ 531 25.1.2 block diagram..................................................................................................... 531 25.1.3 register configuration......................................................................................... 532 25.2 register descriptions ........................................................................................................ 5 32 25.2.1 address trap control register (atcr) .............................................................. 532 25.2.2 trap address register 2 to 0 (tar2 to tar0) ................................................... 533 25.3 precautions in usage......................................................................................................... 5 34 25.3.1 basic operations .................................................................................................. 534 25.3.2 enabling............................................................................................................... 536 25.3.3 bcc instruction..................................................................................................... 536 25.3.4 bsr instruction.................................................................................................... 540 25.3.5 jsr instruction..................................................................................................... 541 25.3.6 jmp instruction.................................................................................................... 543 25.3.7 rts instruction.................................................................................................... 544 25.3.8 sleep instruction ............................................................................................... 545 25.3.9 competing interrupt............................................................................................. 549 section 26 servo circuits .................................................................................................. 553 26.1 overview....................................................................................................................... .... 553 26.1.1 functions.............................................................................................................. 553 26.1.2 block diagram..................................................................................................... 554 26.2 servo port ..................................................................................................................... .... 556 26.2.1 overview.............................................................................................................. 556 rev.2.00 jan. 15, 2007 page xxxvii of xliv rej09b0329-0200 26.2.2 block diagram ..................................................................................................... 556 26.2.3 pin configuration................................................................................................. 558 26.2.4 register configuration......................................................................................... 560 26.2.5 register description............................................................................................. 560 26.2.6 dfg/dpg input signals ...................................................................................... 564 26.3 reference signal generators............................................................................................. 565 26.3.1 overview.............................................................................................................. 565 26.3.2 block diagram ..................................................................................................... 565 26.3.3 register configuration......................................................................................... 567 26.3.4 register description............................................................................................. 568 26.3.5 operation ............................................................................................................. 573 26.4 hsw (head-switch) ti ming generator ............................................................................ 588 26.4.1 overview.............................................................................................................. 588 26.4.2 block diagram ..................................................................................................... 588 26.4.3 hsw timing generator configuration................................................................ 590 26.4.4 register configuration......................................................................................... 591 26.4.5 register description............................................................................................. 591 26.4.6 operation ............................................................................................................. 606 26.4.7 interrupts.............................................................................................................. 612 26.4.8 cautions ............................................................................................................... 613 26.5 high-speed switching circuit for fo ur-head special playback ...................................... 614 26.5.1 overview.............................................................................................................. 614 26.5.2 block diagram ..................................................................................................... 615 26.5.3 pin configuration................................................................................................. 615 26.5.4 register description............................................................................................. 616 26.6 drum speed error detector .............................................................................................. 618 26.6.1 overview.............................................................................................................. 618 26.6.2 block diagram ..................................................................................................... 618 26.6.3 register configuration......................................................................................... 620 26.6.4 register description............................................................................................. 621 26.6.5 operation ............................................................................................................. 626 26.6.6 f h correction in trick play mode......................................................................... 628 26.7 drum phase error detector............................................................................................... 629 26.7.1 overview.............................................................................................................. 629 26.7.2 block diagram ..................................................................................................... 630 26.7.3 register configuration......................................................................................... 631 26.7.4 register description............................................................................................. 632 26.7.5 operation ............................................................................................................. 635 26.7.6 phase comparison................................................................................................ 637 26.8 capstan speed error detector........................................................................................... 637 rev.2.00 jan. 15, 2007 page xxxviii of xliv rej09b0329-0200 26.8.1 overview.............................................................................................................. 637 26.8.2 block diagram..................................................................................................... 638 26.8.3 register configuration......................................................................................... 639 26.8.4 register description............................................................................................. 640 26.8.5 operation ............................................................................................................. 645 26.9 capstan phase error detector ........................................................................................... 647 26.9.1 overview.............................................................................................................. 647 26.9.2 block diagram..................................................................................................... 647 26.9.3 register configuration......................................................................................... 649 26.9.4 register description............................................................................................. 650 26.9.5 operation ............................................................................................................. 653 26.10 x-value and tracking adjustment circuit ....................................................................... 655 26.10.1 overview.............................................................................................................. 655 26.10.2 block diagram..................................................................................................... 655 26.10.3 register description............................................................................................. 657 26.11 digital filters ................................................................................................................ .... 660 26.11.1 overview.............................................................................................................. 660 26.11.2 block diagram..................................................................................................... 661 26.11.3 arithmetic buffer................................................................................................. 663 26.11.4 register configuration......................................................................................... 664 26.11.5 register description............................................................................................. 665 26.11.6 filter character istics ............................................................................................ 673 26.11.7 operations in case of transient re sponse........................................................... 675 26.11.8 initialization of z -1 ................................................................................................ 675 26.12 additional v signal generator ......................................................................................... 677 26.12.1 overview.............................................................................................................. 677 26.12.2 pin configuration................................................................................................. 678 26.12.3 register configuration......................................................................................... 678 26.12.4 register description............................................................................................. 678 26.12.5 additional v pulse signal.................................................................................... 680 26.13 ctl circuit.................................................................................................................... ... 683 26.13.1 overview.............................................................................................................. 683 26.13.2 block diagram..................................................................................................... 684 26.13.3 pin configuration................................................................................................. 685 26.13.4 register configuration......................................................................................... 685 26.13.5 register description............................................................................................. 686 26.13.6 operation ............................................................................................................. 700 26.13.7 ctl input section ............................................................................................... 703 26.13.8 duty discriminator .............................................................................................. 706 26.13.9 ctl output section............................................................................................. 712 rev.2.00 jan. 15, 2007 page xxxix of xliv rej09b0329-0200 26.13.10 trapezoid waveform circuit.............................................................................. 715 26.13.11 note on ctl interrupt........................................................................................ 716 26.14 frequency dividers ........................................................................................................... 7 16 26.14.1 overview ............................................................................................................ 716 26.14.2 ctl frequency divider ..................................................................................... 716 26.14.3 cfg frequency divider ..................................................................................... 721 26.14.4 dfg noise removal circuit .............................................................................. 730 26.15 sync signal de tector......................................................................................................... 7 32 26.15.1 overview ............................................................................................................ 732 26.15.2 block diagram ................................................................................................... 733 26.15.3 pin configuration ............................................................................................... 734 26.15.4 register configuration ....................................................................................... 734 26.15.5 register description ........................................................................................... 734 26.15.6 noise detection .................................................................................................. 741 26.15.7 activation of the sync signal detector .............................................................. 744 26.16 servo interrupt ................................................................................................................ .. 744 26.16.1 overview ............................................................................................................ 744 26.16.2 register configuration ....................................................................................... 744 26.16.3 register description ........................................................................................... 745 section 27 sync separato r for osd and data slicer ................................................ 751 27.1 overview....................................................................................................................... .... 751 27.1.1 features .............................................................................................................. 752 27.1.2 block diagram ................................................................................................... 752 27.1.3 pin configur ation ............................................................................................... 754 27.1.4 register c onfiguratio n ....................................................................................... 754 27.2 register description.......................................................................................................... 755 27.2.1 sync separation input mode register (sepimr) .............................................. 755 27.2.2 sync separation control register (sepcr)....................................................... 760 27.2.3 sync separation af c control register (sepacr) ........................................... 763 27.2.4 horizontal sync signal thres hold register (hvthr) ...................................... 765 27.2.5 vertical sync signal thres hold register (vvthr) .......................................... 769 27.2.6 field detection window register (fwidr) ...................................................... 772 27.2.7 h complement and mask timi ng register (hcmmr) ..................................... 774 27.2.8 noise detection counter (ndetc) ................................................................... 776 27.2.9 noise detection level register (ndetr) ......................................................... 777 27.2.10 data slicer detection window register (ddetwr) ........................................ 778 27.2.11 internal sync frequency register (infrqr) .................................................... 780 27.3 operation...................................................................................................................... ..... 781 27.3.1 selecting source signals fo r sync separation.................................................... 781 rev.2.00 jan. 15, 2007 page xl of xliv rej09b0329-0200 27.3.2 vsync separation ................................................................................................. 787 27.3.3 hsync separation ................................................................................................. 788 27.3.4 field detection..................................................................................................... 789 27.3.5 noise detection.................................................................................................... 789 27.3.6 automatic frequency controller (afc) .............................................................. 790 27.3.7 module stop control regi ster (mstpcr) .......................................................... 795 section 28 data slicer ........................................................................................................ 797 28.1 overview....................................................................................................................... .... 797 28.1.1 features................................................................................................................ 797 28.1.2 block diagram..................................................................................................... 798 28.1.3 pin configuration................................................................................................. 799 28.1.4 register configuration......................................................................................... 800 28.1.5 data slicer use conditions .................................................................................. 800 28.2 register description.......................................................................................................... 801 28.2.1 slice even- (odd-) field mode register (sevfd, sodfd) .............................. 801 28.2.2 slice line setting registers 1 to 4 (sline1 to sline4).................................... 805 28.2.3 slice detection registers 1 to 4 (sdtct1 to sdtct4) ..................................... 807 28.2.4 slice data registers 1 to 4 (sdata1 to sdata4)............................................ 810 28.2.5 module stop control regi ster (mstpcr) .......................................................... 811 28.2.6 monitor output setting register (dout) ........................................................... 812 28.3 operation ...................................................................................................................... .... 813 28.3.1 slice line speci fication ....................................................................................... 813 28.3.2 slice sequence ..................................................................................................... 816 28.4 32-bit slice op eration ...................................................................................................... 81 7 section 29 on-screen display (osd) ........................................................................... 821 29.1 overview....................................................................................................................... .... 821 29.1.1 features................................................................................................................ 821 29.1.2 block diagram..................................................................................................... 823 29.1.3 pin configuration................................................................................................. 824 29.1.4 register configuration......................................................................................... 825 29.1.5 tv formats and display modes .......................................................................... 826 29.2 description of disp lay functions...................................................................................... 826 29.2.1 superimposed mode and text display mode...................................................... 826 29.2.2 character configuration....................................................................................... 827 29.2.3 on-screen display configuration........................................................................ 828 29.3 settings in character units ............................................................................................... 829 29.3.1 character configuration....................................................................................... 829 29.3.2 character colors .................................................................................................. 829 rev.2.00 jan. 15, 2007 page xli of xliv rej09b0329-0200 29.3.3 halftones/cursors ................................................................................................ 830 29.3.4 blinking ............................................................................................................... 831 29.3.5 button display ..................................................................................................... 832 29.3.6 character data rom (osdrom)....................................................................... 833 29.3.7 display data ram (osdram).......................................................................... 835 29.4 settings in row units ....................................................................................................... 84 0 29.4.1 button patterns..................................................................................................... 840 29.4.2 display enlargement............................................................................................ 840 29.4.3 character brightness ............................................................................................ 840 29.4.4 cursor color, brightness, halftone levels .......................................................... 840 29.4.5 row registers (clinen, n = rows 1 to 12)......................................................... 842 29.5 settings in screen units .................................................................................................... 84 7 29.5.1 display positions ................................................................................................. 847 29.5.2 turning the osd display on and off ................................................................. 848 29.5.3 display method.................................................................................................... 848 29.5.4 blinking period .................................................................................................... 848 29.5.5 borders................................................................................................................. 849 29.5.6 background color an d brightne ss ....................................................................... 849 29.5.7 character, cursor, and background chroma saturation...................................... 849 29.5.8 display position register s (hpos and vpos).................................................... 850 29.5.9 screen control register (dcntl) ...................................................................... 851 29.6 other settings................................................................................................................. ... 857 29.6.1 tv format............................................................................................................ 857 29.6.2 display data ram control ................................................................................. 857 29.6.3 timing of osd display updates using register rewriting................................ 857 29.6.4 4fsc/2fsc ............................................................................................................... 858 29.6.5 osdv interrupts .................................................................................................. 858 29.6.6 osd format register (dform) ......................................................................... 858 29.7 digital output ................................................................................................................. .. 862 29.7.1 r, g, and b outputs............................................................................................. 862 29.7.2 yco and ybo outputs ....................................................................................... 865 29.7.3 digital output specificati on register (dout) ................................................... 866 29.7.4 module stop control regi ster (mtstpcr)........................................................ 868 29.8 notes on osd font creation ............................................................................................ 870 29.8.1 note 1 on font creation (font width)................................................................. 870 29.8.2 note 2 on font creation (borders)....................................................................... 870 29.8.3 note 3 on font creation (blinking) ..................................................................... 872 29.8.4 note 4 on font creation (buttons)....................................................................... 873 29.9 osd oscillator, afc, and dot clock ............................................................................... 874 29.9.1 sync signals......................................................................................................... 874 rev.2.00 jan. 15, 2007 page xlii of xliv rej09b0329-0200 29.9.2 afc circuit.......................................................................................................... 874 29.9.3 dot clock............................................................................................................. 874 29.9.4 4/2fsc.................................................................................................................... 875 29.10 osd operation in cpu operation modes ........................................................................ 877 29.11 character data rom (osdrom) access by cpu.......................................................... 878 29.11.1 serial timer control register (stcr) ................................................................ 878 section 30 power supply circuit .................................................................................... 879 30.1 overview....................................................................................................................... .... 879 30.2 power supply connection (internal power supply step-down circuit on-chip) ........... 879 section 31 electrical characteristics ............................................................................. 881 31.1 absolute maximum ratings ............................................................................................. 881 31.2 electrical characteristics of HD6432199R, hd6432198r, hd6432197r, and hd6432196r .................................................................................................................... 882 31.2.1 dc characteristics of HD6432199R, hd6432198r, hd6432197r, and hd6432196r ....................................................................................................... 882 31.2.2 allowable output currents of HD6432199R, hd6432198r, hd6432197r, and hd643219 6r ................................................................................................ 889 31.2.3 ac characteristics of HD6432199R, hd6432198r, hd6432197r, and hd6432196r ....................................................................................................... 890 31.2.4 serial interface timing of hd 6432199r, hd6432198r, hd6432197r, and hd6432196r ....................................................................................................... 893 31.2.5 a/d converter characteristics of HD6432199R, hd6432198r, hd6432197r, and hd643219 6r ................................................................................................ 897 31.2.6 servo section electrical characteristics of HD6432199R, hd6432198r, hd6432197r, and hd 6432196r ........................................................................ 898 31.2.7 osd electrical characteristics of HD6432199R, hd6432198r, hd6432197r, and hd643219 6r ................................................................................................ 901 31.3 electrical characteristics of hd6432197s and hd 6432196s .......................................... 905 31.3.1 dc characteristics of hd6432197s and hd6432196s ? preliminary ? ......... 905 31.3.2 allowable output currents of hd6432197s and hd6432196s ......................... 911 31.3.3 ac characteristics of hd 6432197s and hd6 432196s ....................................... 912 31.3.4 serial interface timing of hd6432197s and hd6432196s................................ 915 31.3.5 a/d converter characteristics of hd6432197s and hd6432196s .................... 919 31.3.6 servo section electrical characteristics of hd6432197s and hd6432196s...... 920 31.3.7 osd electrical characteristics of hd6432197s and hd6432196s.................... 923 31.4 electrical characteris tics of hd 64f2199r ....................................................................... 927 31.4.1 dc characteristics of hd64f 2199r ................................................................... 927 31.4.2 allowable output curre nts of hd 64f2199r ...................................................... 934 rev.2.00 jan. 15, 2007 page xliii of xliv rej09b0329-0200 31.4.3 ac characteristics of hd64f 2199r ................................................................... 935 31.4.4 serial interface timing of hd64f2199r............................................................. 938 31.4.5 a/d converter characteris tics of hd64f 2199r ................................................. 942 31.4.6 servo section electrical characteristics of hd64f2199r................................... 943 31.4.7 osd electrical characteristics of hd64f2199r................................................. 946 31.4.8 flash memory characteristics ............................................................................. 950 appendix a instruction set .............................................................................................. 953 a.1 instructions................................................................................................................... ..... 953 a.2 instruction codes .............................................................................................................. 964 a.3 operation code map......................................................................................................... 974 a.4 number of execution states.............................................................................................. 978 a.5 bus status during instruction execution........................................................................... 988 a.6 change of cond ition code s ............................................................................................ 1002 appendix b internal i/o registers ............................................................................... 1007 b.1 addresses ...................................................................................................................... .. 1007 b.2 function list .................................................................................................................. . 1017 appendix c pin circuit diagrams ................................................................................ 1148 c.1 pin circuit diagrams....................................................................................................... 114 8 appendix d port states in each processing state .................................................... 1162 d.1 pin circuit diagrams....................................................................................................... 116 2 appendix e usage notes ................................................................................................. 1163 e.1 power supply rise a nd fall order.................................................................................. 1163 e.2 sample external circuits................................................................................................. 1166 e.3 handling of pins when osd is not used ...................................................................... 1171 appendix f product lineup ........................................................................................... 1172 appendix g package dimensions ................................................................................ 1173 rev.2.00 jan. 15, 2007 page xliv of xliv rej09b0329-0200 section 1 overview rev.2.00 jan. 15, 2007 page 1 of 1174 rej09b0329-0200 section 1 overview 1.1 overview the h8s/2199r group comprises microcomputer s (mcus) built around the h8s/2000 cpu, adopting renesas technology proprietary architecture, and equipped with on-chip supporting modules. the h8s/2000 has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16- mbyte linear address space. the h8s/2199r group is equipped with a digital servo circuit, sync separator, osd, data slicer, rom, ram, seven types of timers, three types of pwm, two types of serial communication interface, an i 2 c bus interface, a/d converter, and i/ o port as on-chip supporting modules. the on-chip rom is either flash memory (f-ztat ? *) or mask rom, with a capacity of 256, 128, 112, 96, or 80 kbytes. rom is connected to the cpu via a 16-bit data bus, enabling both byte and word data to be accessed in one state. in struction fetching has been speeded up, and processing speed increased. using the h8s/2199r group can implement a system suitable for vtr control. this manual describes the h8s/2199r group hardware. for details on instructions, see the h8s/2600 and h8s/2000 series software manual. note: * f-ztat is a trademark of renesas technology corp. section 1 overview rev.2.00 jan. 15, 2007 page 2 of 1174 rej09b0329-0200 table 1.1 features of the h8s/2199r group item specifications cpu ? general-register architecture ? sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) ? high-speed operation suitable for real-time control ? maximum operating frequency: 10 mhz/4 v to 5.5 v ? high-speed arithmetic operations 8/16/32-bit register-register add/subtract: 100 ns (10-mhz operation) 16 16-bit register-register multiply: 2000 ns (10-mhz operation) 32 16-bit register-register divide: 2000 ns (10-mhz operation) ? instruction set suitable for high-speed operation ? sixty-five basic instructions ? 8/16/32-bit transfer/arithmetic and logic instructions ? unsigned/signed multiply and divide instructions ? powerful bit-manipulation instructions ? cpu operating modes ? advanced mode: 16-mbyte address space timer ? seven types of timer are incorporated ? timer a ? 8-bit interval timer ? clock source can be selected among 8 types of internal clock of which frequencies are divided from the system clock ( ) and subclock ( sub) ? functions as clock time base by subclock input ? timer b ? functions as 8-bit interval timer or reload timer ? clock source can be selected among 7 types of internal clock or external event input ? timer j ? functions as two 8-bit down counters or one 16-bit down counter (reload timer/event counter timer/timer output, etc., 5 types of operation modes) ? remote controlled transmit function ? take up/supply reel pulse frequency division section 1 overview rev.2.00 jan. 15, 2007 page 3 of 1174 rej09b0329-0200 item specifications timer ? timer l ? 8-bit up/down counter ? clock source can be selected among 2 types of internal clock, cfg frequency division signal, and pb and rec-ctl (control pulse) ? compare-match clearing function/auto reload function ? timer r ? three reload timers ? mode discrimination ? reel control ? capstan motor acceleration/deceleration detection function ? slow tracking mono-multi ? timer x1 (except for the h8s/2197s and h8s/2196s) ? 16-bit free-running counter ? clock source can be selected among 3 types of internal clock and dvcfg ? two output compare outputs ? four input capture inputs ? watchdog timer ? functions as watchdog timer or 8-bit interval timer ? generates reset signal or nmi at overflow prescaler unit ? divides system clock frequency and generates frequency division clock for supporting module functions ? divides subclock frequency and generates input clock for timer a (clock time base) ? generates 8-bit pwm frequency and duty period ? 8-bit input capture at external signal edge ? frequency division clock output enabled pwm ? three types of pwm are incorporated ? 14-bit pwm: pulse resolution type 1 channel (except for the h8s/2197s and h8s/2196s) ? 8-bit pwm: duty control type 4 channels (h8s/2197s and h8s/2196s : 2 channel) ? 12-bit pwm: pulse pitch control type 2 channels section 1 overview rev.2.00 jan. 15, 2007 page 4 of 1174 rej09b0329-0200 item specifications serial communication interface (sci) ? asynchronous mode or synchronous mode selectable ? desired bit rate selectable with built-in baud rate generator ? multiprocessor communication function i 2 c bus interface (2 channels) (h8s/2197s and h8s/2196s : 1 channel) ? conforms to phillips i 2 c bus interface standard ? start and stop conditions generated automatically ? selection of acknowledge output levels when receiving, and automatic loading of acknowledge bit when transmitting ? selection of acknowledgement mode or serial mode (without acknowledge bit) a/d converter ? resolution: 10 bits ? input: 12 channels ? high-speed conversion: 13.4 s minimum conversion time (10-mhz operation) ? sample-and-hold function ? a/d conversion can be activated by software or external trigger address trap controller ? interrupt occurs when the preset address is found during bus cycle ? to-be-trapped addresses can be individually set at three different locations i/o port ? 56 input/output pins ? 8 input-only pins ? can be switched for each supporting module servo circuit ? digital servo circuits on-chip ? input and output circuits ? error detection circuit ? phase and gain compensation sync signal (servo) ? on-chip sync signal detection circuit ? can separately detect horizontal and vertical sync signals ? noise detection function sync separator for osd and data slicer ? sync separator including afc ? horizontal and vertical sync signals separated from the composite video signal ? noise detection ? selection of sync separation methods section 1 overview rev.2.00 jan. 15, 2007 page 5 of 1174 rej09b0329-0200 item specifications osd (on screen display) ? screen of 32 characters 12 lines ? 384 types of characters (h8s/2199r f-ztat: 512 types of characters h8s/2197s and h8s/2196s: 256 types of characters) ? character configuration: 12 dots 18 lines ? character colors: eight hues ? background colors: eight hues ? cursor colors: eight hues ? halftone display ? button display data slicer ? slice lines: four lines (h8s/2197s and h8s/2196s: two lines) ? slice levels: seven levels ? sampling clock generated by afc ? slice interrupt ? error detection ? flash memory or mask rom (refer to the product line-up) ? high-speed static ram product name rom ram h8s/2199r 128 k (256 k * ) bytes 4 k (8 k * ) bytes h8s/2198r 112 k bytes 4 k bytes h8s/2197r 96 k bytes h8s/2196r 80 k bytes 4 k bytes h8s/2197s 96 k bytes h8s/2196s 80 k bytes 3 k bytes memory power-down state ? medium-speed mode ? sleep mode ? module stop mode ? standby mode ? subclock operation subactive mode, watch mode, subsleep mode interrupt controller ? six external interrupt pins ( irq5 to irq0 ) ? 44 internal interrupt sources (h8s/2197s and h8s/2196s : 35 internal interrupt sources) ? three priority levels settable section 1 overview rev.2.00 jan. 15, 2007 page 6 of 1174 rej09b0329-0200 item specifications clock pulse generator ? two types of clock pulse generator on-chip ? system clock pulse generator: 8 to 10 mhz ? subclock pulse generator: 32.768 khz packages ? 112-pin plastic qfp (prqp0112ja-a) part no. group mask rom versions f-ztat versions rom/ram (bytes) packages h8s/2199r HD6432199R hd64f2199r 128 k/4 k (256 k * / 8 k * ) prqp0112ja-a hd6432198r ? 112 k/4 k prqp0112ja-a hd6432197r ? 96 k/4 k prqp0112ja-a hd6432196r ? 80 k/4 k prqp0112ja-a hd6432197s ? 96 k/3 k prqp0112ja-a hd6432196s ? 80 k/3 k prqp0112ja-a product lineup note: * f-ztat version section 1 overview rev.2.00 jan. 15, 2007 page 7 of 1174 rej09b0329-0200 1.2 internal block diagram figure 1.1 shows an internal block diagram of the h8s/2199r group. p23/sda1 p25/sda0 p22/sck1 p26/scl0 p21/so1 p27/synci p20/si1 p24/scl1 v ss vcl v ss v cc v ss v cc md0 res osc2 osc1 x2 x1 hsync(csync) sync si g nal detection ov cc ov ss sv ss sv cc cappwm ctl(+) ctlsmt(i) ctlbias cvin2 csync/hsync vlpf/vsync ctl(?) audio ff video ff vpulse ctl fb ctl ref ctlamp(o) dfg cfg drmpwm dpg p13/ irq3 p15/ irq5 p12/ irq2 interrupt controller r a m r o m internal data bus external data bus external address bus external data bus external address bus internal address bus servo pins (ctl input/output amplifier, three-level output, etc.) cvin1 cvout osd (analo g input/output) sync separation sub-carrier oscillator afc h8s/2000 cpu bus controller address trap controller p16/ ic p11/ irq1 p17/tmow p10/ irq0 p14/ irq4 p03/an3 p05/an5 p02/an2 p06/an6 p01/an1 p07/an7 p00/an0 p04/an4 ana an9 an8 anb av cc av ss p83/c.rotary/r p85/comp/b p82/exctl p86/exttrg p81/excap/ybo p87/dpg p80/yco p84/h.amp sw/g p33/pwm1 p35/pwm3 p32/pwm0 p36/buzz p31/sv2 p37/tmo p30/sv1 p34/pwm2 p43/ftic p45/ftoa p42/ftib p46/ftob p41/ftia p47/rptrg p40/pwm14 p44/ftid p73/ppg3 p75/ppg5/rp9 p72/ppg2 p76/ppg6/rpa p71/ppg1 p77/ppg7/rpb p70/ppg0 p74/ppg4/rp8 4fscout/2fscout afc pc afc osc afc lpf 4fscin/2fscin p63/rp3 p65/rp5 p62/rp2 p66/rp6/ adtrg p61/rp1 p67/rp7/tmbi p60/rp0 p64/rp4 14-bit pwm 12-bit pwm 8-bit pwm prescaler unit watchdo g timer timer l timer a sci1 timer b timer j i 2 c bus interface timer r a/d converter timer x1 port 7 port 6 port 4 port 3 port 2 port 1 port 0 port 8 analo g port subclock pulse g enerator subclock pulse pulse g enerator servo circuit data slicer osd figure 1.1 internal block diagram of h8s/2199r group (except for the h8s/2197s and h8s/2196s) section 1 overview rev.2.00 jan. 15, 2007 page 8 of 1174 rej09b0329-0200 figure 1.2 shows an internal block diagram of the h8s/2197s and h8s/2196s. p23/sda1 p25 p22/sck1 p26 p21/so1 p27 p20/si1 p24/scl1 v ss vcl v ss v cc v ss v cc md0 res osc2 osc1 x2 x1 hsync(csync) sync si g nal detection ov cc ov ss sv ss sv cc cappwm ctl(+) ctlsmt(i) ctlbias cvin2 csync/hsync vlpf/vsync ctl(?) audio ff video ff vpulse ctl fb ctl ref ctlamp(o) dfg cfg drmpwm dpg p13/ irq3 p15/ irq5 p12/ irq2 interrupt controller r a m r o m internal data bus external data bus external address bus external data bus external address bus internal address bus servo pins (ctl input/output amplifier, three-level output, etc.) cvin1 cvout osd (analo g input/output) sync separation sub-carrier oscillator afc h8s/2000 cpu bus controller address trap controller p16/ ic p11/ irq1 p17/tmow p10/ irq0 p14/ irq4 p03/an3 p05/an5 p02/an2 p06/an6 p01/an1 p07/an7 p00/an0 p04/an4 ana an9 an8 anb av cc av ss p83/c.rotary/r p85/comp/b p82/exctl p86/exttrg p81/excap/ybo p87/dpg p80/yco p84/h.amp sw/g p33/pwm1 p35 p32/pwm0 p36/buzz p31/sv2 p37/tmo p30/sv1 p34 p43 p45 p42 p46 p41 p47/rptrg p40 p44 p73/ppg3 p75/ppg5/rp9 p72/ppg2 p76/ppg6/rpa p71/ppg1 p77/ppg7/rpb p70/ppg0 p74/ppg4/rp8 4fscout/2fscout afc pc afc osc afc lpf 4fscin/2fscin p63/rp3 p65/rp5 p62/rp2 p66/rp6/ adtrg p61/rp1 p67/rp7/tmbi p60/rp0 p64/rp4 12-bit pwm 8-bit pwm prescaler unit watchdo g timer timer l timer a sci1 timer b timer j i 2 c bus interface timer r a/d converter port 7 port 6 port 4 port 3 port 2 port 1 port 0 port 8 analo g port subclock pulse g enerator subclock pulse pulse g enerator servo circuit data slicer osd figure 1.2 internal block diagram of the h8s/2197s and h8s/2196s section 1 overview rev.2.00 jan. 15, 2007 page 9 of 1174 rej09b0329-0200 1.3 pin arrangement and functions 1.3.1 pin arrangement figure 1.3 shows the pin arrangement of the h8s/2199r group. p33/pwm1 p34/pwm2 md0 vcl osc2 v ss osc1 res x1 x2 fwe p40/pwm14 p41/ftia p42/ftib p43/ftic p44/ftid p45/ftoa p46/ftob p47/rptrg p21/so1 p20/si1 p22/sck1 p23/sda1 p24/scl1 p25/sda0 p26/scl0 p27/synci v ss p32/pwm0 p31/sv2 p30/sv1 p70/ppg0 p71/ppg1 p72/ppg2 p73/ppg3 p74/ppg4/rp8 p75/ppg5/rp9 p76/ppg6/rpa p77/ppg7/rpb p80/yco p81/excap/ybo p82/exctl p83/c.rotary/r p84/h.amp sw/g p85/comp/b p86/exttrg p87/dpg dfg video ff audio ff drm pwm cap pwm vpulse v ss csync v cc v cc p35/pwm3 p36/buzz p37/tmo p60/rp0 p61/rp1 p62/rp2 p63/rp3 p64/rp4 p65/rp5 p66/rp6/ adtr g p67/rp7/tmbi p17/tmow p16/ ic p15/ irq5 p14/ irq4 p13/ irq3 p12/ irq2 p11/ irq1 p10/ irq0 av cc p00/an0 p01/an1 p02/an2 p03/an3 p04/an4 p05/an5 p06/an6 1 sv ss prqp0112ja-a (top view) 84 2 ctlref 83 3 ctl(+) 82 4 ctl(?) 81 5 ctlbias 80 6 ctlfb 79 7 ctlamp(o) 78 8 ctlsmt(i) 77 9 cfg 76 10 sv cc 75 11 afcpc 74 12 afcosc 73 13 afclpf 72 14 csync/hsync 71 15 vlpf/vsync 70 16 cvin2 69 17 cvin1 68 18 ov cc 67 19 cvout 66 20 ov ss 65 21 4fscout/2fscout 64 22 4fscin/2fscin 63 23 av ss 62 24 anb 61 25 ana 60 26 an9 59 27 an8 58 28 p07/an7 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 figure 1.3 pin arrangement of h8s/2199r group (except for the h8s/2197s and h8s/2196s) section 1 overview rev.2.00 jan. 15, 2007 page 10 of 1174 rej09b0329-0200 figure 1.4 shows the pin arrangement of the h8s/2197s and h8s/2196s. p33/pwm1 p34 md0 vcl osc2 v ss osc1 res x1 x2 nc p40 p41 p42 p43 p44 p45 p46 p47/rptrg p21/so1 p20/si1 p22/sck1 p23/sda1 p24/scl1 p25 p26 p27 v ss p32/pwm0 p31/sv2 p30/sv1 p70/ppg0 p71/ppg1 p72/ppg2 p73/ppg3 p74/ppg4/rp8 p75/ppg5/rp9 p76/ppg6/rpa p77/ppg7/rpb p80/yco p81/excap/ybo p82/exctl p83/c.rotary/r p84/h.amp sw/g p85/comp/b p86/exttrg p87/dpg dfg video ff audio ff drm pwm cap pwm vpulse v ss csync v cc v cc p35 p36/buzz p37/tmo p60/rp0 p61/rp1 p62/rp2 p63/rp3 p64/rp4 p65/rp5 p66/rp6/ adtr g p67/rp7/tmbi p17/tmow p16/ ic p15/ irq5 p14/ irq4 p13/ irq3 p12/ irq2 p11/ irq1 p10/ irq0 av cc p00/an0 p01/an1 p02/an2 p03/an3 p04/an4 p05/an5 p06/an6 1 sv ss prqp0112ja-a (top view) 84 2 ctlref 83 3 ctl(+) 82 4 ctl(?) 81 5 ctlbias 80 6 ctlfb 79 7 ctlamp(o) 78 8 ctlsmt(i) 77 9 cfg 76 10 sv cc 75 11 afcpc 74 12 afcosc 73 13 afclpf 72 14 csync/hsync 71 15 vlpf/vsync 70 16 cvin2 69 17 cvin1 68 18 ov cc 67 19 cvout 66 20 ov ss 65 21 4fscout/2fscout 64 22 4fscin/2fscin 63 23 av ss 62 24 anb 61 25 ana 60 26 an9 59 27 an8 58 28 p07/an7 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 figure 1.4 pin arrangement of h8s/2197s and h8s/2196s section 1 overview rev.2.00 jan. 15, 2007 page 11 of 1174 rej09b0329-0200 1.3.2 pin functions table 1.2 summarizes the functions of the h8s/2199r group pins. table 1.2 pin functions type symbol pin no. i/o name and function v cc 56, 112 input power supply: all vcc pins should be connected to the system power supply (+5 v) v ss 57, 79, 110 input ground: all vss pins should be connected to the system power supply (0 v) sv cc 10 input servo power supply: svcc pin should be connected to the servo analog power supply (+5 v) sv ss 1 input servo ground: svss pin should be connected to the servo analog power supply (0 v) av cc 36 input analog power supply: power supply pin for a/d converter. it should be connected to the system power supply (+5 v) when the a/d converter is not used av ss 23 input analog ground: ground pin for a/d converter. it should be connected to the system power supply (0 v) ov cc 18 input osd power supply: ov cc should be connected to the osd analog power supply (+5 v) ov ss 20 input osd ground: ov ss should be connected to the osd analog power supply (0 v) power supply v cl 81 input smoothing capacitor connection: connect 0.1-f power-smoothing capacitance between v cl and v ss clock osc1 78 input osc2 80 output connected to a crystal oscillator. it can also input an external clock. see section 9, clock pulse generator, for typical connection diagrams for a crystal oscillator and external clock input x1 76 input x2 75 output connected to a 32.768 khz crystal oscillator. see section 9, clock pulse generator, for typical connection diagrams section 1 overview rev.2.00 jan. 15, 2007 page 12 of 1174 rej09b0329-0200 type symbol pin no. i/o name and function operating mode control md0 82 input mode pin: this pin sets the operating mode. this pin should not be changed while the mcu is in operation res 77 input reset input: when this pin is driven low, the chip is reset system control fwe 74 input flash memory enable: enables/disables flash memory programming. this pin is available only with mcu with flash memory on-chip. irq0 37 input external interrupt request 0: external interrupt input pin for which rising edge sense, falling edge sense or both edges sense are selectable interrupts irq1 irq2 irq3 irq4 irq5 38 39 40 41 42 input external interrupt requests 1 to 5: external interrupt input pins for which rising or falling edge sense are selectable ic 43 input input capture input: input capture input pin for prescaler unit prescaler unit tmow 44 output frequency division clock output: output pin for clock of which frequency is divided by prescaler timers tmbi 45 input timer b event input: input pin for events to be input to timer b counter irq1 irq2 38 39 input timer j event input: input pin for events to be input to timer j rdt- 1or rdt-2 counter tmo 53 output timer j timer output: output pin for toggle at underflow of rdt-1 of timer j, or remote controlled transmit data buzz 54 output timer j buzzer output: output pin for toggle which is selectable among fixed frequency, 1 hz frequency divided from subclock (32 khz), and frequency division ctl signal section 1 overview rev.2.00 jan. 15, 2007 page 13 of 1174 rej09b0329-0200 type symbol pin no. i/o name and function irq3 40 input timer r input capture: input pin for input capture of timer r tmru-1 or tmru-2 ftoa * ftob * 68 67 output timer x1 output compare a and b output: output pin for output compare a and b of timer x1 timers ftia * ftib * ftic * ftid * 72 71 70 69 input timer x1 input capture a, b, c and d input: input pin for input capture a, b, c and d of timer x1 pwm0 pwm1 pwm2 * pwm3 * 85 84 83 55 output 8-bit pwm square waveform output: output pin for waveform generated by 8-bit pwm 0, 1, 2 and 3 pwm pwm14 * 73 output 14-bit pwm square waveform output: output pin for waveform generated by 14-bit pwm sck1 63 input /output sci clock input/output: clock input pins for sci 1 si1 65 input sci receive data input: receive data input pins for sci 1 serial commu- nication interface (sci) so1 64 output sci transmit data output: transmit data output pins for sci 1 i 2 c bus interface scl0 * scl1 59 61 input /output i 2 c bus interface clock input/output: clock input/output pin for i 2 c bus interface sda0 * sda1 60 62 input /output i 2 c bus interface data input/output: data input/output pin for i 2 c bus interface synci * 58 input i 2 c bus interface clock input: i 2 c formatless serial clock input section 1 overview rev.2.00 jan. 15, 2007 page 14 of 1174 rej09b0329-0200 type symbol pin no. i/o name and function an7 to an0 28 to 35 input analog input channels 7 to 0: analog data input pins. a/d conversion is started by a software triggering an8 an9 ana anb 27 26 25 24 input analog input channels 8, 9, a and b: analog data input pins. a/d conversion is started by an external trigger, a hardware trigger, or software a/d converter adtrg 46 input a/d conversion external trigger input: a/d conversion for analog data input pins 8, 9, a, and b is started by an external trigger servo circuits audio ff 106 output audio ff: output pin for audio head switching signal video ff 105 output video ff: output pin for video head switching signal cappwm 108 output capstan mix: 12-bit pwm output pin giving result of capstan speed error and phase error after filtering drmpwm 107 output drum mix: 12-bit pwm output pin giving result of drum speed error and phase error after filtering vpulse 109 output additional v pulse: three-level output pin for additional v signal synchronized to the video ff signal c.rotary 99 output color rotary signal: output pin for color signal processing control signal in four-head special-effects playback h.ampsw 100 output head-amp switch: output pin for preamplifier output select signal in four-head special-effects playback. comp 101 input compare input: input pin for signal giving the result of preamplifier output comparison in four-head special-effects playback. ctl (+) ctl (-) 3 4 input /output ctl head (+) and (-) pins: i/o pins for ctl signals ctl bias 5 input ctl primary amp bias supply: bias supply pin for ctl primary amp section 1 overview rev.2.00 jan. 15, 2007 page 15 of 1174 rej09b0329-0200 type symbol pin no. i/o name and function ctl amp (o) 7 output ctl amp output: output pin for ctl amp ctl smt (i) 8 input ctl schmitt amp input: input pin for ctl schmitt amp ctlfb 6 input clt feedback input: input pin for ctl amp high-range characteristics control ctlref 2 output ctl amp reference voltage output: output pin for 1/2 vcc (sv) cfg 9 input capstan fg input: schmitt comparator input pin for cfg signal dfg 104 input drum fg input: schmitt input pin for dfg signal dpg 103 input drum pg input: schmitt input pin for dpg signal exctl 98 input external ctl input: input pin for external ctl signal csync 111 input mixed sync signal input: input pin for mixed sync signal excap 97 input capstan external sync signal input: signal input pin for external synchronization of capstan phase control exttrg 102 input external trigger signal input: signal input pin for synchronization with reference signal generator sv1 87 output servo monitor output pin 1: output pin for servo module internal signal sv2 86 output servo monitor output pin 2: output pin for servo module internal signal servo circuits ppg7 to ppg0 95 to 88 output ppg: output pin for hsw timing generator. to be used when head switching is required as well as audio ff and video ff section 1 overview rev.2.00 jan. 15, 2007 page 16 of 1174 rej09b0329-0200 type symbol pin no. i/o name and function csync/ hsync 14 input/ output sync signal input/output: composite sync signal input/output or horizontal sync signal input vlpf/ vsync 15 input sync signal input: pin for connecting external lpf for vertical sync signal or input pin for vertical sync signal afc pc 11 input/ output afc oscillation: pin for connecting external circuit for afc oscillation afc osc 12 input/ output afc oscillation: pin for connecting external circuit for afc oscillation afc lpf 13 input/ output pin for connecting external lpf for afc 4 fsc in/ 2 fsc in 22 input fsc oscillation: input pin for subcarrier oscillator. 4fsc or 2fsc can be selected fsc: subcarrier frequency 4 fsc out/ 2 fsc out 21 output fsc oscillation: output pin for subcarrier oscillator. 4fsc or 2fsc can be selected fsc: subcarrier frequency sync separator cvin2 16 input composite video input: composite video signal input. input 2-vp-p composite video signal, and the sync tip of the signal is clamped to about 2.0 v osd cvin1 17 input composite video input: composite video signal input for osd. input 2- vp-p composite video signal, and the sync tip of the signal is clamped to about 1.4 v cvout 19 output composite video output: composite video signal output for osd. 2-vp-p composite video signal is output r 99 output osd digital output: color signal r output g 100 output osd digital output: color signal g output b 101 output osd digital output: color signal b output section 1 overview rev.2.00 jan. 15, 2007 page 17 of 1174 rej09b0329-0200 type symbol pin no. i/o name and function osd yco 96 output osd digital output: character data output ybo 97 output osd digital output: character display position output data slicer cvin2 16 input composite video input: composite video signal input. input 2-vp-p composite video signal, and the sync tip of the signal is clamped to about 2.0 v. i/o port p07 to p00 28 to 35 input port 0: 8-bit input pins p17 to p10 44 to 37 input /output port 1: 8-bit i/o pins p27 to p20 58 to 65 input /output port 2: 8-bit i/o pins p37 to p30 53 to 55 83 to 87 input /output port 3: 8-bit i/o pins p47 to p40 66 to 73 input /output port 4: 8-bit i/o pins p67 to p60 45 to 52 input /output port 6: 8-bit i/o pins p77 to p70 95 to 88 input /output port 7: 8-bit i/o pins p87 to p80 103 to 96 input /output port 8: 8-bit i/o pins rp7 to rp0 45 to 52 output realtime output port: 8-bit realtime output pins rpb to rp8 95 to 92 output realtime output port: 4-bit realtime output pins rptrg 66 input realtime output port trigger input: input pin for realtime output port trigger note: * not available in the h8s/2197s or h8s/2196s. section 1 overview rev.2.00 jan. 15, 2007 page 18 of 1174 rej09b0329-0200 section 2 cpu rev.2.00 jan. 15, 2007 page 19 of 1174 rej09b0329-0200 section 2 cpu 2.1 overview the h8s/2000 cpu is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the h8/300 and h8/300h cpus. the h8s/2000 cpu has sixteen 16-bit general registers, can address a 16-mbyte (archit ecturally 4-gbyte) linear address space, and is ideal for realtime control. 2.1.1 features the h8s/2000 cpu has the following features. ? upward-compatible with h8/300 and h8/300h cpus can execute h8/300 and h8/300h object programs ? general-register architecture sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) ? sixty-five basic instructions 8/16/32-bit arithmetic and logic instructions multiply and divide instructions powerful bit-manipulation instructions ? eight addressing modes register direct [rn] register indirect [@ern] register indirect with displacemen t [@(d:16,ern) or @(d:32,ern)] register indirect with post-increment or pre-decrement [@ern+ or @-ern] absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] immediate [#xx:8, #xx:16, or #xx:32] program-counter relative [@(d:8,pc) or @(d:16,pc)] memory indirect [@@aa:8] ? 16-mbyte address space program: 16 mbytes data: 16 mbytes (4 gbytes architecturally) section 2 cpu rev.2.00 jan. 15, 2007 page 20 of 1174 rej09b0329-0200 ? high-speed operation all frequently-used instructions execute in one or two states maximum clock rate: 10 mhz 8/16/32-bit register-register add/subtract: 100 ns 8 8-bit register-register multiply: 1200 ns 16 8-bit register-register divide: 1200 ns 16 16-bit register-register multiply: 2000 ns 32 16-bit register-register divide: 2000 ns ? two cpu operating modes normal mode*/advanced mode note: * normal mode is not available for this lsi. ? power-down state transition to power-down state by sleep instruction cpu clock speed selection 2.1.2 differences between h8s/2600 cpu and h8s/2000 cpu the differences between the h8s/2600 cpu and the h8s/2000 cpu are shown below. ? register configuration the mac register is supported only by the h8s/2600 cpu. ? basic instructions the four instructions mac, clrmac, ldmac, and stmac are supported only by the h8s/2600 cpu. ? number of execution states the number of execution states of the mulxu and mulxs instructions differ as follows. number of execution states instruction mnemonic h8s/2600 h8s/2000 mulxu.b rs, rd 3 12 mulxu mulxu.w rs, erd 4 20 mulxs mulxs.b rs, rd 4 13 mulxs.w rs, erd 5 21 there are also differences in the address space, exr register functions, power-down state, etc., depending on the product. section 2 cpu rev.2.00 jan. 15, 2007 page 21 of 1174 rej09b0329-0200 2.1.3 differences from h8/300 cpu in comparison to the h8/300 cpu, the h8s/2000 cpu has the following enhancements. ? more general registers and control registers eight 16-bit extended registers, and one 8-bit control register, have been added. ? expanded address space normal mode* supports the same 64-kbyte address space as the h8/300 cpu. advanced mode supports a maximum 16-mbyte address space. ? enhanced addressing mode the addressing modes have been enhanced to make effective use of the 16-mbyte address space. ? enhanced instructions addressing modes of bit-manipulation instructions have been enhanced. signed multiply and divide instructions have been added. two-bit shift instructions have been added. instructions for saving and restoring multiple registers have been added. a test and set instruction has been added. ? higher speed basic instructions execute twice as fast. note: * normal mode is not available for this lsi. 2.1.4 differences from h8/300h cpu in comparison to the h8/300h cpu, the h8s/2000 cpu has the following enhancements. ? additional control register one 8-bit control register has been added. ? enhanced instructions addressing modes of bit-manipulation instructions have been enhanced. two-bit shift instructions have been added. instructions for saving and restoring multiple registers have been added. a test and set instruction has been added. ? higher speed basic instructions execute twice as fast. section 2 cpu rev.2.00 jan. 15, 2007 page 22 of 1174 rej09b0329-0200 2.2 cpu operating modes the h8s/2000 cpu has two operating modes: normal* and advanced. normal mode* supports a maximum 64-kbyte address space. advanced mode supports a maximum 16-mbyte total address space (architecturally the maxi mum total address space is 4 gbytes, with a maximum of 16 mbytes for the program area and a maximum of 4 gbytes for the data area). the mode is selected by the mode pins of the microcontroller. note: * normal mode is not available for this lsi. cpu operating mode normal mode * advanced mode maximum 64 kbytes for program and data areas combined maximum 16 mbytes for program and data areas combined note: * normal mode is not available for this lsi. figure 2.1 cpu operating modes 2.2.1 normal mode (not available for this lsi) the exception vector table and stack have th e same structure as in the h8/300 cpu. (1) address space a maximum address space of 64 kbytes can be accessed. (2) extended registers (en) the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. when en is used as a 16-bit register it can contain any value, even when the corresponding general register (rn) is used as an address register. if the general register is referenced in the register indi rect addressing mode with pre-decrement (@-rn) or post-increment (@rn+) and a carry or borrow occurs, however, th e value in the corresponding extended register (en) will be affected. section 2 cpu rev.2.00 jan. 15, 2007 page 23 of 1174 rej09b0329-0200 (3) instruction set all instructions and addressing modes can be used. only the lower 16 bits of effective addresses (ea) are valid. (4) exception vector table and memory indirect branch addresses in normal mode the top area starting at h'0000 is allocated to the excep tion vector table. one branch address is stored per 16 bits. the config uration of the exception vector table in normal mode is shown in figure 2.2. for details of the exception vector table, see section 5, exception handling. h'0000 h'0001 h'0002 h'0003 h'0004 h'0005 h'0006 h'0007 h'0008 h'0009 h'000a h'000b reset exception vector exception vector 1 exception vector 2 exception vector table (reserved for system use) figure 2.2 exception v ector table (normal mode) the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in normal mode the operand is a 16-bit word operand, providing a 16- bit branch address. branch addresses can be stored in the top area from h'0000 to h'00ff. note that this area is also used fo r the exception vector table. section 2 cpu rev.2.00 jan. 15, 2007 page 24 of 1174 rej09b0329-0200 (5) stack structure when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc and condition-code register (ccr) are pushed onto the stack in exception handling, they are stored as shown in figure 2.3. the extended control register (exr) is not pushed onto the stack. for details, see section 5, exception handling. (a) subroutine branch (b) exception handling pc (16 bits) ccr ccr * pc (16 bits) sp sp note: * ignored when returning. figure 2.3 stack stru cture in normal mode 2.2.2 advanced mode (1) address space linear access is provided to a 16-mbyte maximum address space (a rchitecturally a maximum 16- mbyte program area and a maximum 4-gbyte data area, with a maximum of 4 gbytes for program and data areas combined). (2) extended registers (en) the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. (3) instruction set all instructions and addressing modes can be used. section 2 cpu rev.2.00 jan. 15, 2007 page 25 of 1174 rej09b0329-0200 (4) exception vector table and memory indirect branch addresses in advanced mode the top area starting at h'00000000 is allocated to the exception vector table in units of 32 bits. in each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4). for details of the exception vector table, see section 5, exception handling. h'00000000 h'00000003 h'00000004 h'0000000b h'0000000c exception vector table reserved reset exception vector (reserved for system use) reserved exception vector 1 reserved h'00000010 h'00000008 h'00000007 figure 2.4 excep tion vector tabl e (advanced mode) the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. the upper 8 bits of these 32 bits are a re served area that is regarded as section 2 cpu rev.2.00 jan. 15, 2007 page 26 of 1174 rej09b0329-0200 h'00. branch addresses can be stored in the area from h'00000000 to h'000000ff. note that the first part of this range is also the exception vector table. (5) stack structure in advanced mode, when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc and condition-code register (ccr) are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. the extended control register (exr) is not pushed onto the stack. for details, see section 5, exception handling. (a) subroutine branch (b) exception handling pc (24 bits) ccr pc (24 bits) sp sp reserved figure 2.5 stack stru cture in advanced mode section 2 cpu rev.2.00 jan. 15, 2007 page 27 of 1174 rej09b0329-0200 2.3 address space figure 2.6 shows a memory map of the h8s/2000 cpu. the h8s/2000 cpu provides linear access to a maximum 64-kbyte address space in normal mode*, and a maximum 16-mbyte (architecturally 4-gbyte) a ddress space in advanced mode. note: * normal mode is not available for this lsi. (b) advanced mode h'0000 h'ffff h'00000000 h'ffffffff h'00ffffff (a) normal mode * data area program area cannot be used with this lsi note: * normal mode is not available for this lsi. figure 2.6 memory map section 2 cpu rev.2.00 jan. 15, 2007 page 28 of 1174 rej09b0329-0200 2.4 register configuration 2.4.1 overview the cpu has the internal registers shown in figure 2.7. there are two types of registers: general registers and control registers. t ? ? ? ? i2 i1 i0 exr 76543210 pc 23 0 15 0 7 0 7 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l general registers (rn) and extended registers (en) control registers (cr) legend: sp pc exr t i2 to i 0 ccr i ui er0 er1 er2 er3 er4 er5 er6 er7 (sp) iuihunzvc ccr 76543210 : half-carry flag : user bit : negative flag : zero flag : overflow flag : carry flag h u n z v c : stack pointer : program counter : extended control register : trace bit : interrupt mask bits : condition-code register : interrupt mask bit : user bit or interrupt mask bit note: * does not affect operation in this lsi. * figure 2.7 cpu registers section 2 cpu rev.2.00 jan. 15, 2007 page 29 of 1174 rej09b0329-0200 2.4.2 general registers the cpu has eight 32-bit general registers. these general registers are all functionally alike and can be used as both address registers and data regi sters. when a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8- bit register. when the general registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). the er registers divide into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. the r registers divide into 8- bit general registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum of sixteen 8-bit registers. figure 2.8 illustrates the usage of the general registers. the usage of each register can be selected independently. ? address registers ? 32-bit registers ? 16-bit registers ? 8-bit registers er registers (er0 to er7) e registers (extended registers) (e0 to e7) r registers (r0 to r7) rh registers (r0h to r7h) rl registers (r0l to r7l) figure 2.8 usage of general registers general register er7 has the function of stack poi nter (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2.9 shows the stack. section 2 cpu rev.2.00 jan. 15, 2007 page 30 of 1174 rej09b0329-0200 sp (er7) free area stack area figure 2.9 stack 2.4.3 control registers the control registers are the 24-bit program counter (pc), 8-bit extended control register (exr), and 8-bit condition-code register (ccr). (1) program counter (pc) this 24-bit counter indicates the address of the next instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word), so the least significant pc bit is ignored. (when an instruction is fetched, the least significant pc bit is regarded as 0.) (2) extended control register (exr) an 8-bit register. in this lsi, this register does not affect operation. bit 7: trace bit (t): this bit is reserved. in this lsi, this bit does not affect operation. bits 6 to 3: reserved: these bits are reserved. th ey are always read as 1. bits 2 to 0: interrupt mask bits (i2 to i0): these bits are reserved. in this lsi, these bits do not affect operation. (3) condition: code register (ccr) this 8-bit register contains internal cpu status information, including an interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. section 2 cpu rev.2.00 jan. 15, 2007 page 31 of 1174 rej09b0329-0200 bit 7: interrupt mask bit (i): masks interrupts other than nmi wh en set to 1. (nmi is accepted regardless of the i bit setting.) the i bit is set to 1 by hardware at the start of an exception- handling sequence. for details, see section 6, interrupt controller. bit 6: user bit or interrupt mask bit (ui): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. this bit can also be used as an interrupt mask bit. for details, see section 6, interrupt controller. bit 5: half-carry flag (h): when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if th ere is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. bit 4: user bit (u): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. bit 3: negative flag (n): stores the value of the most significant bit (sign bit) of data. bit 2: zero flag (z): set to 1 to indicate zero data, and cl eared to 0 to indicate non-zero data. bit 1: overflow flag (v): set to 1 when an arithmetic ove rflow occurs, and cleared to 0 otherwise. bit 0: carry flag (c): set to 1 when a carry occurs, and cleared to 0 otherwise. used by: a. add instructions, to indicate a carry b. subtract instructions, to indicate a borrow c. shift and rotate instructions, to store the carry the carry flag is also used as a bit accumulator by bit-manipulation instructions. some instructions leave some or all of the flag bits unchanged. for the action of each instruction on the flag bits, see appendix a.1, instructions. operations can be performed on the ccr bits by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used as branching conditions for conditional branch (bcc) instructions. section 2 cpu rev.2.00 jan. 15, 2007 page 32 of 1174 rej09b0329-0200 2.4.4 initial register values reset exception handling loads the cp u's program counter (pc) from the vector table, clears the trace bit in exr to 0, and sets th e interrupt mask bits in ccr and exr to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (er7) is not initialized. the stack pointer should therefore be initialized by an mov.l instruction executed immediately after a reset. section 2 cpu rev.2.00 jan. 15, 2007 page 33 of 1174 rej09b0329-0200 2.5 data formats the cpu can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipulation instructi ons operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.5.1 general register data formats figure 2.10 shows the data formats in general registers. 70 70 msb lsb msb lsb 70 43 upper digit lower digit don't care don't care don't care 70 43 upper digit lower digit 70 don't care 65432 710 70 don't care 65432 710 don't care data format data type 1-bit data 1-bit data 4-bit bcd data 4-bit bcd data byte data byte data general register rnh rnl rnh rnl rnh rnl figure 2.10 general re gister data formats (1) section 2 cpu rev.2.00 jan. 15, 2007 page 34 of 1174 rej09b0329-0200 15 0 msb lsb 15 0 msb lsb 31 16 msb 15 0 lsb en rn data type word data word data longword data general register rn en ern data format ern en rn rnh rnl msb lsb : general register er : general register e : general register r : general register rh : general register rl : most significant bit : least significant bit legend: figure 2.11 general re gister data formats (2) section 2 cpu rev.2.00 jan. 15, 2007 page 35 of 1174 rej09b0329-0200 2.5.2 memory data formats figure 2.12 shows the data formats in memory. the cpu can access word data and longword data in memory, but word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd address, no address error occurs but the leas t significant bit of the address is regarded as 0, so the access starts at the preceding address. this also applies to instruction fetches. 70 76 543210 msb lsb msb msb lsb lsb address address l address l address 2m address 2n address 2n +1 address 2n +2 address 2n +3 1-bit data byte data word data longword data data type data format address 2m +1 figure 2.12 memory data formats when er7 (sp) is used as an address register to access the stack, the operand size should be word size or longword size. section 2 cpu rev.2.00 jan. 15, 2007 page 36 of 1174 rej09b0329-0200 2.6 instruction set 2.6.1 overview the h8s/2000 cpu has 65 types of instructions. the instructions are classified by function in table 2.1. table 2.1 instructio n classification function instructions size types mov bwl pop * 1 , push * 1 wl ldm * 5 , stm * 5 l data transfer movfpe * 3 , movtpe * 3 b 5 add, sub, cmp, neg bwl addx, subx, daa, das b inc, dec bwl adds, subs l mulxu, divxu, mulxs, divxs bw extu, exts wl arithmetic tas * 4 b 19 logic operations and, or, xor, not bwl 4 shift shal, shar, shll, sh lr, rotl, rotr, rotxl, rotxr bwl 8 bit manipulation bset, bclr, bnot, btst, bld, bild, bst, bist, band, biand, bor, bior, bxor, bixor b 14 branch bcc * 2 , jmp, bsr, jsr, rts ? 5 system control trapa, rte, sleep, ldc, stc, andc, orc, xorc, nop ? 9 block data transfer eepmov ? 1 total: 65 types legend: b: byte w: word l: longword section 2 cpu rev.2.00 jan. 15, 2007 page 37 of 1174 rej09b0329-0200 notes: 1. pop.w rn and push.w rn are identical to mov.w @sp+, rn and mov.w rn, @- sp. pop.l ern and push.l ern are identical to mov.l @sp+, ern and mov.l ern, @- sp. 2. bcc is the general name for conditional branch instructions. 3. cannot be used in the h8s/2199 group. 4. only register er0, er1, er4, or er5 should be used when using the tas instruction. 5. only registers er0 to er6 should be used when using the stm/ldm instruction. section 2 cpu rev.2.00 jan. 15, 2007 page 38 of 1174 rej09b0329-0200 2.6.2 instructions and addressing modes table 2.2 indicates the combinations of instructions and addressing modes that the h8s/2000 cpu can use. table 2.2 combinations of instructions and addressing modes addressing modes function arithmetic operations system control branch logic operation instruction mov pop, push ldm * 3 , stm * 3 add, cmp sub addx, subx adds, subs inc, dec daa, das neg extu, exts tas * 2 movfpe, movtpe * 1 mulxu, divxu mulxs, divxs and, or, xor andc, orc, xorc not bcc, bsr jmp, jsr rts trapa rte sleep ldc stc nop shift bit manipulation block data transfer data transfer bwl #xx ? ? bwl wl b ? ? ? ? ? ? ? ? ? bwl b ? ? ? ? ? ? ? b ? ? ? ? ? bwl rn ? ? bwl bwl b l bwl b bwl wl ? ? bw bw bwl ? bwl ? ? ? ? ? ? b b ? bwl b ? bwl @ern ? ? ? ? ? ? ? ? ? ? b ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? b ? bwl @(d:16, ern) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? ? bwl @(d:32, ern) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? ? bwl @-ern/@ern+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? ? b @aa:8 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? b ? bwl @aa:16 ? ? ? ? ? ? ? ? ? ? ? b ? ? ? ? ? ? ? ? ? ? ? w w ? ? b ? ? @aa:24 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bwl @aa:32 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? b ? ? @(d:8, pc) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? @(d:16, pc) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? @@aa:8 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? wl l ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bw legend: b: byte w: word l: longword notes: 1. cannot be used in this lsi. 2. only register er0, er1, er4, or er5 should be used when using the tas instruction. 3. only registers er0 to er6 should be used when using the stm/ldm instruction. section 2 cpu rev.2.00 jan. 15, 2007 page 39 of 1174 rej09b0329-0200 2.6.3 table of instructions classified by function tables 2.3 to 2.10 summarize the functions of the instructions. the notation used in table 2.3 is defined below. operation notation rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register) (ead) destination operand (eas) source operand exr extended control register ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition ? subtraction multiplication division logical and logical or logical exclusive or move not (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers (er0 to er7). section 2 cpu rev.2.00 jan. 15, 2007 page 40 of 1174 rej09b0329-0200 table 2.3 data transfer instructions instruction size * 1 function mov b/w/l (eas) rd, rs (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register movfpe b cannot be used in this lsi movtpe b cannot be used in this lsi pop w/l @sp+ rn pops a general register from the stack pop.w rn is identical to mov.w @sp+, rn pop.l ern is identical to mov.l @sp+, ern push w/l rn @-sp pushes a general register onto the stack push.w rn is identical to mov.w rn, @-sp push.l ern is identical to mov.l ern, @-sp ldm * 2 l @sp+ rn (register list) pops two or more general registers from the stack stm * 2 l rn (register list) @-sp pushes two or more general registers onto the stack notes: 1. size refers to the operand size. b: byte w: word l: longword 2. only registers er0 to er6 should be used when using the stm/ldm instruction. section 2 cpu rev.2.00 jan. 15, 2007 page 41 of 1174 rej09b0329-0200 table 2.4 arithmetic instructions instruction size * 1 function add sub b/w/l rd rs rd, rd #imm rd performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (immediate byte data cannot be subtracted from byte data in a general register. use the subx or add instruction) addx subx b rd rs c rd, rd #imm c rd performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register inc dec b/w/l rd 1 rd, rd 2 rd increments or decrements a general register by 1 or 2. (byte operands can be incremented or decremented by 1 only) adds subs l rd 1 rd, rd 2 rd, rd 4 rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register daa das b rd decimal adjust rd decimal-adjusts an addition or subtraction result in a general register by referring to the ccr to produce 4-bit bcd data mulxu b/w rd rs rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits mulxs b/w rd rs rd performs signed multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits divxu b/w rd rs rd performs unsigned division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder section 2 cpu rev.2.00 jan. 15, 2007 page 42 of 1174 rej09b0329-0200 instruction size * 1 function divxs b/w rd rs rd performs signed division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder cmp b/w/l rd - rs, rd - #imm compares data in a general register with data in another general register or with immediate data, and sets ccr bits according to the result neg b/w/l 0 - rd rd takes the two's complement (arithmetic complement) of data in a general register exts w/l rd (sign extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit extu w/l rd (zero extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left tas b @erd - 0, 1 ( section 2 cpu rev.2.00 jan. 15, 2007 page 43 of 1174 rej09b0329-0200 table 2.5 logic instructions instruction size * function and b/w/l rd rs rd, rd #imm rd performs a logical and operation on a general register and another general register or immediate data or b/w/l rd rs rd, rd #imm rd performs a logical or operation on a general register and another general register or immediate data xor b/w/l rd rs rd, rd #imm rd performs a logical exclusive or operation on a general register and another general register or immediate data not b/w/l ~ rd rd takes the one's complement (logical complement) of general register contents note: * size refers to the operand size. b: byte w: word l: longword table 2.6 shift instructions instruction size * function shal shar b/w/l rd (shift) rd performs an arithmetic shift on general register contents a 1-bit or 2-bit shift is possible shll shlr b/w/l rd (shift) rd performs a logical shift on general register contents a 1-bit or 2-bit shift is possible rotl rotr b/w/l rd (rotate) rd rotates general register contents 1-bit or 2-bit rotation is possible rotxl rotxr b/w/l rd (rotate) rd rotates general register contents through the carry flag 1-bit or 2-bit rotation is possible note: * size refers to the operand size. b: byte w: word l: longword section 2 cpu rev.2.00 jan. 15, 2007 page 44 of 1174 rej09b0329-0200 table 2.7 bit manipulation instructions instruction size * function bset b 1 ( section 2 cpu rev.2.00 jan. 15, 2007 page 45 of 1174 rej09b0329-0200 instruction size * function boxr b c ( section 2 cpu rev.2.00 jan. 15, 2007 page 46 of 1174 rej09b0329-0200 table 2.8 branch instructions instruction size * function branches to a specified address if a specified condition is true the branching conditions are listed below mnemonic description condition bra (bt) always (true) always brn (bf) never (false) never bhi high cvz = 0 bls low of same cvz = 1 bcc (bhs) carry clear (high or same) c = 0 bcs (blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal nv = 0 blt less than n v = 1 bgt greater than z (n v) = 0 ble less or equal z (n v) = 1 bcc ? jmp ? branches unconditionally to a specified address bsr ? branches to a subroutine at a specified address jsr ? branches to a subroutine at a specified address rts ? returns from a subroutine section 2 cpu rev.2.00 jan. 15, 2007 page 47 of 1174 rej09b0329-0200 table 2.9 system co ntrol instructions instruction size * function trapa ? starts trap-instruction exception handling rte ? returns from an exception-handling routine sleep ? causes a transition to a power-down state ldc b/w (eas) ccr, (eas) exr moves contents of a general register or memory or immediate data to ccr or exr. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid stc b/w ccr (ead), exr (ead) transfers ccr or exr contents to a general register or memory. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid andc b ccr #imm ccr, exr #imm exr logically ands the ccr or exr contents with immediate data orc b ccr #imm ccr, exr #imm exr logically ors the ccr or exr contents with immediate data xorc b ccr #imm ccr, exr #imm exr logically exclusive-ors the ccr or exr contents with immediate data nop ? pc + 2 pc only increments the program counter note: * size refers to the operand size. b: byte w: word section 2 cpu rev.2.00 jan. 15, 2007 page 48 of 1174 rej09b0329-0200 table 2.10 block data transfer instructions instruction size * function eepmov.b ? if r4l 0 then repeat @er5+ @er6+ r4l ? 1 r4l until r4l = 0 else next; eepmov.w ? if r4 0 then repeat @er5+ er6+ r4 ? 1 r4 until r4 = 0 else next; transfers a data block according to parameters set in general registers r4l or r4, er5, and er6 r4l or r4: size of block (bytes) section 2 cpu rev.2.00 jan. 15, 2007 page 49 of 1174 rej09b0329-0200 2.6.4 basic instruction formats the cpu instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op field), a register field (r field), an effective addre ss extension (ea field), and a condition field (cc). figure 2.13 shows examples of instruction formats. op op rn rm nop, rts, etc. add.b rn, rm, etc. mov.b@(d:16, rn), rm, etc. (1) operation field only (2) operation field and register fields (3) operation field, register fields, and effective address extension rn rm op ea (disp) (4) operation field, effective address extension, and condition field op cc ea (disp) bra d:16, etc. figure 2.13 instruction formats (examples) (1) operation field indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. the operation field always includes the first four bits of the instruction. some instructions have two operation fields. (2) register field specifies a general register. address registers are specified by 3 bits, data registers by 3 bits or 4 bits. some instructions have two register fields. some have no register field. (3) effective address extension eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. section 2 cpu rev.2.00 jan. 15, 2007 page 50 of 1174 rej09b0329-0200 (4) condition field specifies the branching condition of bcc instructions. 2.6.5 notes on use of bit-manipulation instructions the bset, bclr, bnot, bst, and bist instructions read a byte of data, carry out bit manipulation, then write back the byte of data. caution is therefore required when using these instructions on a register containing write-only bits, or a port. the bclr instruction can be used to clear internal i/o register flags to 0. in this case, the relevant flag need not be read beforehand if it is clear that it has been set to 1 in an interrupt handling routine, etc. section 2 cpu rev.2.00 jan. 15, 2007 page 51 of 1174 rej09b0329-0200 2.7 addressing modes and eff ective address calculation 2.7.1 addressing mode the cpu supports the eight addressing modes listed in table 2.11. each instruction uses a subset of these addressing modes. arithmetic and logic instructions can use the register direct and immediate modes. data transfer instructions can use all addressing modes except program-counter relative and memory indirect. bit-manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 2.11 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displacement @(d:16,ern)/@(d:32,ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @-ern 5 absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 immediate #xx:8/#xx:16/#xx:32 7 program-counter relative @(d:8,pc)/@(d:16,pc) 8 memory indirect @@aa:8 (1) register direct?rn the register field of the instruction code specifies an 8-, 16-, or 32-bit general register containing the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit register s. er0 to er7 can be specified as 32-bit registers. (2) register indirect?@ern the register field of the instruc tion code specifies an address re gister (ern) which contains the address of the operand in memory. if the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (h'00). section 2 cpu rev.2.00 jan. 15, 2007 page 52 of 1174 rej09b0329-0200 (3) register indirect with displacemen t?@(d:16, ern) or @(d:32, ern) a 16-bit or 32-bit displacement contained in the inst ruction is added to an address register (ern) specified by the register field of the instructio n, and the sum gives the address of a memory operand. a 16-bit displacement is sign-extended when added. (4) register indirect with post-increm ent or pre-decrement?@ern+ or @-ern a. register indirect w ith post-increment?@ern+ the register field of the instruc tion code specifies an address re gister (ern) which contains the address of a memory operand. after the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. the value added is 1 for byte access, 2 for word access, or 4 for longword access. for word or longword access, the register value should be even. b. register indirect with pre-decrement?@-ern the value 1, 2, or 4 is subtracted from an address register (ern) specified by the register field in the instruction code, and the result becomes th e address of a memory operand. the result is also stored in the address register. the value s ubtracted is 1 for byte access, 2 for word access, or 4 for longword access. for word or longwor d access, the register value should be even. (5) absolute address?@aa:8, @aa:16, @aa:24, or @aa:32 the instruction code contains th e absolute address of a memory operand. the absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). to access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. for an 8-bit absolute address, th e upper 24 bits are all a ssumed to be 1 (h'ffff). for a 16-bit absolute address the upper 16 bits are a sign extension. a 32-bit absolute address can access the entire address space. a 24-bit absolute address (@aa:24) indicates the address of a program instruction. the upper 8 bits are all assumed to be 0 (h'00). table 2.12 indicates the accessi ble absolute address ranges. section 2 cpu rev.2.00 jan. 15, 2007 page 53 of 1174 rej09b0329-0200 table 2.12 absolute address access ranges absolute address normal mode advanced mode 8 bits (@aa:8) h'ff00 to h'ffff h'ffff00 to h'ffffff 16 bits (@aa:16) h'000000 to h'007fff, h'ff8000 to h'ffffff data address 32 bits (@aa:32) program instruction address 24 bits (@aa:24) h'0000 to h'ffff h'000000 to h'ffffff (6) immediate?#xx:8, #xx:16, or #xx:32 the instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. the adds, subs, inc, and dec instructions contain immediate data implicitly. some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. the trapa instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) program-counter relative?@(d:8, pc) or @(d:16, pc) this mode is used in the bcc and bsr instructions. an 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit pc contents to generate a branch address. only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (h'00). the pc value to which the displacement is added is the addre ss of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. the resulting value should be an even number. (8) memory indirect?@@aa:8 this mode can be used by the jmp and jsr instructions. the instruction code contains an 8-bit absolute address specifying a memory operand. this memory operand contains a branch address. the upper bits of the absolute address are all a ssumed to be 0, so the address range is 0 to 255 (h'0000 to h'00ff in normal mode, h'000000 to h' 0000ff in advanced mode). in normal mode the memory operand is a word operand and the branch address is 16 bits long. in advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (h'00). section 2 cpu rev.2.00 jan. 15, 2007 page 54 of 1174 rej09b0329-0200 note that the first part of the address range is also the exception vector area. for further details, see section 5, exception handling. (a) normal mode * note: * not available for this lsi (b) advanced mode branch address specified by @aa:8 specified by @aa:8 reserved branch address figure 2.14 branch a ddress specification in memory indirect mode if an odd address is specified in word or longwor d memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or an instruction code to be fetched at the address preceding the specified addre ss. (for further information, see section 2.5.2, memory data formats.) 2.7.2 effective address calculation table 2.13 indicates how effective addre sses are calculated in each addressing mode. in normal mode* the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. note: * not available for this lsi. section 2 cpu rev.2.00 jan. 15, 2007 page 55 of 1174 rej09b0329-0200 table 2.13 effective address calculation no. addressing mode and instruction format effective address calculation effective address (ea) 1 register direct (rn) op rm rn operand is general register contents 2 register indirect (@ern) general register contents 31 0 31 0 r op 24 23 don?t care 3 register indirect with displacement @(d:16, ern) or @(d:32, ern) general register contents sign extension disp 31 0 31 0 31 0 op r disp don?t care 24 23 4 register indirect with post-increment or pre-decrement ? register indirect with post-increment @ern+ general register contents 1, 2, or 4 31 0 31 0 r op don?t care 24 23 ? register indirect with pre-decrement @?ern general register contents 1, 2, or 4 byte word longword 1 2 4 operand size value added 31 0 31 0 op r don?t care 24 23 section 2 cpu rev.2.00 jan. 15, 2007 page 56 of 1174 rej09b0329-0200 no. addressing mode and instruction format effective address calculation effective address (ea) 5 absolute address @aa:8 @aa:16 @aa:32 31 0 8 7 @aa:24 31 0 16 15 31 0 31 0 op abs op abs abs op op abs h'ffff 24 23 don?t care don?t care don?t care don?t care 24 23 24 23 24 23 sign exten- sion 6 immediate #xx:8/#xx:16/#xx:32 op imm operand is immediate data 7 program-counter relative @(d:8, pc)/@(d:16, pc) 0 0 23 23 disp 31 0 24 23 op disp pc contents don?t care sign exten- sion section 2 cpu rev.2.00 jan. 15, 2007 page 57 of 1174 rej09b0329-0200 no. addressing mode and instruction format effective address calculation effective address (ea) 8 memory indirect @@aa:8 ? normal mode * 0 0 31 8 7 0 15 h'000000 31 0 16 15 op abs abs memory contents h'00 24 23 don?t care ? advanced mode 31 0 31 8 7 0 abs h'000000 31 0 24 23 op abs memory contents don?t care note: * not available for this lsi. section 2 cpu rev.2.00 jan. 15, 2007 page 58 of 1174 rej09b0329-0200 2.8 processing states 2.8.1 overview the cpu has four main processing states: the reset state, exception-handling state, program execution state, and power-down state. figure 2. 15 shows a diagram of the processing states. figure 2.16 indicates the state transitions. reset state the cpu and all on-chip supporting modules have been initialized and are stopped. exception-handling state a transient state in which the cpu changes the normal processing flow in response to a reset, interrupt or trap instruction. program execution state the cpu executes program instructions in sequence. power-down state cpu operation is stopped to conserve power. * sleep mode standby mode processing states note: * the power-down state also includes a medium-speed mode, modue stop mode, sub-active mode, sub-sleep mode and watch mode. figure 2.15 processing states section 2 cpu rev.2.00 jan. 15, 2007 page 59 of 1174 rej09b0329-0200 reset state exception-handling state sleep mode standby mode power-down state program execution state interrupt request external interrupt request res = high re quest for exception handlin g sleep instruction wi th lson=0, ssby= 1, tma3 =0 sleep instruction with lson=0, ssby= 0 notes: end of exception handling * 1 * 2 1. 2. from any state, a transition to the reset state occurs whenever res goes low. a transition can also be made to the reset state when the watchdog timer overflows. the power-down state also includes a watch mode, subactive mode, subsleep mode, etc. for details, see section 4, power-down state. figure 2.16 state transitions 2.8.2 reset state when the res input goes low all current processing stops and the cpu enters the reset state. all interrupts are disabled in the reset state. reset exception handling starts when the res signal changes from low to high. the reset state can also be entered by a watc hdog timer overflow. for details, see section 17, watchdog timer (wdt). section 2 cpu rev.2.00 jan. 15, 2007 page 60 of 1174 rej09b0329-0200 2.8.3 exception-handling state the exception-handling state is a transient state that occurs when the cp u alters the normal processing flow due to a reset, interrupt, or trap instruction. the cpu fetches a start address (vector) from the exception vector tabl e and branches to that address. (1) types of exception ha ndling and their priority exception handling is performed for resets, interrupts, and trap instructions. table 2.14 indicates the types of exception handling and their priority. trap instruction exception handling is always accepted in the program execution state. exception handling and the stack structure depend on the interrupt control mode set in syscr. table 2.14 exception handling types and priority priority type of exception detection timing start of exception handling reset synchronized with clock exception handling starts immediately after a low-to-high transition at the res pin, or when the watchdog timer overflows interrupt end of instruction execution or end of exception-handling sequence * 1 when an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence high low trap instruction when trapa instruction is executed exception handling starts when a trap (trapa) instruction is executed * 2 notes: 1. interrupts are not detected at the end of the andc, orc, xorc, and ldc instructions, or immediately after reset exception handling. 2. trap instruction exception handling is alwa ys accepted in the program execution state. (2) reset exception handling after the res pin has gone low and the reset state has been entered, when res goes high again, reset exception handling starts. when reset exception handling starts the cpu fetches a start address (vector) from the exception vector table an d starts program execution from that address. all interrupts, including nmi, are disabled during reset exception handling and after it ends. section 2 cpu rev.2.00 jan. 15, 2007 page 61 of 1174 rej09b0329-0200 (3) interrupt exception handling and trap instruction exception handling when interrupt or trap-instruction exception handling begins, the cpu references the stack pointer (er7) and pushes the program counter and other control registers onto the stack. next, the cpu alters the settings of the interrupt mask bits in the control registers. then the cpu fetches a start address (vector) from the exception vector table and program execution starts from that start address. figure 2.17 shows the stack after exception handling ends. pc (16 bits) sp ccr ccr * 1 pc (24 bits) sp ccr normal mode * 2 advanced mode notes: 1. ignored when returning. 2. normal mode is not available for this lsi. figure 2.17 stack structure after exception handling (examples) 2.8.4 program execution state in this state the cpu executes pr ogram instructions in sequence. section 2 cpu rev.2.00 jan. 15, 2007 page 62 of 1174 rej09b0329-0200 2.8.5 power-down state the power-down state includes both modes in which the cpu stops operating and modes in which the cpu does not stop. there are five modes in which the cpu stops operating: sleep mode, standby mode, subsleep mode, and watch mode. there are also three other power-down modes: medium-speed mode, module stop mode, and subactive mode. in medium-speed mode, the cpu operates on a medium-speed clock. module stop mode permits halting of the operation of individual modules, other than the cpu. subactive mode, subsleep mode, and watch mode are power-down modes that use subclock input. for details, see section 4, power-down state. (1) sleep mode a transition to sleep mode is made if the s leep instruction is execu ted while the software standby bit (ssby) in the standby control register (sbycr) and the lson bit in the low-power control register (lpwrcr) are both cleared to 0. in sleep mode, cpu operations stop immediately after execution of th e sleep instruction. the contents of cpu registers are retained. (2) standby mode a transition to standby mode is made if the sleep instruction is executed while the ssby bit in sbycr is set to 1 and the lson bit in lpwrcr and the tma3 bit in the tma (timer a) are both cleared to 0. in standby mode, the cpu a nd clock halt and all mcu operations stop. as long as a specified voltage is supplied, the contents of cpu registers and on-chip ram are retained. section 2 cpu rev.2.00 jan. 15, 2007 page 63 of 1174 rej09b0329-0200 2.9 basic timing 2.9.1 overview the cpu is driven by a system clock, denoted by the symbol . the period from one rising edge of to the next is referred to as a ?state.? the me mory cycle or bus cycle consists of one or two states. different methods are us ed to access on-chip memory and on-chip supporting modules. 2.9.2 on-chip memory (rom, ram) on-chip memory is accessed in one state. the data bus is 16 bits wide, permitting both byte and word transfer instruction. figure 2.18 shows the on-chip memory access cycle. internal address bus internal read signal internal data bus internal write signal internal data bus bus cycle t1 address read data write data read access write access figure 2.18 on-chip memory access cycle 2.9.3 on-chip supporting module access timing the on-chip supporting modules are accessed in two stat es. the data bus is either 8 bits or 16 bits wide, depending on the particular internal i/o register being accessed. figure 2.19 shows the access timing for the on-chip supporting modules. section 2 cpu rev.2.00 jan. 15, 2007 page 64 of 1174 rej09b0329-0200 internal address bus internal read signal internal data bus internal write signal internal data bus bus cycle t1 address read access write access read data write data t2 figure 2.19 on-chip supporting module access cycle 2.10 usage note 2.10.1 tas instruction only register er0, er1, er4, or er5 should be used when using the tas instruction. the tas instruction is not generated by the renesas technology h8s and h8/300 series c/c++ compilers. if the tas instruction is used as a user-defined intrinsic function, ensure that only register er0, er1, er4, or er5 is used. 2.10.2 stm/ldm instruction er7 is not used as the register that can be saved (stm)/restored (ldm) when using stm/ldm instruction, because er7 is the stack pointer. two, th ree, or four registers can be saved/restored by one stm/ldm instruction. the following ranges can be specified in the register list. two registers : er0 ? er1, er2 ? er3, or er4 ? er5 three registers : er0 ? er2 or er4 ? er6 four registers : er0 ? er3 the stm/ldm instruction including er7 is not generated by the renesas technology h8s and h8/300 series c/c++ compilers. section 3 mcu operating modes rev.2.00 jan. 15, 2007 page 65 of 1174 rej09b0329-0200 section 3 mcu operating modes 3.1 overview 3.1.1 operating mode selection this lsi has one operating mode (mode 1). this mode is selected depending on settings of the mode pin (md0). table 3.1 lists the mcu operating modes. table 3.1 mcu operating mode selection mcu operating mode md0 cpu operating mode description 0 0 ? ? 1 1 advanced single-chip mode the cpu's architecture allows for 4 gbytes of address space, but this lsi actually accesses a maximum of 16 mbytes. mode 1 operation starts in single-chip mode after reset release. this lsi can only be used in mode 1. this means that the mode pins must be set at mode 1. do not changes the inputs at the mode pins during operation. 3.1.2 register configuration this lsi has a mode control register (mdcr) that indicates the inputs at the mode pin (md0) and a system control register (syscr) and that controls the operation of this lsi. table 3.2 summarizes these registers. table 3.2 mcu registers name abbreviation r/w initial value address * mode control register mdcr r undetermined h'ffe9 system control register syscr r/w h'09 h'ffe8 note: * lower 16 bits of the address. section 3 mcu operating modes rev.2.00 jan. 15, 2007 page 66 of 1174 rej09b0329-0200 3.2 register descriptions 3.2.1 mode control register (mdcr) 0 ? * 1 0 2 0 3 0 4 0 5 ? ? ? ? ? 0 6 ? 0 7 ? ? ? ? ? ? ? ? r mds0 0 bit : initial value : r/w : note: * determined by md0 pin mdcr is an 8-bit read-only register monitors the current operating mode of this lsi. bits 7 to 1 ? reserved: these bits cannot be modified and are always read as 0. bit 0 ? mode select 0 (mds0): this bit indicates the value which reflects the input levels at mode pin (md0) (the current operating mode). bit mds0 corresponds to md0 pin. they are read- only bits-they cannot be written to. the mode pin (md0) input levels are latched into these bits when mdcr is read. 3.2.2 system control register (syscr) 0 ? 1 1 0 ? 2 0 ? 3 1 4 0 r/w 5 0 6 ? 0 7 ? ? ? ? r r intm1 intm0 xrst ? ? 0 bit : initial value : r/w : bits 7 and 6 ? reserved: these bits cannot be modified and are always read as 0. section 3 mcu operating modes rev.2.00 jan. 15, 2007 page 67 of 1174 rej09b0329-0200 bits 5 and 4 ? interrupt control modes 1 and 0 (intm1, intm0) these bits are for selecting the interrupt control mode of the interrupt controller. for details of the interrupt control modes, see section 6.4.1, interrupt control modes and interrupt operation. bit 5 bit 4 intm1 intm0 interrupt control mode description 0 0 interrupt is controlled by bit i (initial value) 0 1 1 interrupt is controlled by bits i and ui, and icr 1 0 ? cannot be used in this lsi 1 ? cannot be used in this lsi bit 3 ? external reset (xrst): indicates the reset source. when the watchdog timer is used, a reset can be generated by watchdog timer overflow as well as by external reset input. xrst is a read-only bit. it is set to 1 by an external reset and cleared to 0 by watchdog timer overflow. bit 3 xrst description 0 a reset is generated by watchdog timer overflow 1 a reset is generated by an external reset (initial value) bits 2 and 1 ? reserved: these bits cannot be modified and are always read as 0. bit 0 ? reserved: this bit is always read as 1. 3.3 operating mode (mode 1) the cpu can access a 16 mbyte address space in advanced mode. section 3 mcu operating modes rev.2.00 jan. 15, 2007 page 68 of 1174 rej09b0329-0200 3.4 address map in each operating mode h8s/2196r h8s/2197r memory indirect branch address absolute address, 16 bits 4 kbytes vector area on-chip rom (80 kbytes) internal i/o register internal i/o register on-chip ram vector area on-chip rom (96 kbytes) internal i/o register internal i/o register osd rom (24 kbytes) on-chip ram (4 kbytes) h'000000 h'000000 h'017fff h'ffd000 h'040000 h'045fff h'ffd2ff h'ffd800 h'ffdaff h'ffefb0 h'ffffaf h'ffffb0 h'ffffff h'0000ff h'007fff h'013fff h'ff8000 h'ffd000 h'ffd2ff h'ffefb0 h'ffff00 h'ffffaf h'ffffb0 h'ffffff osd ram (768 bytes) osd rom (24 kbytes) h'040000 h'045fff h'ffd800 h'ffdaff osd ram (768 bytes) absolute address, 8 bits absolute address, 16 bits figure 3.1 address map (1) section 3 mcu operating modes rev.2.00 jan. 15, 2007 page 69 of 1174 rej09b0329-0200 h8s/2198r h8s/2199r vector area on-chip rom (112 kbytes) internal i/o register internal i/o register on-chip ram (4 kbytes) vector area on-chip rom (128 kbytes) internal i/o register internal i/o register on-chip ram (4 kbytes) h'000000 h'000000 h'01ffff h'ffd000 h'ffd2ff h'ffefb0 h'ffffaf h'ffffb0 h'ffffff h'01bfff h'ffd000 h'ffd2ff h'ffefb0 h'ffffaf h'ffffb0 h'ffffff osd rom (24 kbytes) h'040000 h'045fff h'ffd800 h'ffdaff osd ram (768 bytes) osd rom (24 kbytes) h'040000 h'045fff h'ffd800 h'ffdaff osd ram (768 bytes) h8s/2199r (f-ztat version) vector area flash memory (256 kbytes) internal i/o register internal i/o register on-chip ram (8 kbytes) h'000000 h'ffd000 h'ffd2ff h'ffdfb0 h'ffffaf h'ffffb0 h'ffffff flash memory (osd) (32 kbytes) h'03ffff h'047fff h'ffd800 h'ffdaff osd ram (768 bytes) figure 3.2 address map (2) section 3 mcu operating modes rev.2.00 jan. 15, 2007 page 70 of 1174 rej09b0329-0200 h8s/2196s h8s/2197s vector area vector area on-chip rom (80 kbytes) on-chip rom (96 kbytes) internal i/o register internal i/o register internal i/o register internal i/o register on-chip ram (3 kbytes) on-chip ram (3 kbytes) h'000000 h'000000 h'017fff h'ffd800 h'fff3b0 h'ffffaf h'ffffb0 h'ffffff h'013fff h'ffd800 h'fff3b0 h'ffffaf h'ffffb0 h'ffffff osd rom (16 kbytes) h'040000 h'043fff h'040000 h'043fff osd rom (16 kbytes) osd ram (768 bytes) osd ram (768 bytes) h'ffdaff h'ffdaff h'ffd000 h'ffd2ff h'ffd000 h'ffd2ff figure 3.3 address map (3) section 4 power-down state rev.2.00 jan. 15, 2007 page 71 of 1174 rej09b0329-0200 section 4 power-down state 4.1 overview in addition to the normal program execution state, this lsi has a power-down state in which operation of the cpu and oscillator is halted and power dissipation is reduced. low-power operation can be achieved by individually controlling the cpu, on-chip supporting modules, and so on. this lsi operating modes are as follows: 1. high-speed mode 2. medium-speed mode 3. sub-active mode 4. sleep mode 5. sub-sleep mode 6. watch mode 7. module stop mode 8. standby mode of these, 2 to 8 are power-down modes. certain co mbinations of these modes can be set. after a reset, the mcu is in high-speed mode. table 4.1 shows the internal chip states in each mode, and table 4.2 shows the conditions for transition to the various modes. figure 4.1 shows a mode transition diagram. section 4 power-down state rev.2.00 jan. 15, 2007 page 72 of 1174 rej09b0329-0200 table 4.1 h8s/2199r group internal states in each mode function high-speed medium- speed sleep module stop watch sub-active sub-sleep standby system clock functioning functioning functioning functioning halted halted halted halted subclock pulse generator functioning functioning functioning functioning functioning functioning functioning functioning instruction s halted halted halted halted cpu operation registers functioning medium- speed retained functioning retained subclock operation retained retained irq0 irq1 functioning functioning functioning functioning irq2 irq3 irq4 external interrupts irq5 functioning functioning functioning functioning halted halted functioning halted i/o functioning functioning retained functioning halted functioning retained halted timer a functioning functioning functioning functioning /halted (retained) subclock operation subclock operation subclock operation halted (retained) timer b timer j timer l functioning /halted (retained) halted (retained) halted (retained) halted (retained) halted (retained) timer r on-chip supporting module operation timer x1 * 2 functioning functioning functioning functioning /halted (reset) halted (reset) halted (reset) halted (reset) halted (reset) watchdog timer functioning functioning functioning functioning halted (retained) halted (retained) halted (retained) halted (retained) 8-bit pwm functioning functioning functioning functioning /halted (retained) halted (retained) halted (retained) halted (retained) halted (retained) 12-bit pwm functioning functioning halted (reset) functioning /halted (reset) halted (reset) halted (reset) halted (reset) halted (reset) 14-bit pwm * 2 functioning functioning functioning functioning /halted (retained) halted (retained) halted (retained) halted (retained) halted (retained) psu functioning functioning functioning functioning/ halted subclock operation subclock operation subclock operation halted sci1 functioning/ halted * 1 halted * 1 halted * 1 halted * 1 halted * 1 iic functioning/ halted (retained) halted (retained) halted (retained) halted (retained) halted (retained) a/d functioning functioning functioning functioning /halted (reset) halted (reset) halted (reset) halted (reset) halted (reset) servo circuit functioning functioning halted (reset) functioning /halted (reset) halted (reset) halted (reset) halted (reset) halted (reset) sync separator functioning functioning halted (retained) functioning /halted (retained) halted (retained) halted (retained) halted (retained) halted (retained) section 4 power-down state rev.2.00 jan. 15, 2007 page 73 of 1174 rej09b0329-0200 function high-speed medium- speed sleep module stop watch sub-active sub-sleep standby data slicer halted (reset) on-chip supporting module operation osd functioning functioning halted (reset) functioning /halted (reset) halted (reset) halted (reset) halted (reset) notes: "halted (retained)" means that internal register values are retained. the internal state is "operation suspended." "halted (reset)" means that internal register values and internal states are initialized. in module stop mode, only modules for which a stop setting has been made are halted (reset or retained). in the power-down mode, the analog section of the servo circuits are not turned off, therefore vcc (servo) current does not go low. when power-down is needed, externally shut down the analog system power. 1. the sci1 status differs from the internal register. for details, refer to section 22, serial communication interface 1 (scii). 2. not available in the h8s/2197s or h8s/2196s. section 4 power-down state rev.2.00 jan. 15, 2007 page 74 of 1174 rej09b0329-0200 program-halted state conditions for mode transition (1) conditions for mode transition (2) interruption factor sleep (high-speed) mode sleep (medium-speed) mode subsleep mode program execution state reset state flag sleep instruction interrupt lson ssby tma3 dton a 010 * b * 110 c 0111 d 1111 e 00 ** f 101 * g sck1 to 0 = 0 h sck1 to 0 0 (either 1 bit = 0) power-down mode active (high-speed) mode active (medium-speed) mode subactive mode program-halted state watch mode standby mode irq0 to 1 irq0 to 1, timer a interruption all interruption (excluding servo system) irq0 to 5, timer a interruption 1 2 3 4 interrupt interrupt sleep instruction sleep instruction e note: when a transition is made between modes by means of an interrupt, transition cannot be made on interrupt source generation alone. ensure that interrupt handling is performed after accepting the interrupt request sleep instruction a 1 interrupt 1 2 sleep instruction sleep instruction sleep instruction sleep instruction a b g h d sleep instruction c e 3 interrupt 2 interrupt 3 interrupt 2 interrupt 4 c sleep instruction d b b sleep instruction sleep instruction 1 legend: * don't care figure 4.1 mode transitions section 4 power-down state rev.2.00 jan. 15, 2007 page 75 of 1174 rej09b0329-0200 table 4.2 power-down mode transition conditions control bit states at time of transition state before transition ssby tma3 lson dton state after transition by sleep instruction state after return by interrupt 0 * 0 * sleep high-speed/ medium-speed * 1 0 * 1 * ? ? 1 0 0 * standby high-speed/ medium-speed * 1 1 0 1 * ? ? 1 1 0 0 watch high-speed/ medium-speed * 1 1 1 1 0 watch subactive 1 1 0 1 ? ? high-speed/ medium-speed 1 1 1 1 subactive ? subactive 0 0 * * ? ? 0 1 0 * ? ? 0 1 1 * subsleep subactive 1 0 * * ? ? 1 1 0 0 watch high-speed/ medium-speed * 2 1 1 1 0 watch subactive 1 1 0 1 high-speed/ medium-speed * 2 ? 1 1 1 1 ? ? legend: * don't care notes: ? : do not set. 1. returns to the state before transition. 2. mode varies depending on the state of sck1 to sck0. section 4 power-down state rev.2.00 jan. 15, 2007 page 76 of 1174 rej09b0329-0200 4.1.1 register configuration the power-down state is controlled by the sbycr, lpwrcr, tma (timer a), and mstpcr registers. table 4.3 summarizes these registers. table 4.3 power-down state registers name abbreviation r/w initial value address * standby control register sbycr r/w h'00 h'ffea low-power control register lpwrcr r/w h'00 h'ffeb mstpcrh r/w h'ff h'ffec module stop control register mstpcrl r/w h'ff h'ffed timer mode register a tma r/w h'30 h'ffba note: * lower 16 bits of the address. 4.2 register descriptions 4.2.1 standby control register (sbycr) 0 0 1 0 r/w 2 0 3 ? ? ? ? 0 4 0 r/w 5 0 6 0 7 r/w r/w sts1 r/w sts2 0 r/w ssby sts0 sck1 sck0 bit : initial value : r/w : sbycr is an 8-bit readable/writable register that performs power-down mode control. sbycr is initialized to h'00 by a reset. section 4 power-down state rev.2.00 jan. 15, 2007 page 77 of 1174 rej09b0329-0200 bit 7 ? software standby (ssby): determines the operating mode, in combination with other control bits, when a power-down mode transition is made by executing a sleep instruction. the ssby setting is not changed by a mode transition due to an interrupt, etc. bit 7 ssby description 0 transition to sleep mode after execution of sleep instruction in high-speed mode or medium-speed mode transition to subsleep mode after execution of sleep instruction in subactive mode (initial value) 1 transition to standby mode, subactive mode, or watch mode after execution of sleep instruction in high-speed mode or medium-speed mode transition to watch mode or high-speed mode after execution of sleep instruction in subactive mode bits 6 to 4 ? standby timer select 2 to 0 (sts2 to sts0) : these bits select the time the mcu waits for the clock to stabilize when standby mode, watch mode, or subactive mode is cleared and a transition is made to high-speed mode or medium-speed mode by means of a specific interrupt or instruction. with crystal oscillation, see table 4.5 and make a selection according to the operating frequency so that the standby time is at least 10 ms (the oscillation settling time). bit 6 bit 5 bit 4 sts2 sts1 sts0 description 0 0 0 standby time = 8192 states 0 0 1 standby time = 16384 states 0 1 0 standby time = 32768 states 0 1 1 standby time = 65536 states 1 0 0 standby time = 131072 states 1 0 1 standby time = 262144 states 1 1 * reserved legend: * don't care bits 3 and 2 ? reserved: these bits cannot be modified and are always read as 0. section 4 power-down state rev.2.00 jan. 15, 2007 page 78 of 1174 rej09b0329-0200 bits 1 and 0 ? system clock select 1 and 0 (sck1, sck0) : these bits select the cpu clock for the bus master in high-speed mode and medium-speed mode. bit 1 bit 0 sck1 sck0 description 0 0 bus master is in high-speed mode (initial value) 0 1 medium-speed clock is /16 1 0 medium-speed clock is /32 1 1 medium-speed clock is /64 4.2.2 low-power control register (lpwrcr) 0 0 1 0 r/w r/w 2 0 3 0 4 ? ? ? ? ? ? 0 5 0 6 0 7 r/w nesel r/w lson 0 r/w dton sa1 sa0 bit : initial value : r/w : lpwrcr is an 8-bit readable/writable register that performs power-down mode control. lpwrcr is initialized to h'00 by a reset. bit 7 ? direct-transfer on flag (dton): specifies whether a direct transition is made between high-speed mode, medium-speed mode, and subactive mode when making a power-down transition by executing a sleep instruction. the operating mode to which the transition is made after sleep instruction execution is determin ed by a combination of other control bits. bit 7 dton description 0 ? when a sleep instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, standby mode, or watch mode ? when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode (initial value) 1 ? when a sleep instruction is executed in high-speed mode or medium-speed mode, transition is made directly to subactive mode, or a transition is made to sleep mode or standby mode ? when a sleep instruction is executed in subactive mode, a transition is made directly to high-speed mode, or a transition is made to subsleep mode section 4 power-down state rev.2.00 jan. 15, 2007 page 79 of 1174 rej09b0329-0200 bit 6 ? low-speed on flag (lson): determines the operating mode in combination with other control bits when making a power-down tran sition by executing a sleep instruction. also controls whether a transition is made to high-speed mode or to subactive mode when watch mode is cleared. bit 6 lson description 0 ? when a sleep instruction is executed in high-speed mode or medium-speed mode, transition is made to sleep mode, standby mode, or watch mode ? when a sleep instruction is executed in subactive mode, a transition is made to watch mode, or directly to high-speed mode ? after watch mode is cleared, a transition is made to high-speed mode (initial value) 1 ? when a sleep instruction is executed in high-speed mode a transition is made to watch mode, subactive mode, sleep mode or standby mode ? when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode ? after watch mode is cleared, a transition is made to subactive mode bit 5 ? noise elimination sampling frequency select (nesel): selects the frequency at which the subclock ( w) generated by the subclock pulse generator is sampled with the clock ( ) generated by the system clock oscillator. when = 5 mhz or higher, clear this bit to 0. bit 5 nesel description 0 sampling at divided by 16 1 sampling at divided by 4 bits 4 to 2 ? reserved: these bits cannot be modified and are always read as 0. section 4 power-down state rev.2.00 jan. 15, 2007 page 80 of 1174 rej09b0329-0200 bits 1 and 0 ? subactive mode clock select 1 and 0 (sa1, sa0): these bits select the cpu operating clock in the subactive mode. these bits cannot be modified in the subactive mode. bit 1 bit 0 sa1 sa0 description 0 0 operating clock of cpu is w/8 (initial value) 0 1 operating clock of cpu is w/4 1 * operating clock of cpu is w/2 legend: * don?t care 4.2.3 timer register a (tma) 0 0 1 0 r/w 2 0 3 0 4 1 5 ? ? 1 6 0 7 r/w r/w r/w r/w tma3 r/w tma2 r/w tmaie 0 r/(w) * tmaov tma1 tma0 bit : initial value : r/w : note: * only 0 can be written, to clear the flag. the timer register a (tma) controls timer a interrupts and selects input clock. only bit 3 is explained here. for details of other bits, see section 11.2.1, timer mode register a (tma). tma is a readable/writable register which is initialized to h'30 by a reset. section 4 power-down state rev.2.00 jan. 15, 2007 page 81 of 1174 rej09b0329-0200 bit 3 ? clock source, prescaler select (tma3): selects timer a clock source between pss and psw. it also controls transition operation to the power-down mode. the operation mode to which the mcu is transited after sleep instruction ex ecution is determined by the combination with other control bits. for details, see the description of clock select 2 to 0 in section 11.2.1, timer mode register a (tma). bit 3 tma3 description 0 ? timer a counts -based prescaler (pss) divided clock pulses ? when a sleep instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode or software standby mode (initial value) 1 ? timer a counts w-based prescaler (psw) divided clock pulses ? when a sleep instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, watch mode, or subactive mode ? when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode, watch mode, or high-speed mode 4.2.4 module stop control register (mstpcr) 7 1 mstp15 r/w mstpcrh 6 1 mstp14 r/w 5 1 mstp13 r/w 4 1 mstp12 r/w 3 1 mstp11 r/w 2 1 mstp10 r/w 1 1 mstp9 r/w 0 1 mstp8 r/w 7 1 mstp7 r/w 6 1 mstp6 r/w 5 1 mstp5 r/w 4 1 mstp4 r/w 3 1 mstp3 r/w 2 1 mstp2 r/w 1 1 mstp1 r/w 0 1 mstp0 r/w mstpcrl bit : initial value : r/w : mstpcr comprises two 8-bit readable/writable registers that perform module stop mode control. mstpcr is initialized to h'ffff by a reset. mstpcrh and mstpcrl bits 7 to 0 ? module stop (mstp 15 to mstp 0): these bits specify module stop mode. see table 4.4 for the method of selecting on-chip supporting modules. mstpcrh, mstpcrl bits 7 to 0 mstp 15 to mstp 0 description 0 module stop mode is cleared 1 module stop mode is set (initial value) section 4 power-down state rev.2.00 jan. 15, 2007 page 82 of 1174 rej09b0329-0200 4.3 medium-speed mode when the sck1 and sck0 bits in sbycr are set to 1 in high-speed mode, the operating mode changes to medium-speed mode at the end of the bus cycle. in medium-speed mode, the cpu operates on the operating clock ( 16, 32 or 64) specified by the sck1 and sck0 bits. the on- chip supporting modules other than the cpu always operate on the high-speed clock ( ). in medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. for example, if / 16 is selected as the operating clock, on-chip memory is accessed in 16 states, and internal i/o registers in 32 states. medium-speed mode is cleared by clearing the both bits sck1 and sck0 to 0. a transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. if a sleep instruction is exec uted when the ssby bit in sbycr and the lson bit in lpwrcr are cleared to 0, a transition is made to sleep mode. when sleep mode is cleared by an interrupt, medium-speed mode is restored. if a sleep instruction is executed when the ssby bit in sbycr is set to 1, and the lson bit in lpwrcr and the tma3 bit in tma (timer a) are both cleared to 0, a transition is made to software standby mode. when standby mode is cleared by an external interrupt, medium-speed mode is restored. when the res pin is driven low, a transition is made to the reset state, and medium-speed mode is cleared. the same applies in the case of a re set caused by overflow of the watchdog timer. figure 4.2 shows the timing for transition to and clearance of medium-speed mode. medium-speed mode internal , supporting module clock cpu clock internal address bus internal write signal sbycr sbycr figure 4.2 medium-speed mode transition and clearance timing section 4 power-down state rev.2.00 jan. 15, 2007 page 83 of 1174 rej09b0329-0200 4.4 sleep mode 4.4.1 sleep mode if a sleep instruction is execut ed when the ssby b it in sbycr and the lson bit in lpwrcr are both cleared to 0, the cpu will enter sleep mode. in sleep mode, cpu operation stops but the contents of the cpu's internal registers are retained. other supporting modules (excluding some functions) do not stop. 4.4.2 clearing sleep mode sleep mode is cleared by any interrupt, or with the res pin. clearing with an interrupt: when an interrupt request signal is input, sleep mode is cleared and interrupt exception handling is started. sleep mode will not be cleared if interrupts are disabled, or if interrupts other than nmi have been masked by the cpu. clearing with the res pin: when the res pin is driven low, the reset state is entered. when the res pin is driven high after the prescribed reset input period, the cpu begins reset exception handling. section 4 power-down state rev.2.00 jan. 15, 2007 page 84 of 1174 rej09b0329-0200 4.5 module stop mode 4.5.1 module stop mode module stop mode can be set for individual on-chip supporting modules. when the corresponding mstp bit in mstpcr is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. th e cpu continues operating independently. table 4.4 shows mstp bits and the on-chip supporting modules. when the corresponding mstp bit is cleared to 0, module stop mode is cleared and the module starts operating again at the end of the bus cycle. in module stop mode, the internal states of modules excluding some modules are retained. after reset release, all modules are in module stop mode. when an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. table 4.4 mstp bits and corresponding on-chip supporting modules register bit module mstp15 timer a mstp14 timer b mstp13 timer j mstp12 timer l mstp11 timer r mstp10 timer x1 * mstp9 sync separator mstpcrh mstp8 serial communication interface 1 (sci1) mstpcrl mstp7 i 2 c bus interface (iic0) * mstp6 i 2 c bus interface (iic1) mstp5 14-bit pwm * mstp4 8-bit pwm mstp3 data slicer mstp2 a/d converter mstp1 servo circuit, 12-bit pwm mstp0 osd note: * this bit has no function in the h8s/2197s or h8s/2196s. section 4 power-down state rev.2.00 jan. 15, 2007 page 85 of 1174 rej09b0329-0200 4.6 standby mode 4.6.1 standby mode if a sleep instruction is execut ed when the ssby bit in sbycr is set to 1, the lson bit in lpwrcr is cleared to 0, and the tma3 bit in tma (timer a) is cleared to 0, standby mode will be entered. in this mode, the cpu, on-chip supporting modules, and oscillator (except for subclock oscillator) all stop. however, the contents of the cpu's internal registers and data in the on-chip ram, as well as on-chip peripheral circuits (with some exceptions), are maintained in the current state. (timer x1 and sci1 are partially reset.) the i/o port, at this time, is caused to the high impedance state. in this mode the oscillator stops, and therefore power dissipation is significantly reduced. 4.6.2 c l earing standby mode standby mode is cleared by an external interrupt (pin irq0 to irq1 ), or by means of the res pin. clearing with an interrupt: when an irq0 to irq1 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits sts2 to sts0 in sbycr, stable clocks are supplied to the entire chip, standby mo de is cleared, and interrupt exception handling is started. standby mode cannot be cleared with an irq0 to irq1 interrupt if the corresponding enable bit has been cleared to 0 or has been masked by the cpu. clearing with the res pin: when the res pin is driven low, clock oscillation is started. at the same time as clock oscillation starts, clocks ar e supplied to the entire chip. note that the res pin must be held low until clock oscillation stabilizes. when the res pin goes high, the cpu begins reset exception handling. 4.6.3 setting oscillation settling time after clearing standby mode bits sts2 to sts0 in sbycr should be set as described below. using a crystal oscillator: set bits sts2 to sts0 so that the standby time is at least 10 ms (the oscillation settling time). table 4.5 shows the standby times for different oper ating frequencies and settings of bits sts2 to sts0. section 4 power-down state rev.2.00 jan. 15, 2007 page 86 of 1174 rej09b0329-0200 table 4.5 oscillation settling time settings sts2 sts1 sts0 standby time 10 mhz 8 mhz unit 0 8192 states 0.8 1.0 0 1 16384 states 1.6 2.0 0 32768 states 3.3 4.1 0 1 1 65536 states 6.6 8.2 1 0 131072 states 13.1 * 1 16.4 * 1 0 1 262144 states 26.2 32.8 ms 1 * reserved ? ? legend: * don't care note: 1. recommended time setting using an external clock: any value can be set. section 4 power-down state rev.2.00 jan. 15, 2007 page 87 of 1174 rej09b0329-0200 4.7 watch mode 4.7.1 watch mode if a sleep instruction is executed in high-speed mode, medium-speed mode or subactive mode when the ssby in sbycr is set to 1, the dton bit in lpwrcr is cleared to 0, and the tma3 bit in tma (timer a) is set to 1, the cpu will make a transition to watch mode. in this mode, the cpu and all on-chip supporting modules except timer a stop. as long as the prescribed voltage is supplied, the contents of cpu registers, some on-chip supporting module registers, and on-chip ram, are retained, and i/ o ports are placed in th e high-impedance state. 4.7.2 clearing watch mode watch mode is cleared by an interrupt (timer a interrupt, or pin irq0 to irq1 ), or by means of the res pin. clearing with an interrupt: when an interrupt request signal is input, watch mode is cleared and a transition is made to high-speed mode or medium-speed mode if the lson bit in lpwrcr is cleared to 0, or to subactive mode if the lson bit is set to 1. when making a transition to medium-speed mode, after the elapse of the time set in bits sts2 to sts0 in sbycr, stable clocks are supplied to the entire chip, and interrupt exception handling is started. watch mode cannot be cleared with an irq0 to irq1 interrupt if the corresponding enable bit has been cleared to 0, or with an on-chip suppor ting module interrupt if acceptance of the relevant interrupt has been disabled by the interrupt enable register or masked by the cpu. see section 4.6.3, setting oscillation settling time after clearing standby mode, for the oscillation settling time setting when making a transition from watch mode to high-speed mode or medium-speed mode. clearing with the res pin: see clearing with the res pin in section 4.6.2, clearing standby mode. section 4 power-down state rev.2.00 jan. 15, 2007 page 88 of 1174 rej09b0329-0200 4.8 subsleep mode 4.8.1 subsleep mode if a sleep instruction is executed in subactive mode when the ssb y in sbycr is cleared to 0, the lson bit in lpwrcr is set to 1, and the tma3 bit in tma (timer a) is set to 1, the cpu will make a transition to subsleep mode. in this mode, the cpu and all on-chip supporting modules other than timer a stop. as long as the prescribed voltage is supplied, the contents of cpu registers, some on-chip supporting module registers, and on-chip ram, are retained, and i/ o ports are placed in th e high-impedance state. 4.8.2 clearing subsleep mode subsleep mode is cleared by an interrupt (timer a interrupt, or pin irq0 to irq5 ), or by means of the res pin. clearing with an interrupt: when an interrupt request signal is input, subsleep mode is cleared and interrupt exception handling is started. subsleep mode cannot be cleared with an irq0 to irq5 interrupt if the corresponding enable bit has been cleared to 0, or with an on-chip supporting module interrupt if acceptance of the relevant interr upt has been disabled by the interrupt enable register or masked by the cpu. clearing with the res pin: see (2) clearing with the res pin in section 4.6.2, clearing standby mode. section 4 power-down state rev.2.00 jan. 15, 2007 page 89 of 1174 rej09b0329-0200 4.9 subactive mode 4.9.1 subactive mode if a sleep instruction is executed in high-sp eed mode when the ssby bit in sbycr, the dton bit in lpwrcr, and the tma3 bit in tma (timer a) are all set to 1, the cpu will make a transition to subactive mode. when an interrupt is generated in watch mode, if the lson bit in lpwrcr is set to 1, a transition is made to subactive mode. when an interrupt is generated in subsleep mode, a transition is made to subactive mode. in subactive mode, the cpu performs sequential program execution at low speed on the subclock. in this mode, all on-chip supporting modules other than timer a stop. 4.9.2 clearing subactive mode subsleep mode is cleared by a sleep instruction, or by means of the res pin. clearing with a sleep instruction: when a sleep instruction is executed while the ssby bit in sbycr is set to 1, the dton bit in lpwrcr is cleared to 0, and the tma3 bit in tma (timer a) is set to 1, subactive mode is cleared and a transition is made to watch mode. when a sleep instruction is executed while the ssby bit in sbycr is cleared to 0, the lson bit in lpwrcr is set to 1, and the tma3 bit in tma (timer a) is set to 1, a transition is made to subsleep mode. when a sleep instruction is execu ted while the ssby bit in sbycr is set to 1, the dton bit is set to 1 and the lson bit is cleared to 0 in lpwrcr, and the tma3 bit in tma (timer a) is set to 1, a transition is made directly to high-speed or medium-speed mode. for details of direct transition, see section 4.10, direct transition. clearing with the res pin: see clearing with the res pin in section 4.6.2, clearing standby mode. section 4 power-down state rev.2.00 jan. 15, 2007 page 90 of 1174 rej09b0329-0200 4.10 direct transition 4.10.1 overview of direct transition there are three operating modes in which the cpu executes programs: high-speed mode, medium- speed mode, and subactive mode. a transition between high-speed mode and subactive mode without halting the program* is ca lled a direct transition. a direct transition can be carried out by setting the dton bit in lpwrcr to 1 and executing a sleep instruction. after the transition, direct transition interrupt exception handling is started. direct transition from high-speed mode to subactive mode: if a sleep instruction is executed in high-speed mode while the ssby bit in sbycr, the lson bit and dton bit in lpwrcr, and the tma3 bit in tma (timer a) are all set to 1, a transition is made to subactive mode. direct transition from subactive mode to high-speed mode/medium-speed mode: if a sleep instruction is executed in subactive mode while the ssby b it in sbycr is set to 1, the lson bit is cleared to 0 and the dton bit is set to 1 in lpwrcr, and the tma3 bit in tma (timer a) is set to 1, after the elapse of the time set in bits sts2 to sts0 in sbycr, a transition is made to directly to high-speed mode or medium-speed mode. note: * at the time of transition from subactive mode to high- or medium-speed mode, an oscillation stabilization wait time is generated. section 5 exception handling rev.2.00 jan. 15, 2007 page 91 of 1174 rej09b0329-0200 section 5 exception handling 5.1 overview 5.1.1 exception handling types and priority as table 5.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. exception handling is prioritized as shown in table 5.1. if two or more exceptions occur simultaneously, they are accepted and processed in or der of priority. trap instruction exceptions are accepted at all times in th e program execution state. exception handling sources, the stack structure, and the operation of the cpu vary depending on the interrupt control mode set by the intm0 and intm1 bits in syscr. table 5.1 exception types and priority priority exception type start of exception handling reset starts immediately after a low-to-high transition at the res pin, or when the watchdog timer overflows trace * 1 starts when execution of the current instruction or exception handling ends, if the trace (t) bit is set to 1 interrupt starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued * 2 direct transition started by a direct transition resulting from execution of a sleep instruction high low trap instruction (trapa) * 3 started by execution of a trap instruction (trapa) notes: 1. traces are enabled only in interrupt control modes 2 and 3. (they cannot be used in this lsi.) trace exception handling is not executed after execution of an rte instruction. 2. interrupt detection is not performed on completion of andc, orc, xorc, or ldc instruction execution, or on completion of reset exception handling. 3. trap instruction exception handling requests are accepted at all times in the program execution state. section 5 exception handling rev.2.00 jan. 15, 2007 page 92 of 1174 rej09b0329-0200 5.1.2 exception handling operation exceptions originate from various sources. trap instructions and interrupts are handled as follows: 1. the program counter (pc) and condition-code register (ccr) are pushed onto the stack. 2. the interrupt mask bits are upd ated. the t bit is cleared to 0. 3. a vector address corresponding to the exception source is generated, and program execution starts from that address. for a reset exception, steps 2 and 3 above are carried out. 5.1.3 exception sources and vector table the exception sources are classified as shown in figure 5.1. different vector addresses are assigned to different exception sources. table 5.2 lists the exception sources and their vector addresses. exception sources ? reset ? interrupts ? trap instruction note: * in this lsi, the watchdo g timer g enerates nmis. ? trace (cannot be used in this lsi) ? direct transition external interrupts nmi * , irq5 to irq0 internal interrupts interrupt sources in on-chip supportin g modules ? ? figure 5.1 exception sources section 5 exception handling rev.2.00 jan. 15, 2007 page 93 of 1174 rej09b0329-0200 table 5.2 exception vector table exception source vector number vector address * 1 reset 0 h'0000 to h'0003 1 h'0004 to h'0007 2 h'0008 to h'000b 3 h'000c to h'000f 4 h'0010 to h'0013 reserved for system use 5 h'0014 to h'0017 direct transition 6 h'0018 to h001b external interrupt nmi * 2 7 h'001c to h'001f 8 h'0020 to h'0023 9 h'0024 to h'0027 10 h'0028 to h'002b trap instruction (4 sources) 11 h'002c to h'002f 12 h'0030 to h'0033 13 h'0034 to h'0037 14 h'0038 to h'003b reserved for system use 15 h'003c to h'003f #0 16 h'0040 to h'0043 #1 17 h'0044 to h'0047 address trap #2 18 h'0048 to h'004b internal interrupt (ic) 19 h'004c to h'004f internal interrupt (hsw1) 20 h'0050 to h'0053 irq0 21 h'0054 to h'0057 irq1 22 h'0058 to h'005b irq2 23 h'005c to h'005f irq3 24 h'0060 to h'0063 irq4 25 h'0064 to h'0067 external interrupt irq5 26 h'0068 to h'006b internal interrupt * 2 27 | 31 h'006c to h'006f | h'007c to h'007f reserved 32 | 33 h'0080 to h'0083 | h'0084 to h'0087 internal interrupt * 3 34 | 67 h'0088 to h'008b | h'010c to h'010f section 5 exception handling rev.2.00 jan. 15, 2007 page 94 of 1174 rej09b0329-0200 notes: 1. lower 16 bits of the address. 2. in this lsi, the watch dog timer generates nmis. 3. for details on internal interrupt vectors, see section 6.3.3, interrupt exception vector table. 5.2 reset 5.2.1 overview a reset has the highest exception priority. when the res pin goes low, all processing halts and the lsi enters the reset state. a reset initializes the internal state of the cpu and the registers of on- chip supporting modules. immediately after a reset, interrupt control mode 0 is set. reset exception handling begins when the res pin changes from low to high. the lsis can also be reset by overflow of the watchdog timer. for details, see section 17, watchdog timer (wdt). 5.2.2 reset sequence the lsi enters the re set state when the res pin goes low. to ensure that the chip is reset, hold the res pin low during the oscillation stabilizing time of the clock oscillator when powering on. to reset the chip during operation, hold the res pin low for at least 20 states. for pin states in a reset, see appendix d, port states in the different processing states. when the res pin goes high after being held low for the necessary time, the chip starts reset exception handling as follows: 1. the internal state of the cpu and the registers of the on-chip supporting modules are initialized, and the i bit is set to 1 in ccr. 2. the reset exception vector ad dress is read and transferred to the pc, and program execution starts from the address indicated by the pc. figure 5.2 shows examples of the reset sequence. section 5 exception handling rev.2.00 jan. 15, 2007 page 95 of 1174 rej09b0329-0200 res internal address bus internal read signal internal write signal internal data bus vector fetch (1) (2) (3) (4) : reset exception vector address ((1) = h'0000 or h'000000) : start address (contents of reset exception vector address) : start address ((3) = (2)) : first program instruction (1) (3) high level internal processing fetch of first program instruction (2) (4) figure 5.2 reset sequence (mode 1) 5.2.3 interrupts after reset if an interrupt is accepted after a reset but before the stack pointer (sp) is initialized, the pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immedi ately after a reset. since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: mov.l #xx:32, sp). section 5 exception handling rev.2.00 jan. 15, 2007 page 96 of 1174 rej09b0329-0200 5.3 interrupts interrupt exception handling can be requested by six external sources ( irq5 to irq0 ) and internal sources in the on-chip supporting modules. figure 5.3 shows the interrupt sources and the number of interrupts of each type. the on-chip supporting modules that can request interrupts include the watchdog timer (wdt), prescaler unit (psu), timers a, b, j, l, r a nd x1 (tmr), serial communication interface (sci), a/d converter (adc), i 2 c bus interface (iic), servo circuits, sync detection, data slicer, osd, address trap, etc. each interrupt source has a separate vector address. nmi is the highest-priority interrupt. interrupts are controlled by the interrupt controller. the interrupt controller has two interrupt control modes and can assign interrupts other than nmi to either three priority/mask levels to enable multiplexed interrupt control. for details on interrupts, see section 6, interrupt controller. wdt * 2 (1) psu (1) tmr (15) * 3 sci (4) adc (1) iic (3) * 4 servo circuits (9) synchronized detection (1) address trap (3) interrupts internal interrupts external interrupts notes: numbers in parentheses are the numbers of interrupt sources. in this lsi, the watchdog timer generates nmis. when the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. the number of interrupt sources is eight in the h8s/2197s or h8s/2196s. the number of interrupt sources is one in the h8s/2197s or h8s/2196s. 1. 2. 3. 4. nmi * 1 (1) irq5 to irq0 (6) figure 5.3 interrupt sou rces and number of interrupts section 5 exception handling rev.2.00 jan. 15, 2007 page 97 of 1174 rej09b0329-0200 5.4 trap instruction trap instruction exception handling starts when a trapa instruction is executed. trap instruction exception handling can be executed at a ll times in the program execution state. the trapa instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. table 5.3 shows the status of ccr and exr after execution of trap instruction exception handling. table 5.3 status of ccr and exr after trap instruction exception handling ccr exr * interrupt control mode i ui i2 to i0 t 0 1 ? ? ? 1 1 1 ? ? legend: 1: set to 1 0: cleared to 0 ? : retains value prior to execution. * : does not affect operation in this lsi. section 5 exception handling rev.2.00 jan. 15, 2007 page 98 of 1174 rej09b0329-0200 5.5 stack status after exception handling figures 5.4 and 5.5 show the stack after completion of trap instruction exception handling and interrupt exception handling. ccr ccr * pc (16 bits) sp note: * ignored on return. interrupt control modes 0 and 1 figure 5.4 stack status after exception handling (normal mode) * note: * normal mode is not available for this lsi. ccr pc (24 bits) sp interrupt control modes 0 and 1 figure 5.5 stack status after exception handling (advanced mode) section 5 exception handling rev.2.00 jan. 15, 2007 page 99 of 1174 rej09b0329-0200 5.6 notes on use of the stack when accessing word data or longword data, this ch ip assumes that the lowest address bit is 0. the stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (sp: er7) should always be kept even. use the following instructions to save registers: push.w rn (or mov.w rn, @-sp) push.l ern (or mov.l ern, @-sp) use the following instructions to restore registers: pop.wrn (or mov.w @sp+, rn) pop.lern (or mov.l @sp+, ern) setting sp to an odd value may lead to a malfunction. figure 5.6 shows an example of what happens when the sp value is odd. sp legend: : condition-code register : program counter : general register r1l : stack pointer h'fffefa h'fffefb h'fffefc h'fffefd h'fffeff r1l pc sp ccr pc sp ccr pc r1l sp note: this diagram illustrates an example in which the interrupt control mode is 0, is advanced mode. trapa instruction executed mov.b r1l, @-er7 sp set to h'fffeff data saved above sp contents of ccr lost figure 5.6 operation when sp value is odd section 5 exception handling rev.2.00 jan. 15, 2007 page 100 of 1174 rej09b0329-0200 section 6 interrupt controller rev.2.00 jan. 15, 2007 page 101 of 1174 rej09b0329-0200 section 6 interrupt controller 6.1 overview 6.1.1 features this lsi controls interrupts by means of an interrupt controller. the interrupt controller has the following features: ? two interrupt control modes ? either of two interrupt control modes can be set by means of the intm1 and intm0 bits in the system control register (syscr). ? priorities settable with icr ? an interrupt control register (icr) is provided for setting interrupt priorities. three priority levels can be set for each module for all interrupts except nmi. ? independent vector addresses ? all interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. ? six external interrupt pins ? nmi is the highest-priority interrupt, and is accepted at all times. ? falling edge, rising edge, or both edge detection can be selected for interrupt irq0. ? falling edge or rising edge can be individually selected for interrupts irq5 to irq1. note: * in this lsi, the watch dog timer generates nmis. section 6 interrupt controller rev.2.00 jan. 15, 2007 page 102 of 1174 rej09b0329-0200 6.1.2 block diagram figure 6.1 shows a block diagram of the interrupt controller. irq input internal interrupt requests legend: iegr ienr irqr icr syscr : irq edge select register : irq enable register : irq status register : interrupt control register : system control register interrupt request vector number i, ui irq input unit irqr iegr ienr icr cpu interrupt controller syscr intm1, intm0 ccr priority determina- tion figure 6.1 block diagram of interrupt controller section 6 interrupt controller rev.2.00 jan. 15, 2007 page 103 of 1174 rej09b0329-0200 6.1.3 pin configuration table 6.1 summarizes the pins of the interrupt controller. table 6.1 interrupt controller pins name symbol i/o function external interrupt request 0 irq0 input maskable external interrupts; rising, falling, or both edges can be selected external interrupt requests 1 to 5 irq1 to irq5 input maskable external interrupts: rising, or falling edges can be selected 6.1.4 register configuration table 6.2 summarizes the registers of the interrupt controller. table 6.2 interrupt controller registers name abbreviation r/w initial value address * 1 system control register syscr r/w h'00 h'ffe8 irq edge select register iegr r/w h'00 h'fff0 irq enable register ienr r/w h'00 h'fff1 irq status register irqr r/ (w) * 2 h'00 h'fff2 interrupt control register a icra r/w h'00 h'fff3 interrupt control register b icrb r/w h'00 h'fff4 interrupt control register c icrc r/w h'00 h'fff5 interrupt control register d icrd r/w h'00 h'fff6 port mode register 1 pmr1 r/w h'00 h'ffce notes: 1. lower 16 bits of the address. 2. only 0 can be written, for flag clearing. section 6 interrupt controller rev.2.00 jan. 15, 2007 page 104 of 1174 rej09b0329-0200 6.2 register descriptions 6.2.1 system control register (syscr) 0 0 1 0 ? 2 0 ? 3 1 r 4 0 r/w 5 0 r 0 7 ? ? xrst intm0 intm1 0 6 ?? ?? ? ? bit : initial value : r/w : syscr is an 8-bit readable register that selects the interrupt control mode. only bits 5, 4, 2 and 1 are described here; for details on the other bits, see section 3.2.2, system control register (syscr). syscr is initialized to h'08 by a reset. bits 5 and 4 ? interrupt control mode (intm1, intm0): these bits select one of two interrupt control modes for the interrupt controller. the intm1 bit must not be set to 1. bit 5 bit 4 intm1 intm0 interrupt control mode description 0 0 interrupts are controlled by i bit (initial value) 0 1 1 interrupts are controlled by i and ui bits and icr 1 0 ? cannot be used in this lsi 1 ? cannot be used in this lsi section 6 interrupt controller rev.2.00 jan. 15, 2007 page 105 of 1174 rej09b0329-0200 6.2.2 interrupt control registers a to d (icra to icrd) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 icr4 icr3 icr2 icr1 icr0 0 r/w icr7 r/w r/w r/w icr6 icr5 6 bit : initial value : r/w : the icr registers are four 8-bit readable/writable registers that set the interrupt control level for interrupts other than nmi. the correspondence between icr settings and inte rrupt sources is shown in table 6.3. the icr registers are initialized to h'00 by a reset. bits 7 to 0 ? interrupt control level (icr7 to icr0): set the control level for the corresponding interrupt source. bit n icrn description 0 corresponding interrupt source is control level 0 (non-priority) (initial value) 1 corresponding interrupt source is control level 1 (priority) note: n = 7 to 0 table 6.3 correspondence between in terrupt sources and icr settings icra7 icra6 icra5 icra4 icra3 icra2 icra1 icra0 icra reserved input capture hsw1 irq0 irq1 irq2 irq3 irq4 irq5 sync separator, osd icrb7 icrb6 icrb5 icrb4 icrb3 icrb2 icrb1 icrb0 icrb data slicer sync separator servo (drum, capstan latch) timer a timer b time r j timer r timer l icrc7 icrc6 icrc5 icrc4 icrc3 icrc2 icrc1 icrc0 icrc timer x1 * synchro- nized detection watchdog timer servo iic1 sci1 (uart) iic0 * a/d icrd icrd7 icrd6 icrd5 icrd4 icrd3 icrd2 icrd1 icrd0 hsw2 reserved reserved reserved reserved reserved reserved reserved note: * this bit has no function in the h8s/2197s or h8s/2196s. section 6 interrupt controller rev.2.00 jan. 15, 2007 page 106 of 1174 rej09b0329-0200 6.2.3 irq enable register (ienr) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 5 0 0 7 r/w r/w r/w irq5e irq4e irq3e irq2e irq1e irq0e 0 6 ?? ?? bit : initial value : r/w : ienr is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests irq5 to irq0. ienr is initialized to h'00 by a reset. bits 7 and 6 ? reserved: these bits are always read as 0. do not write 1 to them. bits 5 to 0 ? irq5 to irq0 enable (irq5e to irq0e): these bits select whether irq5 to irq0 are enabled or disabled. bit n irqne description 0 irqn interrupt disabled (initial value) 1 irqn interrupt enabled note: n = 5 to 0 section 6 interrupt controller rev.2.00 jan. 15, 2007 page 107 of 1174 rej09b0329-0200 6.2.4 irq edge select registers (iegr) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 5 0 0 7 ? ? r/w r/w r/w irq4eg r/w irq5eg irq3eg irq2eg irq1eg irq0eg1 irq0eg0 0 6 bit : initial value : r/w : iegr is an 8-bit readable/writable register that selects detected edge of the input at pins irq5 to irq0 . iegr register is initialized to h'00 by a reset. bit 7 ? reserved: this bit is always read as 0. do not write 1 to it. bits 6 to 2 ? irq5 to irq1 pins detected edge select (irq5eg to irq1eg): these bits select detected edge for interrupts irq5 to irq1. bits 6 to 2 irqneg description 0 interrupt request generated at falling edge of irqn pin input (initial value) 1 interrupt request generated at rising edge of irqn pin input note: n = 5 to 1 bits 1 and 0 ? irq0 pin detected edge select (irq0eg1, irq0eg0) : these bits select detected edge for interrupt irq0. bit 1 bit 0 irq0eg1 irq0eg0 description 0 0 interrupt request generated at falling edge of irq0 pin input (initial value) 0 1 interrupt request generated at rising edge of irq0 pin input 1 * interrupt request generated at both falling and rising edges of irq0 pin input legend: * don't care section 6 interrupt controller rev.2.00 jan. 15, 2007 page 108 of 1174 rej09b0329-0200 6.2.5 irq status register (irqr) 0 0 1 0 r/(w) * 2 0 r/(w) * 3 0 4 0 r/(w) * 5 0 0 7 r/(w) * r/(w) * r/(w) * irq5f irq4f irq3f irq2f irq1f irq0f 0 6 ?? ?? note: * only 0 can be written, to clear the flag. bit : initial value : r/w : irqr is an 8-bit readable/writable register that indicates the status of irq5 to irq0 interrupt requests. irqr is initialized to h'00 by a reset. bits 7 and 6 ? reserved: these bits are always read as 0. do not write 1 to them. bits 5 to 0 ? irq5 to irq0 flags: these bits indicate the status of irq5 to irq0 interrupt requests. bit n irqnf description 0 [clearing conditions] (initial value) (1) cleared by reading irqnf set to 1, then writing 0 in irqnf (2) when irqn interrupt exception handling is executed 1 [setting conditions] (1) when a falling edge occurs in irqn input while falling edge detection is set (irqneg = 0) (2) when a rising edge occurs in irqn input while rising edge detection is set (irqneg = 0) (3) when a falling or rising edge occurs in irq0 input while both-edge detection is set (irq0eg1 = 1) note: n = 5 to 0 section 6 interrupt controller rev.2.00 jan. 15, 2007 page 109 of 1174 rej09b0329-0200 6.2.6 port mode register 1 (pmr1) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 0 r/w pmr17 pmr16 pmr15 pmr14 pmr13 pmr12 pmr11 pmr10 r/w r/w r/w 6 bit : initial value : r/w : port mode register 1 (pmr1) controls pin function switching-over of port 1. switching is specified for each bit. pmr1 is an 8-bit readable/writable register and is initialized to h'00 by a reset. only bits 5 to 0 are explained here. for details, see section 10.3.2, register configuration. bits 5 to 0 ? p15/ irq5 to p10/ irq0 pin switching (pmr15 to pmr10): these bits are for setting the p1n/ irqn pin as the input pin for p1n or as the irqn pin for external interrupt request input. bit n pmr1n description 0 p1n/ irqn pin functions as the p1n input/output pin (initial value) 1 p1n/ irqn pin functions as the irqn input/output pin note: n = 5 to 0 notes on switching the pin function by pmr1 are as follows: ? when the port is set as the ic input pin or irq5 to irq0 input pin, the pin level must be high or low regardless of active mode or power-down mode. do not set the pin level at medium. ? switching the pin function of p16/ ic or p15/ irq5 to p10/ irq0 may be mistakenly identified as edge detection and detection signal may be generated. to prevent this, operate as follows: ? set the interrupt enable/disable flag to disable before switching the pin function. ? clear the applicable interrupt request flag to 0 after switching the pin function and executing another instruction. section 6 interrupt controller rev.2.00 jan. 15, 2007 page 110 of 1174 rej09b0329-0200 program example : mov.b r0l,@ienr ?????? interrupt disabled mov.b r1l,@pmr1 ?????? pin function change nop ?????? optional instruction bclr m @irqr ?????? applicable interrupt clear mov.b r1l,@ienr ?????? interrupt enabled : 6.3 interrupt sources interrupt sources comprise external interrupts (irq5 to irq0) and internal interrupts. 6.3.1 external interrupts there are six external interrupt s ources; irq5 to irq0. of these, irq1 to irq0 can be used to restore this chip from standby mode. ? irq5 to irq0 interrupts: interrupts irq5 to irq0 are requested by an input signal at pins irq5 to irq0 . interrupts irq5 to irq0 have the following features: (a) using iegr, it is possible to select whether an interrupt is requested by a falling edge, rising edge, or both edges, at pin irq0 . (b) using iegr, it is possible to select whether an interrupt is requested by a falling edge or rising edge at pins irq5 to irq1 . (c) enabling or disabling of interrupt requests irq5 to irq0 can be selected with ienr. (d) the interrupt control level can be set with icr. (e) the status of interrupt requests irq5 to irq0 is indicated in irqr. irqr flags can be cleared to 0 by software. section 6 interrupt controller rev.2.00 jan. 15, 2007 page 111 of 1174 rej09b0329-0200 figure 6.2 shows a block diagram of interrupts irq5 to irq0. clear signal r s q edge detection circuit irqneg irqnf irqne note: n = 5 to 0 irqn interrupt request irqn input figure 6.2 block diagram of interrupts irq5 to irq0 figure 6.3 shows the timing of irqnf setting. internal irqnf irqn input pin figure 6.3 timing of irqnf setting the vector numbers for irq5 to irq0 interrupt exception handling are 21 to 26. upon detection of irq5 to irq0 interrupts, the applicable pin is set in the port register 1 (pmr1) as irqn pin. section 6 interrupt controller rev.2.00 jan. 15, 2007 page 112 of 1174 rej09b0329-0200 6.3.2 internal interrupts there are 38 sources for internal interrupts from on-chip supporting modules. ? for each on-chip supporting module there are flag s that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. if any one of these is set to 1, an interrupt request is issued to the interrupt controller. ? the interrupt control level can be set by means of icr. ? the nmi is the highest priority interrupt and is always accepted regardless of the control mode and cpu interrupt mask bit. in this lsi, nmis are used as interrupts generated by the watchdog timer. section 6 interrupt controller rev.2.00 jan. 15, 2007 page 113 of 1174 rej09b0329-0200 6.3.3 interrupt exception vector table table 6.4 shows interrupt exception handling sources , vector addresses, and interrupt priorities. for default priorities, the lower the vector number, the higher the priority. priorities among modules can be set by means of ic r. the situation when two or more modules are set to the same priority, an d priorities within a module, are fixed as shown in table 6.4. table 6.4 interrupt sources, vector addresses, and interrupt priorities priority interrupt source origin of interrupt source vector no. vector address icr remarks reset external pin 0 h'0000 to h'0003 ? ? 1 h'0004 to h'0007 ? ? 2 h'0008 to h'000b ? ? 3 h'000c to h'000f ? ? 4 h'0010 to h'0013 ? reserved ? 5 h'0014 to h'0017 ? direct transition instruction 6 h'0018 to h'001b ? nmi watchdog timer 7 h'001c to h'001f ? trapa#0 8 h'0020 to h'0023 ? trapa#1 9 h'0024 to h'0027 ? trapa#2 10 h'0028 to h'002b ? trap instruction trapa#3 instruction 11 h'002c to h'002f ? 12 h'0030 to h'0033 13 h'0034 to h'0037 14 h'0038 to h'003b high low reserved ? 15 h'003c to h'003f ? section 6 interrupt controller rev.2.00 jan. 15, 2007 page 114 of 1174 rej09b0329-0200 priority interrupt source origin of interrupt source vector no. vector address icr remarks #0 16 h'0040 to h'0043 #1 17 h'0044 to h'0047 address trap #2 atc 18 h'0048 to h'004b ? ic psu 19 h'004c to h'004f icra6 hsw1 servo circuit 20 h'0050 to h'0053 icra5 irq0 21 h'0054 to h'0057 icra4 irq1 22 h'0058 to h'005b icra3 irq2 23 h'005c to h'005f irq3 24 h'0060 to h'0063 icra2 irq4 25 h'0064 to h'0067 irq5 external pin 26 h'0068 to h'006b icra1 external v interrupt sync separator 27 h'006c to h'006f icra0 osd v interrupt osd 28 h'0070 to h'0073 data slicer odd field interrupt data slicer 29 h'0074 to h'0077 icrb7 data slicer even field interrupt 30 h'0078 to h'007b noise interrupt sync separator 31 h'007c to h'007f icrb6 reserved ? 32 h'0080 to h'0083 ? 33 h'0084 to h'0087 drum latch 1 (speed) servo circuit 34 h'0088 to h'008b icrb5 capstan latch 1 (speed) 35 h'008c to h'008f tmai timer a 36 h'0090 to h'0093 icrb4 tmbi timer b 37 h'0094 to h'0097 icrb3 high tmj1i timer j 38 h'0098 to h'009b icrb2 tmj2i 39 h'009c to h'009f tmr1i timer r 40 h'00a0 to h'00a3 icrb1 tmr2i 41 h'00a4 to h'00a7 tmr3i 42 h'00a8 to h'00ab low tmli timer l 43 h'00ac to h'00af icrb0 section 6 interrupt controller rev.2.00 jan. 15, 2007 page 115 of 1174 rej09b0329-0200 priority interrupt source origin of interrupt source vector no. vector address icr remarks icxa * timer x1 * 44 h'00b0 to h'00b3 icxb * 45 h'00b4 to h'00b7 icxc * 46 h'00b8 to h'00bb icxd * 47 h'00bc to h'00bf ocx1 * 48 h'00c0 to h'00c3 ocx2 * 49 h'00c4 to h'00c7 ovfx * 50 h'00c8 to h'00cb icrc7 vd interrupts sync signal detection 51 h'00cc to h'00cf icrc6 reserved ? 52 h'00d0 to h'00d3 8-bit interval timer watchdog timer 53 h'00d4 to h'00d7 icrc5 ctl 54 h'00d8 to h'00db drum latch 2 (speed) 55 h'00dc to h'00df capstan latch 2 (speed) 56 h'00e0 to h'00e3 drum latch 3 (phase) 57 h'00e4 to h'00d7 capstan latch 3 (phase) servo circuit 58 h'00e8 to h'00eb icrc4 iic1 iic1 59 h'00ec to h'00ef icrc3 eri 60 h'00f0 to h'00f3 rxi 61 h'00f4 to h'00f7 txi 62 h'00f8 to h'00fb sci1 tei sci1 (uart) 63 h'00fc to h'00ff icrc2 64 h'0100 to h'0103 iic0 * ddcsw * iic0 * 65 h'0104 to h'0107 icrc1 a/d conversion end a/d 66 h'0108 to h'010b icrc0 high low hsw2 servo circuit 67 h'010c to h'010f icrd7 note: * not available in the h8s/2197s or h8s/2196s. section 6 interrupt controller rev.2.00 jan. 15, 2007 page 116 of 1174 rej09b0329-0200 6.4 interrupt operation 6.4.1 interrupt control modes and interrupt operation interrupt operations in this lsi differ depending on the interrupt control mode. the nmi interrupt* and address trap interrupts are accep ted at all times except in the reset state. in the case of irq interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. clearing an enable bit to 0 di sables the corresponding interrupt request. interrupt sources in which the enable bits are set to 1 are controlled by the interrupt controller. table 6.5 shows the interrupt control modes. the interrupt controller performs interrupt control according to th e interrupt control mode set by the intm1 and intm0 bits in syscr, the priorities set in icr, and the masking state indicated by the i and ui bits in the cpu?s ccr. note: * in this lsi, the nmi interrupt is generated by the watchdog timer. table 6.5 interrupt control modes syscr interrupt control mode intm1 intm0 priority setting register interrupt mask bits description 0 0 0 icr i interrupt mask control is performed by the i bit priority can be set with icr 1 1 icr i, ui 3-level interrupt mask control is performed by the i and ui bits priority can be set with icr section 6 interrupt controller rev.2.00 jan. 15, 2007 page 117 of 1174 rej09b0329-0200 figure 6.4 shows a block diagram of the priority decision circuit. interrupt control modes 0 and 1 i interrupt source ui vector number interrupt acceptance control and 3-level mask control default priority determination i c r figure 6.4 block diagram of interrupt priority determination operation ? interrupt acceptance control and 3-level cont rol: in interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask c ontrol is performed by means of the i and ui bits in ccr, and icr (control level). table 6.6 shows the interrupts sel ected in each interrupt control mode. table 6.6 interrupts selected in each interrupt control mode interrupt mask bit interrupt control mode i ui selected interrupts 0 * all interrupts (control level 1 has priority) 0 1 * nmi * 1 and address trap interrupts 1 0 * all interrupts (control level 1 has priority) 1 0 nmi * 1 , address trap and control level 1 interrupts 1 nmi * 1 and address trap interrupts legend: * don't care note: 1. in this lsi, the nmi interrupt is generated by the watchdog timer. ? default priority determination: if the same value is set for icr, acceptance of multiple interrupts is enabled, and so on ly the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. interrupt sources with a lower priority than the accep ted interrupt source are held pending. table 6.7 shows operations and control signal functions in each interrupt control mode. section 6 interrupt controller rev.2.00 jan. 15, 2007 page 118 of 1174 rej09b0329-0200 table 6.7 operations and control signal functions in each interrupt control mode setting interrupt acceptance control, 3-level control interrupt control mode intm1 intm0 i ui icr default priority determination 0 0 0 { im ? pr { 1 1 { im im pr { legend: { : interrupt operation control performed im: used as interrupt mask bit pr: sets priority ? : not used 6.4.2 interrupt control mode 0 enabling and disabling of irq interrupts and on-chip supporting module interrupts can be set by the i bit in the cpu?s ccr, and icr. interrupts are enabled when the i bit is cleared to 0, and disabled when set to 1. control level 1 interrupt sources have higher priority. figure 6.5 shows a flowchart of the inte rrupt acceptance operation in this case. ? if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. ? when interrupt requests are sent to the interrupt controller, a control level 1 interrupt, according to the contro l level set in icr, has priority for se lection, and other interrupt requests are held pending. if a number of interrupt requests with the same control level setting are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 6.4 is selected. ? the i bit is then referenced. if th e i bit is cleared to 0, the inte rrupt request is accepted. if the i bit is set to 1, only an nmi * 1 or an address trap interrupt is accepted, and other interrupt requests are held pending. ? when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. ? the pc and ccr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruc tion to be executed after returning from the interrupt handling routine. ? next, the i bit in ccr is set to 1. this disables all interrupts except nmi* and address trap. ? a vector address is generated for the accept ed interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. section 6 interrupt controller rev.2.00 jan. 15, 2007 page 119 of 1174 rej09b0329-0200 note: * in this lsi, the nmi interrupt is generated by the watchdog timer. program execution state interrupt generated? nmi address trap interrupt? control level 1 interrupt? i c i = 0 yes yes yes yes yes yes yes no yes yes yes yes no no no no no no save pc and ccr i 1 read vector address branch to interrupt handling routine i c no no h s w 1 h s w 1 h s w 2 h s w 2 hold pending figure 6.5 flowchart of procedu re up to interrupt acceptance in interrupt control mode 0 section 6 interrupt controller rev.2.00 jan. 15, 2007 page 120 of 1174 rej09b0329-0200 6.4.3 interrupt control mode 1 three-level masking is implemented for irq interrupts and on-chip supporting module interrupts by means of the i and ui bits in the cpu?s ccr and icr. ? control level 0 interrupt requests are enabled when the i bit is cleared to 0, and disabled when set to 1. ? control level 1 interrupt requests are enabled when the i bit or ui bit is cleared to 0, and disabled when both the i bit and the ui bit are set to 1. for example, if the interrupt enable bit for an interrupt request is set to 1, and h'04, h'00, h'00 and h'00 are set in icra, icrb, icrc and icrd respectively, (i.e. irq2 interrupt is set to control level 1 and other interrupts to control level 0), the situation is as follows: ? when i = 0, all interrupts are enabled (priority order: nmi > irq2 > ic > hsw1 > ...) ? when i = 1 and ui = 0, only nmi, address trap and irq2 interrupts are enabled ? when i = 1 and ui = 1, only nmi and address trap interrupts are enabled figure 6.6 shows the state transitions in these cases. only nmi, address trap and irq2 interrupts enabled all interrupts enabled exception handling execution or ui 1 exception handling execution or i 1, ui 1 i 0 i 1, ui 0 ui 0 i 0 only nmi and address trap interrupts enabled figure 6.6 example of state transitions in interrupt control mode 1 figure 6.7 shows an operation fl owchart of interrupt reception. section 6 interrupt controller rev.2.00 jan. 15, 2007 page 121 of 1174 rej09b0329-0200 (1) if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. (2) when interrupt requests are sent to the interrupt controller, a control level 1 interrupt, according to the contro l level set in icr, has priority for se lection, and other interrupt requests are held pending. if a number of interrupt requests with the same control level setting are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 6.4 is selected. (3) the i bit is then referenced. if the i bit is cleared to 0, the ui bit has no effect. an interrupt request set to interrupt control leve l 0 is accepted when the i bit is cleared to 0. if the i bit is set to 1, only nmi* and address trap interrupts are accepted, and other interrupt requests are held pending. an interrupt request set to interrupt control level 1 has priority over an interrupt request set to interrupt control level 0, and is accep ted if the i bit is cleared to 0, or if the i bit is set to 1 and the ui bit is cleared to 0. when both the i bit and the ui bit are set to 1, only nmi* and address trap interrupts are accepted, and other interrupt requests are held pending. (4) when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. (5) the pc and ccr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruc tion to be executed after returning from the interrupt handling routine. (6) next, the i and ui bits in ccr are set to 1. this masks all interrupts except nmi* and address trap. (7) a vector address is generated for the acce pted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. note: * in this lsi, the nmi interrupt is generated by the watchdog timer. section 6 interrupt controller rev.2.00 jan. 15, 2007 page 122 of 1174 rej09b0329-0200 program execution state nmi i c yes yes yes yes yes yes yes no yes yes yes yes no no no no no no i c no no h s w 1 h s w 1 h s w 2 h s w 2 yes no yes no interrupt generated? address trap interrupt? control level 1 interrupt? i = 0 i = 0 ui = 0 save pc and ccr i 1, ui 1 read vector address branch to interrupt handling routine hold pending figure 6.7 flowchart of procedu re up to interrupt acceptance in interrupt control mode 1 section 6 interrupt controller rev.2.00 jan. 15, 2007 page 123 of 1174 rej09b0329-0200 6.4.4 interrupt exception handling sequence figure 6.8 shows the interrupt exception handling sequence. the example shown is for the case where interrupt control 0 is set in advanced mo de, and the program area and stack area are in on- chip memory. (1) (1) instruction prefetch address (not executed. this is the contents of the saved pc, the return address.) saved pc and saved ccr vector address interrupt handling routine start address (vector address contents) interrupt handling routine start address ((13) = (10)(12)) first instruction of interrupt handling routine (2)(4) (6)(8) (10)(12) (13) (9)(11) (14) (3) (5) (7) (9) (11) (13) internal address bus interrupt request signal internal read signal internal write signal internal data bus (2) (4) (6) (8) (10) (12) (14) stack vector fetch interrupt level determination wait for end of instruction interrupt acceptance internal operation internal operation instruction prefetch interrupt handling routine instruction prefetch instruction code (not executed.) (3) instruction prefetch address (not executed.) (5) sp-2 (7) sp-4 figure 6.8 interrupt exception handling section 6 interrupt controller rev.2.00 jan. 15, 2007 page 124 of 1174 rej09b0329-0200 6.4.5 interrupt response times table 6.8 shows interrupt response times-the interv al between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. the symbols used in table 6.8 are explained in table 6.9. table 6.8 interrupt response times no. number of states advanced mode 1 interrupt priority determination * 1 3 2 number of wait states until executing instruction ends * 2 1 to 19 + 2 ? s i 3 pc, ccr stack save 2 ? s k 4 vector fetch 2 ? s i 5 instruction fetch * 3 2 ? s i 6 internal processing * 4 2 total (using on-chip memory) 12 to 32 notes: 1. two states in case of internal interrupt. 2. refers to mulxs and divxs instruction. 3. prefetch after interrupt acceptance and interrupt handling routine prefetch. 4. internal processing after interrupt acceptance and internal processing after vector fetch. table 6.9 number of states in in terrupt handling routine execution object of access symbol internal memory instruction fetch s i 1 stack operation sk 1 section 6 interrupt controller rev.2.00 jan. 15, 2007 page 125 of 1174 rej09b0329-0200 6.5 usage notes 6.5.1 contention between interru pt generation and disabling when an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. in other words, when an interrupt enable bit is cleared to 0 by an instru ction such as bclr or mov, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. however, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. the same also applies when an interr upt source flag is cleared to 0. figure 6.9 shows an example in which the ocia e bit in timer x1 tier is cleared to 0. tier address internal address bus internal write signal ociae ocfa ocia interrupt signal tier write cycle by cpu ocia interrupt exception handling figure 6.9 contention between in terrupt generation and disabling section 6 interrupt controller rev.2.00 jan. 15, 2007 page 126 of 1174 rej09b0329-0200 the above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 6.5.2 instructions that disable interrupts instructions that disable interrupts are ldc, andc, orc, and xorc. after any of these instructions is executed, all interrupts including nmi are disabled and the next instruction is always executed. when the i bit or ui bit is set by one of these instructions, the new value becomes valid two states after ex ecution of the instruction ends. 6.5.3 interrupts during execution of eepmov instruction interrupt operation differs between the eepmov.b instruction and the eepmov.w instruction. with the eepmov.b instruction, an interrupt request (including nmi) issued during the transfer is not accepted until the move is completed. with the eepmov.w instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. the pc value saved on the stack in this case is the address of the next instruction. therefore, if an interrupt is generated during execution of an eepmov.w instruction, the following coding should be used. l1: eepmov.w mov.w r4,r4 bne l1 section 7 rom rev.2.00 jan. 15, 2007 page 127 of 1174 rej09b0329-0200 section 7 rom 7.1 overview the h8s/2199r has 128 kbytes or 256 kbytes of on-chip rom (flash memory or mask rom), the h8s/2198r has 112 kbytes, the h8s/2197r and h8s/2197s have 96 kbytes, and the h8s/2196r and h8s/2196s have 80 kbytes*. the rom is connected to the cpu by a 16-bit data bus. the cpu accesses both byte and word data in one state, enabling faster instruction fetches and higher processing speed. the flash memory versions of the h8s/2199r can be erased and programmed on-board as well as with a general-purpose prom programmer. note: * for details on product line-up, refer to section 1, overview. 7.1.1 block diagram figure 7.1 shows a block diagram of the rom. internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'000000 h'000002 h'01fffe h'000001 h'000003 h'01ffff figure 7.1 rom block diagram (h8s/2199r) section 7 rom rev.2.00 jan. 15, 2007 page 128 of 1174 rej09b0329-0200 7.2 overview of flash memory 7.2.1 features the features of the flash memory are summarized below. ? four flash memory operating modes ? program mode ? erase mode ? program-verify mode ? erase-verify mode ? programming/erase methods the flash memory is programmed 128 bytes at a time. erasing is performed by block erase (in single-block units). when erasing all blocks, the individual blocks must be erased sequentially. block erasing can be performed as required on 4-kbyte, 32-kbyte, and 64-kbyte blocks. (in osd rom, block erasing can be performed on 1-kbyte, 2-kbyte, and 28-kbyte blocks). ? programming/erase times the flash memory programming time is 10 ms (typ.) for simultaneous 128-byte programming, equivalent to 78 s (typ.) per byte, and the erase time is 100 ms (typ.) per block. ? reprogramming capability the flash memory can be reprogrammed up to 100 times. ? on-board programming modes there are two modes in which flash memory can be programmed/erased/verified on-board: ? boot mode ? user program mode ? automatic bit rate adjustment if data transfer on boot mode, automatic adjustment is possible at host transfer bit rates and lsi's bit rates. ? protect modes there are three protect modes, hardware, soft ware, and error protect, which allow protected status to be designated for flash memory program/erase/verify operations. ? programmer mode flash memory can be programmed/erased in programmer mode, using a prom programmer, as well as in on-board programming mode. section 7 rom rev.2.00 jan. 15, 2007 page 129 of 1174 rej09b0329-0200 7.2.2 block diagram figure 7.2 shows a block diagram of the flash memory. module bus bus interface/controller flash memory (256 kbytes) operat- in g mode flmcr1 stcr flmcr1 flmcr2 ebr1 ebr2 : serial/timer control re g ister : flash memory control re g ister 1 : flash memory control re g ister 2 : erase block re g ister 1 : erase block re g ister 2 le g end: internal address bus internal data bus (16 bits) stcr fwe pin mode pin flmcr2 ebr1 flash memory (osd rom) (32 kbytes) ebr2 figure 7.2 block diagram of flash memory (h8s/2199r only) section 7 rom rev.2.00 jan. 15, 2007 page 130 of 1174 rej09b0329-0200 7.2.3 flash memory operating modes mode transitions when each mode pin and the fwe pin are set in th e reset state and a reset-start is executed, the mcu enters one of the operating modes shown in figure 7.3. in user mode, flash memory can be read but not programmed or erased. flash memory can be programmed and erased in boot mode, user program mode, and programmer mode. boot mode on-board pro g ram mode user pro g ram mode user mode reset state pro g rammer mode fwe = 1, md0 = 0, p12 = p13 = p14 = 1 md0 = 0, p12 = p13 = 1, p14 = 0 res = 0 res = 0 fwe = 1 swe = 1 fwe = 0 or swe = 0 res = 0 md1 = 1, fwe = 0 res = 0 only make a transition between user mode and user pro g ram mode when the cpu is not accessin g the flash memory. note: figure 7.3 flash memory mode transitions section 7 rom rev.2.00 jan. 15, 2007 page 131 of 1174 rej09b0329-0200 on-board programming modes ? boot mode section 7 rom rev.2.00 jan. 15, 2007 page 132 of 1174 rej09b0329-0200 ? user program mode section 7 rom rev.2.00 jan. 15, 2007 page 133 of 1174 rej09b0329-0200 differences between boot mode and user program mode boot mode user program mode entire memory erase yes yes block erase no yes programming control program * program/program-verify erase/erase-verify program/program-verify note: * to be provided by the user, in accordance with the recommended algorithm. block configuration the main rom area is divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. the osd rom area is divided into two 1-kbyte blocks, one 2-kbyte block, and one 28- kbyte block. address h'00000 address h'3ffff 256 kbytes 64 kbytes 64 kbytes 64 kbytes 32 kbytes address h'40000 address h'47fff 32 kbytes osd rom area main rom area 28 kbytes 2 kbytes 1 kbyte 1 kbyte 4 kbytes 8 figure 7.6 flash memory block configuration section 7 rom rev.2.00 jan. 15, 2007 page 134 of 1174 rej09b0329-0200 7.2.4 pin configuration the flash memory is controlled by means of the pins shown in table 7.1. table 7.1 flash memory pins pin name abbreviation i/o function reset res input reset flash write enable fwe input flash program/erase protection by hardware mode 0 md0 input sets this lsi operating mode port 12 p12 input sets this lsi operating mode when md0 = 0 port 13 p13 input sets this lsi operating mode when md0 = 0 port 14 p14 input sets this lsi operating mode when md0 = 0 transmit data so1 output serial transmit data output receive data si1 input serial receive data input 7.2.5 register configuration table 7.2 shows the registers used to control the flash memory when enabled. in order for these registers to be accessed, the flshe bit must be set to 1 in stcr. table 7.2 flash memory registers register name abbreviation r/w initial value address * 1 flash memory control register 1 flmcr1 * 5 r/w * 2 h'00 * 3 h'fff8 flash memory control register 2 flmcr2 * 5 r/w * 2 h'00 * 4 h'fff9 erase block register 1 ebr1 * 5 r/w * 2 h'00 * 4 h'fffa erase block register 2 ebr2 * 5 r/w * 2 h'00 * 4 h'fffb serial/timer control register stcr r/w h'00 h'ffee notes: 1. lower 16 bits of the address. 2. when the fwe bit in flmcr1 is not set at 1, writes are disabled. 3. when a high level is input to the fwe pin, the initial value is h'80. 4. when a low level is input to the fwe pin, or if a high level is input and the swe bit in flmcr1 is not set, these registers are initialized to h'00. 5. flmcr1, flmcr2, ebr1, and ebr2 are 8-bit registers. only byte accesses are valid for these registers, the access requiring 2 states. section 7 rom rev.2.00 jan. 15, 2007 page 135 of 1174 rej09b0329-0200 7.3 flash memory register descriptions 7.3.1 flash memory control register 1 (flmcr1) 7 fwe ? * r 6 swe1 0 r/w 5 esu1 0 r/w 4 psu1 0 r/w 3 ev1 0 r/w 0 p1 0 r/w 2 pv1 0 r/w 1 e1 0 r/w bit initial value r/w : : : note: * determined by the state of the fwe pin. flmcr1 is an 8-bit register used for flash memory operating mode control. with addresses h'00000 to h'3ffff, program-verify mode or erase-verify mode is entered by setting swe to 1 when fwe = 1, then setting the pv1 bit and ev1 bit. program mode is entered by setting swe1 when fwe = 1, then setting the swe1 bit and psu1, and finally setting the p1 bit. with addresses h'00000 to h'3ffff, erase mode is entered by setting sw e1 when fwe = 1, then setting the esu1 bit, and finally setting the e1 bit. flmcr1 is initialized by a reset, in standby mode or watch mode, when a low level is input to the fwe pin, and when a high level is input to the fwe pin while the swe1 bit in flmcr1 is not set to 1. its initial value is h'80 when a high level is input to the fwe pin, and h'00 when a low level is input. when on-chip flash memory is disabled, a read will return h'00, and writes are invalid. writes to the swe1 bit in flmcr1 are enabled only when fwe = 1; writes to the esu1, psu1, ev1 and pv1 bits only when fwe = 1 and swe1 = 1; writes to the e1 bit only when fwe = 1, swe1 = 1, and esu1 = 1; and writes to the p1 bit only when fwe = 1, swe1 = 1, and psu1 = 1. bit 7 ? flash write enable (fwe): sets hardware protection against flash memory programming/erasing. bit 7 fwe description 0 when a low level is input to the fwe pin (hardware-protected state) 1 when a high level is input to the fwe pin section 7 rom rev.2.00 jan. 15, 2007 page 136 of 1174 rej09b0329-0200 bit 6 ? software write enable (swe): enables or disables flash memory programming. swe should be set before setting bits 5 to 0, bits 7 to 0 in ebr1, and bits 3 to 0 in ebr2. bit 6 swe1 description 0 writes are disabled (initial value) 1 writes are enabled [setting condition] setting is available when fwe = 1 is selected bit 5 ? erase set-up 1 (esu1): prepares for erase mode. esu1 should be set to 1 before setting the e1 bit in flmcr1 to 1. do not set the swe1, psu1, ev1, pv1, e1, or p1 bit at the same time. bit 5 esu1 description 0 erase set-up cleared (initial value) 1 transition to erase set-up mode [setting condition] setting is available when fwe = 1 and swe1 = 1 are selected bit 4 ? program set-up 1 (psu1): prepares for program mode. psu1 should be set to 1 before setting the p1 bit in flmcr1 to 1. do not set the swe1, esu1, ev1, pv1, e1 or p1 bit at the same time. bit 4 psu1 description 0 program set-up cleared (initial value) 1 transition to program set-up mode [setting condition] setting is available when fwe = 1 and swe1 = 1 are selected section 7 rom rev.2.00 jan. 15, 2007 page 137 of 1174 rej09b0329-0200 bit 3 ? erase-verify (ev1): selects erase-verify mode trans ition or clearing. do not set the swe1, esu1, psu1, pv1, e1, or p1 bit at the same time. bit 3 ev1 description 0 erase-verify mode cleared (initial value) 1 transition to erase-verify mode [setting condition] setting is available when fwe = 1 and swe1 = 1 are selected bit 2 ? program-verify (pv1): selects program-verify mode transition or clearing. do not set the swe1, esu1, psu1, ev1, e1, or p1 bit at the same time. bit 2 pv1 description 0 program-verify mode cleared (initial value) 1 transition to program-verify mode [setting condition] setting is available when fwe = 1 and swe1 = 1 are selected bit 1 ? erase (e1): selects erase mode transition or clearin g. do not set the swe1, esu1, psu1, ev1, pv1, or p1 bit at the same time. bit 1 e1 description 0 erase mode cleared (initial value) 1 transition to erase mode [setting condition] setting is available when fwe = 1, swe1 = 1, and esu1 = 1 are selected section 7 rom rev.2.00 jan. 15, 2007 page 138 of 1174 rej09b0329-0200 bit 0 ? program (p1): selects program mode transition or clearing (target address range : h'00000 to h'3ffff) . do not set the swe1, psu1, esu1, ev1, pv1, or e1 bit at the same time. bit 0 p1 description 0 program mode cleared (initial value) 1 transition to program mode [setting condition] setting is available when fwe = 1, swe1 = 1, and psu1 = 1 are selected 7.3.2 flash memory control register 2 (flmcr2) 7 fler 0 r 6 swe2 0 r/w 5 esu2 0 r/w 4 psu2 0 r/w 3 ev2 0 r/w 0 p2 0 r/w 2 pv2 0 r/w 1 e2 0 r/w bit initial value r/w : : : flmcr2 is an 8-bit register used for flash memory operating control mode. with addresses h'40000 to h'47fff, program-verify mode and erase-verify mode is entered by setting swe2 when fwe (flmcr1) = 1, then setting the ev2 bit and the pv2 bit. program mode is entered by setting swe2 when fwe (flmcr1) = 1, then setting the swe2 bit and psu2 bit, and finally setting the p2 bit. with addresses h'40000 to h'47fff, erase m ode is entered by setting swe2 when fwe (flmcr1) = 1, then setting the esu2 bit , and finally setting the e2 bit. flmcr2 is initialized to h'00 by a reset, in standby mode or watch mode, when a low level is input to the fwe pin, and when a high level is input to the fwe pin while the swe2 bit in flmcr2 is set to 1. fler can be initialized only by a reset. writes to the swe2 bit in the flmcr2 are enabled only when fwe (flmcr1) = 1; writes to the esu2, psv2, ev2, and pv2 bits only when fwe (flmcr1) = 1 and swe2 = 1; writes to the e2 bit only when fwe (flmcr1) = 1, sw2 = 1, and esu2 = 1; writes to the p2 bit only when fwe (flmcr1) = 1, swe2 = 1, and psu2 = 1. section 7 rom rev.2.00 jan. 15, 2007 page 139 of 1174 rej09b0329-0200 bit 7 ? flash memory error (fler): indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error- protection state. bit 7 fler description 0 flash memory is operating normally flash memory program/erase protection (error protection) is disabled [clearing condition] reset (initial value) 1 an error has occurred during flash memory programming/erasing flash memory program/erase protection (error protection) is enabled [setting condition] see section 7.6.3, error protection bit 6 ? software write enable 2 (swe2): enables or disables flash memory programming (target address range: h'40000 to h'47fff). sw2 shoul d be set when setting bits 5 to 0 and bits 7 to 4 in ebr2. bit 6 swe2 description 0 writes are disabled (initial value) 1 writes are enabled [setting condition] setting is available when fwe = 1 is selected bit 5 ? erase set-up 2 (esu2): prepares for erase mode. (target address range: h'40000 to h'47fff). do not set the psu2, ev2, pv2, w2, p2 bits at the same time. bit 5 esu2 description 0 erase set-up cleared (initial value) 1 transition to erase set-up mode [setting condition] setting is enabled when fwe = 1 and swe2 = 1 are selected section 7 rom rev.2.00 jan. 15, 2007 page 140 of 1174 rej09b0329-0200 bit 4 ? program set-up 2 (psu2): prepares for program mode (target address rang: h'40000 to h'47fff). do not set the esu2, ev2, pv2, e2, p2 bits at the same time. bit 4 psu2 description 0 program set-up cleared (initial value) 1 transition to program set-up mode [setting condition] setting is enabled when fwe = 1 and swe2 = 1 are selected bit 3 ? erase-verify 2 (ev2): selects erase-verify mode tran sition or clearing (target address range : h'40000 to h'47fff). do not set the esu2, psu2, pv2, e2, p2 bits at the same time. bit 3 ev2 description 0 erase-verify mode cleared (initial value) 1 transition to erase-verify mode [setting condition] setting is available when fwe = 1 and swe2 = 1 are selected bit 2 ? program-verify 2 (pv2): selects program-verify mode transition or clearing (target address range: h'40000 to h'47fff). do not set the esu2, psu2, ev2, e2, and p2 bits at the same time. bit 2 pv2 description 0 program-verify mode cleared 1 transition to program-verify mode [setting condition] setting is available when fwe = 1 and swe2 = 1 are selected section 7 rom rev.2.00 jan. 15, 2007 page 141 of 1174 rej09b0329-0200 bit 1 ? erase 2 (e2): selects erase mode transition or clearing (target address range: h'40000 to h'47fff, do not set the esu2, psu2, ev2, pv2, and p2 bits at the same time. bit 1 e2 description 0 erase mode cleared 1 transition to erase mode [setting condition] setting is available when fwe = 1, swe2 = 1, and esu2 = 1 are selected bit 0 ? program 2 (p2): selects program mode transition or clearing (target address range: h'40000 to h'47fff). do not set the esu2, psu2, ev2, pv2, and e2 bits at the same time. bit 0 p2 description 0 program mode cleared 1 transition to program mode [setting condition] setting is available when fwe = 1, swe2 = 1, and psu2 = 1 are selected 7.3.3 erase block register 1 (ebr1) 7 eb7 0 r/w 6 eb6 0 r/w 5 eb5 0 r/w 4 eb4 0 r/w 3 eb3 0 r/w 0 eb0 0 r/w 2 eb2 0 r/w 1 eb1 0 r/w bit initial value r/w : : ebr1 is an 8-bit register that specify the flash memory erase area block by block. ebr1 is initialized to h'00 by a reset, in standby mode or watch mode, when a low level is input to the fwe pin, and when a high level is input to the fwe pin and the swe1 bit in flmcr1 is not set. when a bit in ebr1 is set to 1, the corresponding block can be erased. other blocks are erase-protected. set only one bit in ebr1 and ebr2. more than one bit cannot be set. if set, all bits are cleared to 0. table 7.3 shows the flash memory block configuration. section 7 rom rev.2.00 jan. 15, 2007 page 142 of 1174 rej09b0329-0200 7.3.4 erase block register 2 (ebr2) 7 eb15 0 r/w 6 eb14 0 r/w 5 eb13 0 r/w 4 eb12 0 r/w 3 eb11 0 r/w 0 eb8 0 r/w 2 eb10 0 r/w 1 eb9 0 r/w bit initial value r/w : : : ebr2 is an 8-bit register that specify the flash memory eras e area block by block; ebr2 is initialized to h'00 by a reset, in standby mode or watch mode, and when a low level is input to the fwe pin. bits 3 to 0 are initialized to 0 when a high level is i nput to the fwe pin and the swe1 in flmcr1 is not set. bits7 to 4 are initialized to 0 when the swe2 in flmcr2 is not set. when a bit in ebr2 is set to 1, the corresponding block can be erased. other blocks are erase-protected. set only one bit in ebr1 and ebr2. more than one bit cannot be set. if set, all bits are cleared to 0. the flash memory block configuration is shown in table 7.3. table 7.3 flash memory erase blocks block (size) address eb0 (4 kbytes) h'000000 to h'000fff eb1 (4 kbytes) h'001000 to h'001fff eb2 (4 kbytes) h'002000 to h'002fff eb3 (4 kbytes) h'003000 to h'003fff eb4 (4 kbytes) h'004000 to h'004fff eb5 (4 kbytes) h'005000 to h'005fff eb6 (4 kbytes) h'006000 to h'006fff eb7 (4 kbytes) h'007000 to h'007fff eb8 (32 kbytes) h'008000 to h'00ffff eb9 (64 kbytes) h'010000 to h'01ffff eb10 (64 kbytes) h'020000 to h'02ffff eb11 (64 kbytes) h'030000 to h'03ffff eb12 (1 kbyte) h'040000 to h'0403ff eb13 (1 kbyte) h'040400 to h'0407ff eb14 (2 kbytes) h'040800 to h'040fff eb15 (28 kbytes) h'041000 to h'047fff section 7 rom rev.2.00 jan. 15, 2007 page 143 of 1174 rej09b0329-0200 7.3.5 serial/timer control register (stcr) 7 ? 0 ? 6 iicx1 0 r/w 5 iicx0 0 r/w 4 ? 0 ? 3 flshe 0 r/w 0 ? 0 ? 2 osrome 0 r/w 1 ? 0 ? bit initial value r/w : : : stcr is an 8-bit read/write register that controls the i 2 c bus interface operating mode, on-chip flash memory (in f-ztat versions ), and osd rom. for details on iic bus interface, refer to section 23, i 2 c bus interface (iic). if a module controlled by stcr is not used, do not write 1 to the corresponding bit. stcr is initialized to h'00 by a reset. bits 6 and 5 ? i 2 c control (iicx1, iicx0): these bits control the operation of the i 2 c bus interface. for details, see section 23, i 2 c bus interface (iic). bit 3 ? flash memory control register enable (flshe): setting the flshe bit to 1 enables read/write access to the flash me mory control registers. if flsh e is cleared to 0, the flash memory control registers are desel ected. in this case, the flash me mory control register contents are retained. bit 3 flshe description 0 flash memory control registers deselected (initial value) 1 flash memory control registers selected bit 2 ? osd rom enable (osrome): controls the osd character data rom (osdrom) access. when this bit is set to 1, the osdrom can be accessed by th e cpu, and when this bit is cleared to 0, the osdrom cannot be accessed by the cpu but accessed by the osd module. before writing to or erasing the osdrom in the f-ztat version, be sure to set this bit to 1. note: during osd display, the osdrom cannot be accessed by the cpu. before accessing the osdrom by the cpu, be sure to clear the osdon bit in the screen control register to 0 then set the osrome bit to 1. if the osrome bit is set to 1 during osd display, the character data rom cannot be accessed correctly by cpu. bit 2 osrome description 0 osd rom is accessed by the osd (initial value) 1 osd rom is accessed by the cpu section 7 rom rev.2.00 jan. 15, 2007 page 144 of 1174 rej09b0329-0200 bits 7, 4, 1 and 0 ? reserved: always read as 0. do not write 1 to these bits. 7.4 on-board programming modes when pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. there are two on-board programming modes: boot mode and user program mode. the pin settings for transition to each of these modes are shown in table 7.4. for a diagram of the transitions to the various flash memory modes, see figure 7.3. table 7.4 setting on-board programming modes mode pin mode name fwe md0 p12 p13 p14 boot mode 1 0 1 * 2 1 * 2 1 * 2 user program mode 1 * 1 1 ? ? ? notes: 1. in user program mode, the fwe pin should not be constantly set to 1. set fwe to 1 to make a transition to user program mode before performing a program/erase/verify operation. 2. can be used as i/o ports after boot mode is initiated. section 7 rom rev.2.00 jan. 15, 2007 page 145 of 1174 rej09b0329-0200 7.4.1 boot mode when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. the channel 1 sci to be used is set to asynchronous mode. when a reset-start is executed after the lsi?s pins have been set to boot mode, the boot program built into the lsi is started and the programming control program prepared in the host is serially transmitted to the lsi via the sci. in the lsi, the programming control program received via the sci is written into the programming control program area in on-chip ram. after the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). the transferred programming control program must therefore include coding that follows the programming algorithm given later. figure 7.7 shows the system configuration in boot mode. figure 7.8 shows the boot program mode execution procedure. si1 so1 sci1 this lsi flash memory write data reception verify data transmission host on-chip ram figure 7.7 system configuration in boot mode section 7 rom rev.2.00 jan. 15, 2007 page 146 of 1174 rej09b0329-0200 note: if a memory cell does not operate normally and cannot be erased, one h'ff byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. start set pins to boot mode and execute reset-start host transfers data (h'00) continuously at prescribed bit rate the lsi measures low period of h'00 data transmitted by host the lsi calculates bit rate and sets value in bit rate register after bit rate adjustment, the lsi transmits one h'00 data byte to host to indicate end of adjustment host confirms normal reception of bit rate adjustment end indication (h'00), and transmits one h'55 data byte after receiving h'55, lsi transmits one h'aa data byte to host host transmits number of programming control program bytes (n), upper byte followed by lower byte the lsi transmits received number of bytes to host as verify data (echo-back) n = 1 host transmits programming control program sequentially in byte units the lsi transmits received programming control program to host as verify data (echo-back) transfer received programming control program to on-chip ram n = n? no yes end of transmission check flash memory data, and if data has already been written, erase all blocks after confirming that all flash memory data has been erased, the lsi transmits one h'aa data byte to host execute programming control program transferred to on-chip ram n + 1 n figure 7.8 boot mode execution procedure section 7 rom rev.2.00 jan. 15, 2007 page 147 of 1174 rej09b0329-0200 automatic sci bit rate adjustment start bit stop bit d0 d1 d2 d3 d4 d5 d6 d7 low period (9 bits) measured (h'00 data) high period (1 or more bits) figure 7.9 automatic sci bit rate adjustment when boot mode is initiated, the lsi measur es the low period of the asynchronous sci communication data (h'00) transmitted continuo usly from the host. the sci transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. the lsi calculates the bit rate of the transmission from the host from the measured low period, and transmits one h'00 byte to the host to indicate the end of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit one h'55 byte to the lsi. if reception cannot be performed normally, initiate boot mode ag ain (reset), and repeat the above operations. depending on the host's transmission bit rate and the lsi system clock frequency, there will be a discrepancy between the bit rates of the host and the lsi. to ensure correct sci operation, the host's transfer bit rate should be set to (4800, 9600, 19200) bps. table 7.5 shows typical host transfer bit rates and system clock frequencies for which automatic adjustment of the lsi?s bit rate is possible. the boot program should be executed within this system clock range. table 7.5 system clock frequencies for which automatic adjustment of this lsi bit rate is possible host bit rate (bps) system clock frequency 4800 8 mhz to 10 mhz 9600 8 mhz to 10 mhz 19200 8 mhz to 10 mhz section 7 rom rev.2.00 jan. 15, 2007 page 148 of 1174 rej09b0329-0200 on-chip ram area divisions in boot mode: in boot mode, the 2048-byte area from h'ffdfb0 to h'ffe7af is reserved for use by the boot program, as shown in figure 7.10. the area to which the programming control program is transferred is h'ffe7b0 to h'ffffaf (6144 bytes). the boot program area can be used when the programming control program transferred into ram enters the execution state. a stack area should be set up as required. h'ffdfb0 h'ffe7af programming control program area (6144 bytes) h'ffffaf boot program area * (2048 bytes) note: * the boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to ram. note that the boot program reamins stored in this area after a branch is made to the programming control program. figure 7.10 ram areas in boot mode section 7 rom rev.2.00 jan. 15, 2007 page 149 of 1174 rej09b0329-0200 notes on use of boot mode: 1. when the lsi comes out of reset in boot mode, it measures the low period of the input at the sci's si1 pin. the reset should end with si1 pin high. after the reset ends, it takes about 100 states for the lsi to get ready to measure the low period of the si1 pin input. 2. in boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. 3. interrupts cannot be used while the flash memory is being programmed or erased. 4. the si1 and so1 pins should be pulled up on the board. 5. before branching to the programming control program (h'ffe7b0 in ram area), the lsi terminates transmit and receive operations by th e on-chip sci (channel 1) (by clearing the re and te bits in scr to 0), but the adjusted bit rate value remains set in brr. the transmit data output pin, so1, goes to the high-level output state (p21pcr = 1, p21pdr = 1). the contents of the cpu's internal general re gisters are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. in particular, since the stack pointer (sp) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. the initial values of other on-chip registers are not changed. 6. boot mode can be entered by making the pin settings shown in table 7.4 and executing a reset- start. when the lsi detects the boot mode setting at reset release*, it retains that state internally. boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the fwe pin and mode pins, and executing reset release*. boot mode can also be cleared by a wdt overflow reset. if the mode pin input levels are changed in boot mode, the boot mode state will be maintained in the microcomputer, and boot mode continued, unless a reset occurs. however, the fwe pin must not be driven low while the boot program is running or flash memory is being programmed or erased. note: * mode pin and fwe pin input must satisfy the mode programming setup time (t mds = 4 states) with respect to the reset release timing. section 7 rom rev.2.00 jan. 15, 2007 page 150 of 1174 rej09b0329-0200 7.4.2 user program mode when set to user program mode, the lsi can progr am and erase its flash memory by executing a user program/erase control program. therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of fwe control and supply of programming data, and storing a program/erase control program in part of the program area as necessary. in this mode, the lsi starts up in mode 1 and applies a high level to the fwe pin. the flash memory itself cannot be read while the swe1 bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip ram or external memory. figure 7.11 shows the procedure for executin g the program/erase control program when transferred to on-chip ram. clear fwe fwe = high branch to flash memory application program branch to program/erase control program in ram area execute program/erase control program (flash memory rewriting) transfer program/erase control program to ram md0 = 1 reset start write the fwe assessment program and transfer program (and the program/erase control program if necessary) beforehand note: do not apply a constant high level to the fwe pin. apply a high level to the fwe pin only when the flash memory is programmed or erased. also, while a high level is applied to the fwe pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. figure 7.11 user program mode execution procedure section 7 rom rev.2.00 jan. 15, 2007 page 151 of 1174 rej09b0329-0200 7.5 programming/erasing flash memory in the on-board programming modes, flash memory programming and erasing is performed by software, using the cpu. there are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-veri fy mode. with addre sses h'00000 to h'3ffff, transitions to these modes can be made by setting the psu1, esu1, p1, e1, pv1 and ev1 bits in flmcr1. with addresses h'40000 to h'47fff, trans itions to these modes can be made by setting the psu2, esu2, p2, e2, pv2, a nd ev2 bits in the flmcr2. the flash memory cannot be read while being prog rammed or erased. therefore, the program that controls flash memory programming/erasing (the programming control program) should be located and executed in on-chip ram or external memory. notes: 1. operation is not guaranteed if setting/resetting of the swe1, esu1, psu1, ev1, pv1, e1, and p1 bits in flmcr1 , and the swe2, esu2, psu2, ev2, pv2, e2, and p2 in flmcr2, is executed by a program in flash memory. 2. when programming or erasing, set fwe to 1 (programming/erasing will not be executed if fwe = 0). 3. perform programming in the erased state. do not perform additional programming on previously programmed addresses. 4. do not write to addresses h'00000 to h'3ffff and h'40000 to h'47fff at the same time. otherwise operation cannot be guaranteed. 5. do not operate the osd when writing or erasing addresses h'40000 to h'47fff. do not set the osrome in stcr to 1 before manipulating the flash control register. 7.5.1 program mode (n = 1 when the target address range is h'00000 to h'3ffff and n = 2 when the target address range is h'40000 to h'47fff) follow the procedure shown in the program/program-verify flowchart in figure 7.12 to write data or programs to flash memory. performing prog ram operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. programming should be carri ed out 128 bytes at a time. following the elapse of 1.0 s or more after the swen bit is set to 1 in flash memory control register n (flmcrn), 128-byte program data is stored in the program data area and reprogram data area, and the 128-byte data in the reprogram data area written consecutively to the write addresses. the lower 8 bits of the start address written to must be h'00, or h'80. one hundred and twenty-eight consecutive byte data transfers are performed. the program address and program data are latched in the flash memory. a 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, h'ff data must be written to the extra addresses. next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. section 7 rom rev.2.00 jan. 15, 2007 page 152 of 1174 rej09b0329-0200 set 6.6 ms as the wdt overflow period. after this, preparation for program mode (program setup) is carried out by setting the psun bit in flmcrn, and after the elapse of 50 s or more, the operating mode is switched to program mode by setting the pn bit in flmcrn. the time during which the pn bit is set is the flash memory programming time. make a program setting for one programming operation using the table in the programming flowchart. 7.5.2 program-verify mode (n = 1 when the target address range is h'00000 to h'3ffff and n = 2 when the target address range is h'40000 to h'47fff) in program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. after the elapse of a given programming time, the programming mode is exited (the pn bit in flmcrn is cleared, th en the psun bit is cleared at least 5 s later). the watchdog timer is cleared after the elapse of 5 s or more, and the operating mode is switched to program-verify mode by setting the pvn bit in flmcrn. before reading in program-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of 4 s or more. when the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. wait at least 2 s after the dummy write before performing this read operation. next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 7.12) a nd transferred to the reprogram data area. after 128 bytes of data have been verified, exit program-verify mode, wait for at least 2 s, then clear the swen bit in flmcrn. if reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. however, ensure that the program/program-verify sequence is not repeated more than 1,000 times on the same bits. section 7 rom rev.2.00 jan. 15, 2007 page 153 of 1174 rej09b0329-0200 programming pulse apply subroutine write pulse application subroutine start start of programming set swe1 (2) bit in flmcr(2) set pv1(2) bit in flmcr1(2) clear pv1(2) bit in flmcr1(2) clear swe1(2) bit in flmcr1(2) write pulse additional program pulse 10 s call subroutine store 128-byte program data in program data area and reprogram data area write 128-byte program data in ram reprogram data area consecutevely to flash memory write 128-byte program data in ram additional data area consecutively to flash memory tsswe: wait 1 s tspv: wait 4 s tspvr: wait 2 s tcpv: wait 2 s tcswe: wait 100 s end of programming programming pulse 30 s or 200 s h'ff dummy write to verify address read verify data calculate additional program data calculate reprogram data complete 128-byte data verification? transfer additional program data to additional program data area transfer reprogram data to reprogram data area program data = verify data? refer to note * 6 for the pulse width * 1 * 2 * 5 * 4 * 3 * 4 * 1 ng ng ng ng ng ok ok ok ok ok 6 n? n n + 1 6 n ? m = 0? clear swe1 (2) bit in flmcr1(2) tcwe: wait 100 s programming failure ng ok n 1000? m = 1 * 4 call subroutine n = 1 m = 0 enable wdt set psu1 (2) bit in flmcr1 (2) set p1 (2) bit in flmcr1 (2) clear p1(2) bit in flmcr1 (2) clear psu1(2) bit in flmcr1 (2) tspsu: wait 50 s tcp: wait 5 s tcpsu: wait 5 s disable wdt end of subroutine note: 6. programming pulse width number of times of programming programming time (z) s the programming pulse must be 10 s in additional programming perform programming after erasing data. do not perform additional programming to addresses that have already been written to. notes: 1. data transfer is performed by byte transfer. the lower eight bits of the start address must be h'00 or h'80. a 128-by te data transfer must be performed even if writing fewer than 128 bytes: in this case, h'ff must be written to the extra addresses. 2. verify data is read in 16-bit (word) units. 3. even in case of the bit which is already-programmed in the 128-byte programming loop, perform additional programming if the bit fails at the next verify. 4. an area for storing program data (128 bytes), reprogram data (128 bytes), and additional program (128bytes) must be provide d in ram. the contents of the reprogram and additional program areas are rewritten as programming processes. 5. a 30 s or 200 s programming pulse must be applied. for details on programming pulse, refer to note 6. to perform additional data programming, apply a programming pulse of 10 s. reprogram data x' is the reprogram data after pro gram pulse is applied. program data storage are (128 bytes) reprogram data storage area (128 bytes) additional program data storage area (128 bytes) reprogram data calculation table additiona l program data calculation table increment address tsp10 or tsp30 or tsp200: wait 10 s or 30 s or 200 s 1 2 3 4 5 6 7 8 9 10 11 12 13 998 999 1000 30 30 30 30 30 30 200 200 200 200 200 200 200 200 200 200 ram source data (d) 0 0 1 1 reprogram data (x) 1 0 1 1 additional program data (y) 0 1 1 1 reprogram data (x') 0 0 1 1 comments verify data (v) 0 1 0 1 verify data (v) 0 1 0 1 programming completed programming incomplete; reprogram still in erased state; no action comments additional programming performed additional programming not performed additional programming not performed figure 7.12 program/program-verify flowchart section 7 rom rev.2.00 jan. 15, 2007 page 154 of 1174 rej09b0329-0200 7.5.3 erase mode (n = 1 when the target address range is h'00000 to h'3ffff and n = 2 when the target address range is h'40000 to h'47fff) flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single- block erase) shown in figure 7.13. to perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in erase block register 1 or 2 (ebr1 or ebr2) at least 1 s after setting the swen bit to 1 in flash memory control register n (flmcrn). next, the watchdog timer is set to prevent overerasing in the event of program runaway, etc. set more than 19.8 ms as the wdt overflow period . after this, preparation for erase mode (erase setup) is carried out by setting the esun bit in flmcrn, and after a elapse of 100 s or more, the operating mode is switched to erase mode by setting the en bit in flmcrn. the time during which the en bit is set is the flash memory eras e time. ensure that erase time does not exceed 10 ms. note: with flash memory erasing, preprogramming (setting all data in the memory to be erased to 0) is not necessary before starting the erase procedure. section 7 rom rev.2.00 jan. 15, 2007 page 155 of 1174 rej09b0329-0200 end of erasing start set swe1 (2) bit in flmcr1 (2) set esu1 (2) bit in flmcr1 (2) set e1 (2) bit in flmcr1 (2) tsswe: wait 1 s tsesu: wait 100 s n = 1 set ebr1 (2) enable wdt * 3 tse: wait 10 ms tce: wait 10 s tcesu: wait 10 s tsev: wait 20 s set block start address to verify address tsevr: wait 2 s tcev: wait 4 s * 2 * 4 * 5 clear e1 (2) bit in flmcr1 (2) clear esu1 (2) bit in flmcr1 (2) set ev1 (2) bit in flmcr1 (2) h'ff dummy write to verify address read verify data clear ev1 (2) bit in flmcr1 (2) tcev: wait 4 s clear ev1 (2) bit in flmcr1 (2) clear swe1 (2) bit in flmcr1 (2) disable wdt * 1 verify data = all 1? tcswe: wait 100 s tcswe: wait 100 s end of erasing of all erase blocks? erase failure clear swe1 (2) bit in flmcr1 (2) n (n)? no no no no yes yes yes yes notes: 1. 2. 3. 4. 5. increment address n n + 1 last address of block? preprogramming (setting erase block data to all 0) is not necessary. verify data is read in 16-bit (word) units. set only one bit in ebr. more than two bit cannot be set. erasing is performed in block units. to erase a number of blocks, the individual blocks must be erased sequentially. for the value of n, see table 31.32, flash memory characteristics. figure 7.13 erase/erase-verify flowchart section 7 rom rev.2.00 jan. 15, 2007 page 156 of 1174 rej09b0329-0200 7.5.4 erase-verify mode (n = 1 when the target address range is h'00000 to h'3ffff and n = 2 when the target address range is h'40000 to h'47fff) in erase-verify mode, data is read after memory has been erased to ch eck whether it has been correctly erased. after the elapse of the erase time, erase mode is exited (the en b it in flmcrn is cleared, then the esun bit is cleared at least 10 s later), the watchdog timer is cleared after the elapse of 10 s or more, and the operating mode is switched to erase-verify mode by setting the evn bit in flmcrn. before reading in erase-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of 6.0 s or more. when the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. wait at least 2 s after the dummy write before performing this read operation. if the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. if the read data has not been erased, set erase mode again, and repeat the erase/erase-verify sequence in the sa me way. however, ensure that the erase/erase- verify sequence is not repeated more than 100 times. when verification is completed, exit erase- verify mode, and wait for at least 4 s. if erasure has been completed on all the erase blocks, clear the swen bit in flmcrn. if th ere are any unerased blocks, make a 1 bit setting for the flash memory area to be erased, and repeat the er ase/erase-verify sequence in the same way. section 7 rom rev.2.00 jan. 15, 2007 page 157 of 1174 rej09b0329-0200 7.6 flash memory protection there are three kinds of flash memory program/er ase protection: hardware protection, software protection, and error protection. 7.6.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. hardware protection is reset by settings in flash memory control registers 1 and 2 (flmcr1, flmcr2) and erase block registers 1 and 2 (ebr1, ebr2). (see table 7.6.) in error protected state, the flmcr1, flmcr2 , ebr1, and ebr2 settings are maintained. table 7.6 hardware protection functions item description program erase fwe pin protection ? when a low level is input to the fwe pin, flmcr1, flmcr2 (excluding the fler bit), ebr1, and ebr2 are initialized, and the program/erase-protected state is entered yes yes reset/standby protection ? in a reset (including a wdt overflow reset) and in standby mode or watch mode, flmcr1, flmcr2, ebr1, and ebr2 are initialized, and the program/erase-protected state is entered ? in a reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stabilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristics yes yes section 7 rom rev.2.00 jan. 15, 2007 page 158 of 1174 rej09b0329-0200 7.6.2 software protection software protection can be implemented by setting the swe1 bit in flmcr1 and swe2 bit in flmcr2 and erase block registers 1 and 2 (ebr1, ebr2). when software protection is in effect, setting the p1 or e1 bit in flash memory control register 1 (flmcr1) or p2 or e2 bit in flash memory control register 2 (flmcr2) does not cause a transition to program mode or erase mode. (see table 7.7.) table 7.7 software protection functions item description program erase swe bit protection ? clearing the swe bit to 0 in flmcr1 sets the program/erase-protected state for all blocks (execute in on-chip ram or external memory) yes yes block specification protection ? erase protection can be set for individual blocks by settings in erase block registers 1 and 2 (ebr1, ebr2) ? setting ebr1 and ebr2 to h'00 places all blocks in the erase-protected state ? yes 7.6.3 error protection in error protection, an error is detected when mcu runaway occurs during flash memory programming/erasing, or operati on is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. if the mcu malfunctions during flash memory programming/erasing, the fler bit is set to 1 in flmcr2 and the error protection state is entered. the flmcr1, flmcr2, ebr1, and ebr2 settings are retained, but program mode or erase mode is ab orted at the point at which the error occurred. program mode or erase mode cannot be re-entered by re-setting the p or e bit. however, pv1, pv2, ev1 and ev2 bit setting is enabled, and a transition can be made to verify mode. fler bit setting conditions are as follows: ? when flash memory is read during programming/erasing (including a vector read or instruction fetch) ? immediately after exception handling (excluding a reset) during programming/erasing ? when a sleep instruction (including stand by) is executed during programming/erasing section 7 rom rev.2.00 jan. 15, 2007 page 159 of 1174 rej09b0329-0200 error protection is released only by a reset and in hardware standby mode. figure 7.14 shows the flash memory state transition diagram. : memory read possible : verify-read possible : programming possible : erasing possible rd vf pr er legend: : memory read impossible : verify-read impossible : programming impossible : erasing impossible r d vf p r e r r d vf pr er fler = 0 error occurrence error occurre nce (sleep instru ction) r e s = 0 r e s = 0 r e s = 0 r d vf p r e r fler = 0 program mode erase mode reset (hardware protection) rd vf p r e r fler = 1 r d vf p r e r fler = 1 error protection mode error protection mode (power-down mode) power-down mode flmcr1, flmcr2 (except fler bit), ebr1, ebr2 initialization state flmcr1, flmcr2, ebr1, ebr2 initialization state power-down mode release figure 7.14 flash memory state transitions 7.7 interrupt handling when progr amming/erasing flash memory all interrupts are disabled when flash memory is being programmed or erased (when the p1 or e1 bit is set in flmcr1, or the p2 or e2 bit is set in flmr2), and while the boot program is executing in boot mode * 1 , to give priority to the program or erase operation. there are three reasons for this: ? interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. ? in the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly * 2 , possibly resulting in mcu runaway. ? if interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. section 7 rom rev.2.00 jan. 15, 2007 page 160 of 1174 rej09b0329-0200 for these reasons, in on-board programming mode alone there are conditions for disabling interrupt, as an exception to the general rule. however, this provision does not guarantee normal erasing and programming or mcu operation. all re quests must therefore be disabled inside and outside the mcu during fwe application. interrupt is also disabled in the error-protection state while the p1 or e1 bit remains set in flmcr1, or the p2 or e2 bit remains set in flmcr2. notes: 1. interrupt requests must be disabled inside and outside the mcu until data write by the write control program is complete. 2. the vector may not be read correctly in this case for the following two reasons: ? if flash memory is read while being programmed or erased (while the p or e bit is set in flmcr1 or flmcr2), correct read data will not be obtained (undetermined values will be returned). ? if the interrupt entry in the interrupt vector table has not been programmed yet, interrupt exception handling will not be executed correctly. 7.8 flash memory programmer mode 7.8.1 programmer mode setting programs and data can be written and erased in programmer mode as well as in the on-board programming modes. in programmer mode, flash memory read mode, auto-program mode, auto- erase mode, and status read mode are supported with these device types. in auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. 7.8.2 socket adapt ers and memory map in programmer mode, a socket adapter is mounte d on the prom programmer. the socket adapter product codes are listed in table 7.8. figure 7.15 shows the memory map in programmer mode. table 7.8 socket adapter product codes part no. package socket adapter product code hd64f2199r 112-pin qfp me2199eshf1h (minato electronics) section 7 rom rev.2.00 jan. 15, 2007 page 161 of 1174 rej09b0329-0200 h8s/2199r h'000000 mcu mode programmer mode h'047fff h'00000 h'47fff on-chip rom area figure 7.15 memory map in programmer mode 7.8.3 programmer mode operation table 7.9 shows how the different operating mo des are set when using programmer mode, and table 7.10 lists the commands used in programmer mode. details of each mode are given below. ? memory read mode: memory read mode supports byte reads. ? auto-program mode: auto-program mode supports programming of 128 bytes at a time. status polling is used to confirm the end of auto-programming. ? auto-erase mode: auto-erase mode supports automatic erasing of the entire flash memory. status polling is used to confirm the end of auto-erasing. ? status read mode: status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the io6 signal. in status read mode, error information is output if an error occurs. table 7.9 settings for each opera ting mode in programmer mode pin names mode fwe ce oe we io0 to io7 a0 to a18 read h or l l l h data output ain output disable h or l l h h hi-z x command write h or l * 3 l h l data input ain * 2 chip disable * 1 h or l h x x hi-z x notes: 1. chip disable is not a standby state; internally, it is an operation state. 2. ain indicates that there is also address input in auto-program mode. 3. for command writes when making a transition to auto-program or auto-erase mode, input a high level to the fwe pin. section 7 rom rev.2.00 jan. 15, 2007 page 162 of 1174 rej09b0329-0200 table 7.10 programmer mode commands 1st cycle 2nd cycle command name number of cycles mode address data mode address data memory read mode 1 + n write x h'00 read ra dout auto-program mode 129 write x h'40 write wa din auto-erase mode 2 write x h'20 write x h'20 status read mode 2 write x h'71 write x h'71 notes: 1. in auto-program mode. 129 cycles are r equired for command writing by a simultaneous 128-byte write. 2. in memory read mode, the number of cycles depends on the number of address write cycles (n). 7.8.4 memory read mode ? after the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. to read memory contents, a trans ition must be made to memory read mode by means of a command write befo re the read is executed. ? command writes can be performed in memory read mode, just as in the command wait state. ? once memory read mode has been entere d, consecutive reads can be performed. ? after power-on, memory read mode is entered. table 7.11 ac characteristics in memory read mode (1) ? preliminary ? conditions: v cc = 5.0 v 10%, v ss = 0 v, ta = 25 c 5 c item symbol min max unit command write cycle t nxtc 20 ? s ce hold time t ceh 0 ? ns ce setup time t ces 0 ? ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns we rise time t r ? 30 ns we fall time t f ? 30 ns section 7 rom rev.2.00 jan. 15, 2007 page 163 of 1174 rej09b0329-0200 ce a18 to a0 io7 to io0 h'00 oe we command write t wep t ceh t dh t ds t f t r t nxtc note: data is latched on the rising edge of we . t ces memory read mode address stable data figure 7.16 memory read mode timing waveforms after command write table 7.12 ac characteristics when entering another mode from memory read mode ? preliminary ? conditions: v cc = 5.0 v 10%, v ss = 0 v, ta = 25 c 5 c item symbol min max unit command write cycle t nxtc 20 ? s ce hold time t ceh 0 ? ns ce setup time t ces 0 ? ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns we rise time t r ? 30 ns we fall time t f ? 30 ns section 7 rom rev.2.00 jan. 15, 2007 page 164 of 1174 rej09b0329-0200 ce a18 to a0 io7 to io0 h'xx oe we other mode command write t wep t ceh t dh t ds t nxtc note: do not enable we and oe at the same time. t ces address stable data t f t r figure 7.17 timing waveforms when entering another mode from memory read mode table 7.13 ac characteristics in memory read mode (2) ? preliminary ? conditions: v cc = 5.0 v 10%, v ss = 0 v, ta = 25 c 5 c item symbol min max unit access time t acc ? 20 s ce output delay time t ce ? 150 ns oe output delay time t oe ? 150 ns output disable delay time t df ? 100 ns data output hold time t oh 5 ? ns ce a18 to a0 io7 to io0 vil vil vih oe we t acc t oh t oh t acc address stable address stable data data figure 7.18 timing waveforms for ce / oe enable state read section 7 rom rev.2.00 jan. 15, 2007 page 165 of 1174 rej09b0329-0200 ce a18 to a0 io7 to io0 vih oe we t ce t acc t oe t oh t oh t df t ce t acc t oe address stable address stable data data t df figure 7.19 timing waveforms for ce / oe clocked read 7.8.5 auto-program mode ac characteristics table 7.14 ac characteristics in auto-program ? preliminary ? conditions: v cc = 5.0 v 10%, v ss = 0 v, ta = 25 c 5 c item symbol min max unit command write cycle t nxtc 20 ? s ce hold time t ceh 0 ? ns ce setup time t ces 0 ? ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns status polling start time t wsts 1 ? ms status polling access time t spa ? 150 ns address setup time t as 0 ? ns address hold time t ah 60 ? ns memory write time t write 1 3000 ms we rise time t r ? 30 ns we fall time t f ? 30 ns write setup time t pns 100 ? ns write end setup time t pnh 100 ? ns section 7 rom rev.2.00 jan. 15, 2007 page 166 of 1174 rej09b0329-0200 ce fwe a18 to a0 io7 oe we t nxtc t wsts t spa t nxtc t ces t ds t dh t wep t as t pnh t pns t ah t ceh address stable data transfer 1 byte to 128 bytes io6 programming wait data io5 to io0 h'40 data h'00 t f t r t write (1 to 3,000 ms) programming operation end identification signal programming normal end identification signal figure 7.20 auto-program mode timing waveforms notes on use of auto-program mode ? in auto-program mode, 128 bytes are programmed simultaneously. this should be carried out by executing 128 consecutive byte transfers. ? a 128-byte data transfer is necessary even when programming fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. ? the lower 8 bits of the transfer address must be h'00 or h'80. if a value other than an effective address is input, processing will switch to a memo ry write operation but a write error will be flagged. ? memory address transfer is performed in the second cycle (figure 7.20). do not perform transfer after the second cycle. ? do not perform a command write during a programming operation. ? perform one auto-programming operation for a 128-byte block for each address. characteristics are not guaranteed for two or more programming operations. ? confirm normal end of auto-programming by checking io6. alternatively, status read mode can also be used for this purpose (io7 status polling uses the auto-program operation end identification pin). ? the status polling io6 and io7 pin information is retained until the next command write. until the next command write is performed, reading is possible by enabling ce and oe . section 7 rom rev.2.00 jan. 15, 2007 page 167 of 1174 rej09b0329-0200 7.8.6 auto-erase mode ac characteristics table 7.15 ac characteristics in auto-erase mode ? preliminary ? conditions: v cc = 5.0 v 10%, v ss = 0 v, ta = 25 c 5 c item symbol min max unit command write cycle t nxtc 20 ? s ce hold time t ceh 0 ? ns ce setup time t ces 0 ? ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns status polling start time t ests 1 ? ms status polling access time t spa ? 150 ns memory erase time t erase 100 40000 ms we rise time t r ? 30 ns we fall time t f ? 30 ns erase setup time t ens 100 ? ns erase end setup time t enh 100 ? ns ce fwe a18 to a0 io5 to io0 io6 io7 oe we t erase (100 to 40000ms) t ests t spa t nxtc t nxtc t ces t ceh t dh cl in dl in t ds t wep t ens h'00 h'20 h'20 t enh erase end identification signal erase normal end identification signal t f t r figure 7.21 auto-erase mode timing waveforms section 7 rom rev.2.00 jan. 15, 2007 page 168 of 1174 rej09b0329-0200 notes on use of erase-program mode ? auto-erase mode supports only entire memory erasing. ? do not perform a command write during auto-erasing. ? confirm normal end of auto-erasing by checking io6. alternatively, status read mode can also be used for this purpose (io7 status polling uses the auto-erase operation end identification pin). ? the status polling io6 and io7 pin information is retained until the next command write. until the next command write is performed, reading is possible by enabling ce and oe . 7.8.7 status read mode status read mode is used to identify what type of abnormal end has occurred. use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. the return code is retained until a command write for other than status read mode is performed. table 7.16 ac characteristics in status read mode ? preliminary ? conditions: v cc = 5.0 v 10%, v ss = 0 v, ta = 25 c 5 c item symbol min max unit command write cycle t nxtc 20 ? s ce hold time t ceh 0 ? ns ce setup time t ces 0 ? ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns oe output delay time t oe ? 150 ns disable delay time t df ? 100 ns ce output delay time t ce ? 150 ns we rise time t r ? 30 ns we fall time t f ? 30 ns section 7 rom rev.2.00 jan. 15, 2007 page 169 of 1174 rej09b0329-0200 ce a18 to a0 io7 to io0 oe we t ces t nxtc t nxtc t df note: io2 and io3 are undefined. t ces t dh t ceh t ds t wep t wep data t dh t ceh t ds t oe t ce t nxtc h'71 h'71 t f t r t f t r figure 7.22 status read mode timing waveforms table 7.17 status read mode return commands pin name io7 io6 io5 io4 io3 io2 io1 io0 attribute normal end identification command error programming error erase error ? ? programming or erase count exceeded effective address error initial value 0 0 0 0 0 0 0 0 indications normal end: 0 abnormal end: 1 command error: 1 otherwise: 0 programming error: 1 otherwise: 0 erase error: 1 otherwise: 0 ? ? count exceeded: 1 otherwise: 0 effective address error: 1 otherwise: 0 note: io2 and io3 are undefined. section 7 rom rev.2.00 jan. 15, 2007 page 170 of 1174 rej09b0329-0200 7.8.8 status polling the io7 status polling flag indicates the operating status in auto-program or auto-erase mode. the io6 status polling flag indicates a normal or abnormal end in auto-program or auto-erase mode. table 7.18 status polling output truth table pin names internal operation in progress abnormal end ? normal end io7 0 1 0 1 io6 0 0 1 1 io0 to io5 0 0 0 0 7.8.9 programmer mode transition time commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. after the programmer mode setup time, a transition is made to memory read mode. table 7.19 command wait state transition time specifications item symbol min max unit standby release (oscillation stabilization time) t osc1 10 ? ms programmer mode setup time t bmv 10 ? ms v cc hold time t dwn 0 ? ms v cc res fwe memory read mode command wait state command wait state normal/abnormal end identifica- tion auto-program mode auto-erase mode t osc1 t bmv t dwn note: except in auto-program mode and auto-erase mode, drive the fwe input pin low. don't care don't care figure 7.23 oscillation stabilization time, boot program transfer time, and power supply fall sequence section 7 rom rev.2.00 jan. 15, 2007 page 171 of 1174 rej09b0329-0200 7.8.10 notes on memory programming ? when programming addresses which have previously been programmed, carry out auto- erasing before auto-programming. ? when performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. notes: 1. the flash memory is initially in the erased state when the device is shipped by renesas. for other chips for which the erasure history is unknown, it is recommended that auto- erasing be executed to check and suppl ement the initialization (erase) level. 2. auto-programming should be performe d once only on the same address block. section 7 rom rev.2.00 jan. 15, 2007 page 172 of 1174 rej09b0329-0200 7.9 note on switching from f?zta t version to mask-rom version the mask rom version does not have the internal registers for flash memory control that are provided in the f-ztat version. table 7.20 lists the registers that are present in the f-ztat version but not in the mask rom version. if a register listed in table 7.20 is read in the mask rom version, an undefined value will be returned. therefore, if application software developed on the f-ztat version is switched to a mask rom version product, it must be modified to ensure that the registers in table 7.20 have no effect. table 7.20 registers present in f-ztat version but absent in mask rom version register abbreviation address flash memory control register 1 flmcr1 h'fff8 flash memory control register 2 flmcr2 h'fff9 erase block register 1 ebr1 h'fffa erase block register 2 ebr2 h'fffb section 8 ram rev.2.00 jan. 15, 2007 page 173 of 1174 rej09b0329-0200 section 8 ram 8.1 overview the h8s/2199r, h8s/2198r, h8s/2197r, and h8s/2196r have 4 kbytes, h8s/2197s, and h8s/2196s have 3 kbytes, and h8s/2199r f-ztat version has 8 kbytes of on-chip high-speed static ram. the on-chip ram is connected to the cpu by a 16-bit data bus, enabling both byte data and word data to be accessed in one state. this makes it possible to perform fast word data transfer. 8.1.1 block diagram figure 8.1 shows a block diagram of the on-chip ram. internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'ffefb0 h'ffefb2 h'ffefb4 h'ffffae h'ffefb1 h'ffefb3 h'ffefb5 h'ffffaf figure 8.1 block diagram of ram (h8s/2199r) section 8 ram rev.2.00 jan. 15, 2007 page 174 of 1174 rej09b0329-0200 section 9 clock pulse generator rev.2.00 jan. 15, 2007 page 175 of 1174 rej09b0329-0200 section 9 clock pulse generator 9.1 overview this lsi has a built-in clock pulse generator (cpg) that generates the system clock ( ), the bus master clock, and internal clocks. the clock pulse generator consists of a system clock oscillator, a duty adjustment circuit, clock selection circuit, medium-speed clock divider, subclock oscillator, and subclock division circuit. 9.1.1 block diagram figure 9.1 shows a block diagram of the clock pulse generator. system clock oscillator duty adjustment circuit clock selection circuit medium- speed clock divider subclock oscillator subclock division circuit osc1 osc2 x1 x2 /16, /32, /64 w/2, w/4, w/8 sub or sub timer a count clock internal clock to supportin g modules bus master cloc k to cpu sub ( w/2, w/4, w/8) figure 9.1 block diagram of clock pulse generator 9.1.2 register configuration the clock pulse generator is controlled by sbycr and lpwrcr. table 9.1 shows the register configuration. table 9.1 cpg registers name abbreviation r/w initial value address * standby control register sbycr r/w h'00 h'ffea low-power control register lpwrcr r/w h'00 h'ffeb note: * lower 16 bits of the address. section 9 clock pulse generator rev.2.00 jan. 15, 2007 page 176 of 1174 rej09b0329-0200 9.2 register descriptions 9.2.1 standby control register (sbycr) 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ? 0 ? 0 sck0 0 r/w 2 ? 0 ? 1 sck1 0 r/w bit initial value r/w : : : sbycr is an 8-bit readable/writable register that performs power-down mode control. only bits 0 and 1 are described here. for a description of th e other bits, see section 4.2.1, standby control register (sbycr). sbycr is initialized to h'00 by a reset. bits 1 and 0 ? system clock select 1 and 0 (sck1, sck0): these bits select the bus master clock for high-speed mode and medium-speed mode. bit 1 bit 0 sck1 sck0 description 0 bus master is in high-speed mode (initial value) 0 1 medium-speed clock is /16 1 0 medium-speed clock is /32 1 medium-speed clock is /64 9.2.2 low-power control register (lpwrcr) 7 dton 0 r/w 6 lson 0 r/w 5 nesel 0 r/w 4 ? 0 ? 3 ? 0 ? 0 sa0 0 r/w 2 ? 0 ? 1 sa1 0 r/w bit initial value r/w : : : lpwrcr is an 8-bit readable/writable register that performs power-down mode control. only bit 1 and 0 is described here. for a description of the other bits, see section 4.2.2, low- power control register (lpwrcr). lpwrcr is initialized to h'00 by a reset. section 9 clock pulse generator rev.2.00 jan. 15, 2007 page 177 of 1174 rej09b0329-0200 bits 1 and 0 ? subactive mode clock select (sa1, sa0): select cpu clock for subactive mode. in subactive mode, writes are disabled. bit 1 bit 0 sa1 sa0 description 0 cpu operating clock is w/8 (initial value) 0 1 cpu operating clock is w/4 1 * cpu operating clock is w/2 legend: * don't care 9.3 oscillator clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 9.3.1 connecting a crystal resonator circuit configuration: a crystal resonator can be connected as shown in the example in figure 9.2. an at-cut parallel-resonance crystal should be used. osc1 osc2 c l2 c l1 c l1 = c l2 = 10 to 22pf figure 9.2 connection of crystal resonator (example) crystal resonator: figure 9.3 shows the equivalent circuit of the crystal resonator. use a crystal resonator that has the characteristics shown in ta ble 9.2 and the same frequency as the system clock ( ). osc1 c l at-cut parallel-resonance type osc2 c 0 lr s figure 9.3 crystal resonator equivalent circuit section 9 clock pulse generator rev.2.00 jan. 15, 2007 page 178 of 1174 rej09b0329-0200 table 9.2 crystal resonator parameters frequency (mhz) 8 10 r s max ( ) 80 60 c o max (pf) 7 7 note on board design: when a crystal resonator is connected, the following points should be noted. other signal lines should be routed away from th e oscillator circuit to prevent induction from interfering with correct oscillation. see figure 9.4. when designing the board, place the crystal resonator and its load capacitors as close as possible to the osc1 and osc2 pins. c l2 si g nal a si g nal b c l1 this lsi osc1 osc2 avoid figure 9.4 example of incorrect board design section 9 clock pulse generator rev.2.00 jan. 15, 2007 page 179 of 1174 rej09b0329-0200 9.3.2 external clock input circuit configuration: an external clock signal can be input as shown in the examples in figure 9.5. if the osc2 pin is left open, make sure that stray capacitance is no more than 10 pf. in example (b), make sure that the external clock is held high in standby mode, subactive mode, subsleep mode, and watch mode. osc1 osc2 external clock input open (a) osc2 pin left open osc1 osc2 external clock input (b) inverted-phase clock input at osc2 pin figure 9.5 external clock input (examples) section 9 clock pulse generator rev.2.00 jan. 15, 2007 page 180 of 1174 rej09b0329-0200 external clock: the external clock signal should have the same frequency as the system clock ( ). table 9.3 and figure 9.6 show the input conditions for the external clock. table 9.3 external clock input conditions v cc = 4.0 to 5.5 v item symbol min max unit test conditions external clock input low pulse width t exl 40 ? ns figure 9.6 external clock input high pulse width t exh 40 ? ns external clock rise time t exr ? 10 ns external clock fall time t exf ? 10 ns t exh t exl t exr t exf osc1 figure 9.6 external clock input timing table 9.4 shows the external clock output settling delay time, and figure 9.7 shows the external clock output settling delay timing. the oscillator and duty adjustment circuit have a function for adjusting the waveform of the external clock input at the osc1 pin. when the prescribed clock signal is input at the osc1 pin, internal clock signal output is fixed after the elapse of the external clock output settling delay time (t dext ). as the clock signal output is not fixed during the t dext period, the reset signal should be driven low to maintain the reset state. section 9 clock pulse generator rev.2.00 jan. 15, 2007 page 181 of 1174 rej09b0329-0200 table 9.4 external clock output settling delay time conditions: v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ss = av ss = 0 v item symbol min max unit notes external clock output settling delay time t dext * 500 ? s figure 9.7 note: * t dext includes 20 t cyc of res pulse width (t resw ). t dext * res (internal) osc1 v cc 4.0 v note: * t dext includes 20 t cyc of res pulse width (t resw ). figure 9.7 external clock output settling delay timing section 9 clock pulse generator rev.2.00 jan. 15, 2007 page 182 of 1174 rej09b0329-0200 9.4 duty adjustment circuit when the oscillator frequency is 5 mhz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock ( ). 9.5 medium-speed clock divider the medium-speed divider divides the system clock to generate /16, /32, and /64 clocks. 9.6 bus master clock selection circuit the bus master clock selection ci rcuit selects the system clock ( ) or one of the medium-speed clocks ( /16, /32 or /64) to be supplied to the bus master (cpu), according to the settings of bits sck2 to sck0 in sbycr. 9.7 subclock oscillator circuit 9.7.1 connecting 32.768 khz crystal resonator when using a subclock, connect a 32.768 khz crystal resonator to x1 and x2 pins as shown in figure 9.8. for precautions on connecting, see note on board design, in section 9.3.1 connecting a crystal resonator. x1 x2 c 2 c 1 c 1 = c 2 = 15 pf (typ) figure 9.8 connecting a 32.768 khz crystal resonator (example) section 9 clock pulse generator rev.2.00 jan. 15, 2007 page 183 of 1174 rej09b0329-0200 figure 9.9 shows a crystal resonator equivalent circuit. x1 c s c 0 = 1.5 pf (typ) r s = 14 k (typ) f w = 32.768 khz type: mx38t (nihon denpa kogyo co., ltd.) note: values shown are the reference values. x2 c 0 l s r s figure 9.9 32.768 khz crystal resonator equivalent circuit 9.7.2 when subclock is not needed connect x1 pin to v cl , and x2 pin should remain open as shown in figure 9.10. x1 x2 v cl open figure 9.10 terminal when subclock is not needed 9.8 subclock waveform shaping circuit to eliminate noise in the subclock input from the x1 pin, this circuit samples the clock using a clock obtained by dividing the clock. the sampling frequency is set with the nesel bit in lpwrcr. for details, see section 4.2.2, low-power control register (lpwrcr). the clock is not sampled in subactive mode, subsleep mode, or watch mode. section 9 clock pulse generator rev.2.00 jan. 15, 2007 page 184 of 1174 rej09b0329-0200 9.9 notes on the resonator resonator characteristics are closely related to the user board design. perform appropriate assessment of resonator connection, mask vers ion and f-ztat, by referring to the connection example given in this section. the resonator circuit rate differs depending on the free capacity of the resonator and the execution circuit, so consult with the resonator manufacturer before determination. make sure the voltage applied to the resonator pin does not exceed the maximum rated voltage. section 10 i/o port rev.2.00 jan. 15, 2007 page 185 of 1174 rej09b0329-0200 section 10 i/o port 10.1 overview 10.1.1 port functions this lsi has seven 8-bit i/o ports (including one cmos high-current port), and one 8-bit input port. table 10.1 shows the functions of each port. ea ch i/o part a port contro l register (pcr) that controls an input and output and a port data register (pdr) for storing output data. the input and output can be controlled in a unit of bit. the pin whose peripheral function is used both as an alternative function can set the pin function in a unit of bit by a port mode register (pmr). 10.1.2 port input ? reading a port ? when a general port of pcr = 0 (input) is read, the pin level is read. ? when a general port of pcr = 1 (output) is read, the value of the corresponding pdr bit is read. ? when the pins (excluding an7 to an0 and rpb7 to rp0 pins) set to the peripheral function are read, the results are as given in items (1) and (2) according to the pcr value. ? processing input pins the general input port or general i/o port is gated by read signals. unused pins can be left open if they are not read. however, if an open pin is read, a feedthrough current may apply during the read period according to an intermediate level. the read period is about one-state. relevant ports: p0, p1, p2, p3, p4, p5, p6, p7, and p8 when an alternative pin is set to an alternative function other than the general i/o, always set the pin level to a high or low level. if the pin is left open, a feedthrough current applies according to an intermediate level, which ad versely affects reliability, causes malfunctions, and in the worst case may damage the pin. because the pmr is not initialized in low power consumption mode, pay attention to the pin input level after the mode has been shifted to the low power consumption mode. relevant pins: ic , irq0 to irq5 , sck1, si1, sda1, scl1, sda0*, scl0*, synci*, ftia*, ftib*, ftic*, ftid*, rptrg, tmbi, adtrg , exctl, comp, dpg, excap, and exttrg note: * not available in the h8s/2197s or h8s/2196s. section 10 i/o port rev.2.00 jan. 15, 2007 page 186 of 1174 rej09b0329-0200 table 10.1 port functions port description pins alternative functions function switching register port 0 p07 to p00 input- only ports p07/an7 to p00/an0 analog data input channels 7 to 0 pmr0 p17/tmow prescalar unit frequency division clock output p16/ ic prescalar unit input capture input port 1 p17 to p10 i/o ports (built-in mos pull- up transistors) p15/ irq5 to p10/ irq0 external interrupt request input pmr1 p27/synci formatless serial clock input * p26/scl0 i 2 c bus interface clock i/o * p25/sda0 i 2 c bus interface data i/o * stcr iccr p24/scl1 i 2 c bus interface clock i/o p23/sda1 i 2 c bus interface data i/o p22/sck1 sci1 clock i/o p21/so1 sci1 transmit data output port 2 p27 to p20 i/o ports (built-in mos pull- up transistors) p20/si1 sci1 receive data input smr scr p37/tmo timer j timer output p36/buzz timer j buzzer output p35/pwm3 p34/pwm2 p33/pwm1 p32/pwm0 8-bit pwm3 output * 8-bit pwm2 output * 8-bit pwm1 output 8-bit pwm0 output p31/sv2 servo monitor output port 3 p37 to p30 i/o ports (built-in mos pull- up transistors) p30/sv1 pmr3 port 4 p47 to p40 i/o ports p47/rptrg realtime output port trigger input pmr4 p46/ftob timer x output compare b output * p45/ftoa timer x output compare a output * tocr p44/ftid timer x input capture d input * p43/ftic timer x input capture c input * p42/ftib timer x input capture b input * p41/ftia timer x input capture a input* ? p40/pwm14 14-bit pwm output * pmr4 section 10 i/o port rev.2.00 jan. 15, 2007 page 187 of 1174 rej09b0329-0200 port description pins alternative functions function switching register realtime output port p67/rp7/ tmbi timer b event output realtime output port p66/rp6/ adtrg a/d conversion start external trigger input port 6 p63 to p60 i/o ports p65/rp5 to p60/rp0 realtime output port pmr6 pmra ppg output p77/ppg7/ rpb to p74/ ppg4/rp8 realtime output port port 7 p77 to p70 i/o ports p73/ppg3 to p70/ppg0 ppg output pmr7 pmrb p87/dpg dpg signal input p86/exttrg external trigger signal input pre-amplifier output result signal input p85/comp/b color signal output (b) pre-amplifier output select signal input p84/h.amp sw/g color signal output (g) control signal output for processing color signals p83/c.rotary/r color signal output (r) p82/exctl external ctl signal input external capstan signal input p81/excap/ ybo osd character position output port 8 p87 to p80 i/o ports p80/yco osd character data output pmr8 pmrc notes: this lsi does not have port 5. * these alternative functions are not available in the h8s/2197s or h8s/2196s. section 10 i/o port rev.2.00 jan. 15, 2007 page 188 of 1174 rej09b0329-0200 10.1.3 mos pull-up transistors the mos pull-up transistors in ports 1 to 3 can be switched on or off by the mos pull-up select registers 1 to 3 (pur1 to pur3) in units of bits. settings in pur1 to pur3 are valid when the pin function is set to an input by pcr1 to pcr3. if the pin function is set to an output, the mos pull- up transistor is turned off. figure 10.1 shows the circuit configuration of a pin with a mos pull-up transistor. v cc pur stby stby legend: pcr pdr pur pcr pdr : low power consumption mode signal (the pull-up mos transistor is turned off by the stby signal in low power consumption mode except for sleep mode) : mos pull-up select register : port control register : port data register input data v cc v ss figure 10.1 circuit configuration of pin with mos pull-up transistor section 10 i/o port rev.2.00 jan. 15, 2007 page 189 of 1174 rej09b0329-0200 10.2 port 0 10.2.1 overview port 0 is an 8-bit input-only port. table 10.2 shows the port 0 configuration. port 0 consists of pins that are used both as standard input ports (p07 to p00) and analog input channels (an7 to an0). it is switched by port mode register 0 (pmr0). table 10.2 port 0 configuration port function alternative function port 0 p07 (standard input port) an7 (analog input channel) p06 (standard input port) an6 (analog input channel) p05 (standard input port) an5 (analog input channel) p04 (standard input port) an4 (analog input channel) p03 (standard input port) an3 (analog input channel) p02 (standard input port) an2 (analog input channel) p01 (standard input port) an1 (analog input channel) p00 (standard input port) an0 (analog input channel) 10.2.2 register configuration table 10.3 shows the port 0 register configuration. table 10.3 port 0 register configuration name abbrev. r/w size initial value address * port mode register 0 pmr0 r/w byte h'00 h'ffcd port data register 0 pdr0 r byte ? h'ffc0 note: * lower 16 bits of the address. section 10 i/o port rev.2.00 jan. 15, 2007 page 190 of 1174 rej09b0329-0200 port mode register 0 (pmr0) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 0 r/w r/w r/w r/w 6 pmr04 pmr03 pmr02 pmr01 pmr00 pmr07 pmr06 pmr05 bit : initial value : r/w : port mode register 0 (pmr0) controls switching of each pin function of port 0. the switching is specified in a unit of bit. pmr0 is an 8-bit read/write enable register. when reset, pmr0 is initialized to h'00. bits 7 to 0 ? p07/an7 to p00/an0 pin switching (pmr07 to pmr00): pmr07 to pmr00 set whether the p0n/ann pin is used as a p0n input pin or an ann pin for the analog input channel of an a/d converter. bit n pmr0n description 0 the p0n/ann pin functions as a p0n input pin (initial value) 1 the p0n/ann pin functions as an ann input pin note: n = 7 to 0 port data register 0 (pdr0) 0 1 r 2 r 3 4 r r 5 7 pdr04 pdr03 pdr02 pdr01 pdr00 r pdr07 r r r pdr06 pdr05 6 ? ? ? ? ? ? ?? initial value : r/w : bit : port data register 0 (pdr0) reads the port states. when the corresponding bit of pmr0 is 0 (general input port), the pin state is read if pdr0 is read. when the corresponding bit of pmr0 is 1 (analog input channel), 1 is read if pdr0 is read. pdr0 is an 8-bit read-only register. when pdr0 is reset, its values become undefined. section 10 i/o port rev.2.00 jan. 15, 2007 page 191 of 1174 rej09b0329-0200 10.2.3 pin functions this section describes the pin functions of port 0 and their selection methods. p07/an7 to p00/an0: p07/an7 to p00/an0 are switched according to the pmr0n bit of pmr0 as shown below. pmr0n pin function 0 p0n input pin 1 ann input pin note: n = 7 to 0 10.2.4 pin states table 10.4 shows the pin 0 st ates in each operation mode. table 10.4 port 0 pin states pins reset active sleep standby watch subactive subsleep p07/an7 to p00/an0 high- impedance high- impedance high- impedance high- impedance high- impedance high- impedance high- impedance section 10 i/o port rev.2.00 jan. 15, 2007 page 192 of 1174 rej09b0329-0200 10.3 port 1 10.3.1 overview port 1 is an 8-bit i/o port. table 10.5 shows the port 1 configuration. port 1 consists of pins that are used both as standard i/o ports (p17 to p10) and frequency division clock output (tmow), input capture input ( ic ), or external interrupt request inputs ( irq5 to irq0 ). it is switched by port mode register 1 (pmr1) and port control register 1 (pcr1). port 1 can select the functions of mos pull-up transistors. table 10.5 port 1 configuration port function alternative function port 1 p17 (standard i/o port) tmow (frequency division clock output) p16 (standard i/o port) ic (input capture input) p15 (standard i/o port) irq5 (external interrupt request input) p14 (standard i/o port) irq4 (external interrupt request input) p13 (standard i/o port) irq3 (external interrupt request input) p12 (standard i/o port) irq2 (external interrupt request input) p11 (standard i/o port) irq1 (external interrupt request input) p10 (standard i/o port) irq0 (external interrupt request input) 10.3.2 register configuration table 10.6 shows the port 1 register configuration. table 10.6 port 1 register configuration name abbrev. r/w size initial value address * port mode register 1 pmr1 r/w byte h'00 h'ffce port control register 1 pcr1 w byte h'00 h'ffd1 port data register 1 pdr1 r/w byte h'00 h'ffc1 mos pull-up select register 1 pur1 r/w byte h'00 h'ffe1 note: * lower 16 bits of the address. section 10 i/o port rev.2.00 jan. 15, 2007 page 193 of 1174 rej09b0329-0200 port mode register 1 (pmr1) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 0 r/w r/w r/w r/w 6 pmr14 pmr13 pmr12 pmr11 pmr10 pmr17 pmr16 pmr15 bit : initial value : r/w : port mode register 1 (pmr1) controls switching of each pin function of port 1. the switching is specified in a unit of bit. pmr1 is an 8-bit read/write enable register. when reset, pmr1 is initialized to h'00. note the following items when the pin functions are switched by pmr1. ? if port 1 is set to an ic input pin and irq5 to irq0 by pmr1, the pin level needs be set to the high or low level regardless of the active mode and low power consumption mode. the pin level must not be set to an intermediate level. ? when the pin functions of p16/ ic and p15/ irq5 to p10/ irq0 are switched by pmr1, they are incorrectly recognized as edge detection accordi ng to the state of a pin signal and a detection signal may be generated. to prevent this, perform the operation in the following procedure. ? before switching the pin functions, inhibit an interrupt enable flag from being interrupted. ? after having switched the pin functions, clear the relevant interrupt request flag to 0 by a single instruction. program example: : mov.b r0l,@ienr ?????? interrupt disabled mov.b r1l,@pmr1 ?????? pin function change nop ?????? optional instruction bclr m @irqr ?????? applicable interrupt clear mov.b r1l,@ienr ?????? interrupt enabled : bit 7 ? p17/tmow pin swit c hing (pmr17): pmr17 sets whether the p17/tmow pin is used as a p17 i/o pin or a tmow pin for the frequency division clock output. bit 7 pmr17 description 0 the p17/tmow pin functions as a p17 i/o pin (initial value) 1 the p17/tmow pin functions as a tmow output pin section 10 i/o port rev.2.00 jan. 15, 2007 page 194 of 1174 rej09b0329-0200 bit 6 ? p16/ ic pin switching (pmr16): pmr16 sets whether the p16/ ic pin as a p16 i/o pin or an ic pin for the input capture input of the prescalar unit. the ic pin has a built-in noise cancel circuit. see section 21, prescalar unit. bit 6 pmr16 description 0 the p16/ ic pin functions as a p16 i/o pin (initial value) 1 the p16/ ic pin functions as an ic input pin bits 5 to 0 ? p15/ irq5 to p10/ irq0 pin switching (pmr15 to pmr10): pmr15 to pmr10 set whether the p1n/ irqn pin is used as a p1n i/o pin or an irqn pin for the external interrupt request input. bit n pmr1n description 0 the p1n/ irqn pin functions as a p1n i/o pin (initial value) 1 the p1n/ irqn pin functions as an irqn input pin note: n = 5 to 0 port control register 1 (pcr1) 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 0 7 0 w w w w 6 pcr14 pcr13 pcr12 pcr11 pcr10 pcr17 pcr16 pcr15 bit : initial value : r/w : port control register 1 (pcr1) controls the i/os of pins p17 to p10 of port 1 in a unit of bit. when pcr1 is set to 1, the corresponding p17 to p10 pins become output pins, and when it is set to 0, they become input pins. when the relevant pin is set to a general i/o by pmr1, settings of pcr1 and pdr1 become valid. pcr1 is an 8-bit write-only register. when pcr1 is read, 1 is read. when reset, pcr1 is initialized to h'00. section 10 i/o port rev.2.00 jan. 15, 2007 page 195 of 1174 rej09b0329-0200 bits 7 to 0 ? p17 to p10 pin switching (pcr17 topcr10) bit n pcr1n description 0 the p1n pin functions as an input pin (initial value) 1 the p1n pin functions as an output pin note: n = 7 to 0 port data register 1 (pdr1) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 0 r/w r/w r/w r/w 6 pdr14 pdr13 pdr12 pdr11 pdr10 pdr17 pdr16 pdr15 bit : initial value : r/w : port data register 1 (pdr1) stores the data for the pins p17 to p10 of port 1. when pcr1 is 1 (output), the pdr1 values are directly read if por t 1 is read. accordingly, the pin states are not affected. when pcr1 is 0 (input), the pi n states are read if port 1 is read. pdr1 is an 8-bit read/ write enable register. when reset, pdr1 is initialized to h'00. mos pull-up select register 1 (pur1) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 0 r/w r/w r/w r/w 6 pur14 pur13 pur12 pur11 pur10 pur17 pur16 pur15 bit : initial value : r/w : mos pull-up selector register 1 (pur1) controls the on and off of the mos pull-up transistor of port 1. only the pin whose corresponding bit of pcr1 was set to 0 (input) becomes valid. when the corresponding bit of pcr1 is set to 1 (output), the corresponding bit of pur1 becomes invalid and the mos pull-up transistor is turned off. pur1 is an 8-bit read/ write enable register. when reset, pur1 is initialized to h'00. bits 7 to 0 ? p17 to p10 mos pull-up control (pcr17 to pcr10) bit n pur1n description 0 the p1n pin has no mos pull-up transistor (initial value) 1 the p1n pin has a mos pull-up pin note: n = 7 to 0 section 10 i/o port rev.2.00 jan. 15, 2007 page 196 of 1174 rej09b0329-0200 10.3.3 pin functions this section describes the port 1 pin functions and their selection methods. p17/tmow: p17/tmow is switched as shown below according to the pmr17 bit in pmr1 and the pcr17 bit in pcr1. pmr17 pcr17 pin function 0 p17 input pin 0 1 p17 output pin 1 * tmow output pin legend: * don?t care p16/ ic : p16/ ic is switched as shown below according to the pmr16 bit in pmr1, the nc on/off bit in prescalar unit control/status register (pcsr), and the pcr16 bit in pcr1. pmr16 pcr16 nc on/off pin function 0 p16 input pin 0 1 * p16 output pin 1 * 0 ic input pin noise cancel invalid 1 noise cancel valid legend: * don?t care p15/ irq5 to p10/ irq0 : p15/ irq15 to p10/ irq0 are switched as shown below according to the pmr1n bit in pmr1 and the pcr1n bit in pcr1. pmr1n pcr1n pin function 0 p1n input pin 0 1 p1n output pin 1 * irqn input pin legend: * don?t care. notes: 1. n = 5 to 0 2. the irq5 to irq0 input pins can select the leading or falling edge as an edge sense (the irq0 pin can select both edges). see section 6.2.4, irq edge select register (iegr). 3. irq1 or irq2 can be used as a timer j event input and irq3 can be used as a timer r input capture input. for details, see section 13, timer j or section 15, timer r. section 10 i/o port rev.2.00 jan. 15, 2007 page 197 of 1174 rej09b0329-0200 10.3.4 pin states table 10.7 shows the port 1 pin states in each operation mode. table 10.7 port 1 pin states pins reset active sleep standby watch subactive subsleep p17/tmow p16/ ic p15/ irq5 to p10/ irq0 high- impedance operation holding high- impedance high- impedance operation holding note: if the ic input pin and irq5 to irq0 input pins are set, the pin level need be set to the high or low level regardless of the active mode and low power consumption mode. note that the pin level must not reach an intermediate level. section 10 i/o port rev.2.00 jan. 15, 2007 page 198 of 1174 rej09b0329-0200 10.4 port 2 10.4.1 overview port 2 is an 8-bit i/o port. table 10.8 shows the port 2 configuration. port 2 consists of pins that are used both as standard i/o ports (p27 to p20) and sci clock i/o (sck1), receive data input (si1 ), send data output (so1), i 2 c bus interface clock i/o (scl0, scl1), or data i/o (sda0, sda1). it is switched by serial mode register (smr), serial control register (scr), and port control register 2 (pcr2). port 2 can select the mos pull-up function. table 10.8 port 2 configuration port function alternative function port 2 p27 (standard i/o port) synci (formatless serial clock input) p26 (standard i/o port) scl0 (i 2 c bus interface clock i/o) p25 (standard i/o port) sda0 (i 2 c bus interface data i/o) p24 (standard i/o port) scl1 (i 2 c bus interface clock i/o) p23 (standard i/o port) sda1 (i 2 c bus interface data i/o) p22 (standard i/o port) sck1 (sci1 clock i/o) p21 (standard i/o port) so1 (sci1 transmit data output) p20 (standard i/o port) si1 (sci1 receive data input) note: the h8s/2197s and h8s/2196s do not have synci, scl0, and sda0 pin functions. 10.4.2 register configuration table 10.9 shows the port 2 register configuration. table 10.9 port 2 register configuration name abbrev. r/w size initial value address * port control register 2 pcr2 w byte h'00 h'ffd2 port data register 2 pdr2 r/w byte h'00 h'ffc2 mos pull-up select register 2 pur2 r/w byte h'00 h'ffe2 note: * lower 16 bits of the address. section 10 i/o port rev.2.00 jan. 15, 2007 page 199 of 1174 rej09b0329-0200 port control register 2 (pcr2) 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 0 7 0 w w w w 6 pcr24 pcr23 pcr22 pcr21 pcr20 pcr27 pcr26 pcr25 bit : initial value : r/w : port control register 2 (pcr2) controls the i/os of pins p27 to p20 of port 2 in a unit of bit. when pcr2 is set to 1, the corresponding p27 to p20 pins become output pins, and when it is set to 0, they become input pins. wh en the relevant pin is set to a general i/o, settings of pcr2 and pdr2 are valid. pcr2 is an 8-bit write-only register. when pcr2 is read, 1 is read. when reset, pcr2 is initialized to h'00. bits 7 to 0 ? p27 to p20 pin switching (pcr27 to pcr20) bit n pcr2n description 0 the p2n pin functions as an input pin (initial value) 1 the p2n pin functions as an output pin note: n = 7 to 0 port data register 2 (pdr2) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 0 r/w r/w r/w r/w 6 pdr24 pdr23 pdr22 pdr21 pdr20 pdr27 pdr26 pdr25 bit : initial value : r/w : port data register 2 (pdr2) stores the data for the pins p27 to p20 of port 2. when pcr2 is 1 (output), the pdr2 values are directly read if por t 2 is read. accordingly, the pin states are not affected. when pcr2 is 0 (input), the pi n states are read if port 2 is read. pdr2 is an 8-bit read/write enable register. when reset, pdr2 is initialized to h'00. section 10 i/o port rev.2.00 jan. 15, 2007 page 200 of 1174 rej09b0329-0200 mos pull-up select register 2 (pur2) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 0 r/w r/w r/w r/w 6 pur24 pur23 pur22 pur21 pur20 pur27 pur26 pur25 bit : initial value : r/w : mos pull-up selector register 2 (pur2) controls the on and off of the mos pull-up transistor of port 2. only the pin whose corresponding bit of pcr2 was set to 0 (input) becomes valid. if the corresponding bit of pcr2 is set to 1 (output), the corresponding bit of pur2 becomes invalid and the mos pull-up transistor is turned off. pur2 is an 8-bit read/write enable register. when reset, pur2 is initialized to h'00. bits 7 to 0 ? p27 to p20 pull-up mos control (pur27 to pur20) bit n pur2n description 0 the p2n pin has no mos pull-up transistor (initial value) 1 the p2n pin has a mos pull-up transistor note: n = 7 to 0 10.4.3 pin functions this section describes the port 2 pin functions and their selection methods. p27/synci: p27/synci is switched as shown belo w according to the pcr27 bit in pcr2. pcr27 pin function 0 p27 input pin 1 p27 output pin notes: because the synci always functions, the alternative pin need always be set to the high or low level regardless of active mode or low power consumption mode. the h8s/2197s and h8s/2196s do not have synci pin function. section 10 i/o port rev.2.00 jan. 15, 2007 page 201 of 1174 rej09b0329-0200 p26/scl0: p26/scl0 is switched as shown below acco rding to the pcr26 bit in pcr2 and the ice bit in the i 2 c bus control register 0 (iccr0). ice pcr26 pin function 0 p26 input pin 0 1 p26 output pin 1 * scl0 i/o pin legend: * don?t care notes: the h8s/2197s and h8s/2196s do not have scl0 pin function. p25/sda0: p25/sda0 is switched as shown below acco rding to the pcr25 bit in pcr2 and the ice bit in the i 2 c bus control register 0 (iccr0). ice pcr25 pin function 0 p25 input pin 0 1 p25 output pin 1 * sda0 i/o pin legend: * don?t care notes: the h8s/2197s and h8s/2196s do not have sda0 pin function. p24/scl1: p24/scl1 is switched as shown below acco rding to the pcr24 bit in pcr2 and the ice bit in the i 2 c bus control register 1 (iccr1). ice pcr24 pin function 0 p24 input pin 0 1 p24 output pin 1 * scl1 i/o pin legend: * don?t care p23/sda1: p23/sda1 is switched as shown below acco rding to the pcr23 bit in pcr2 and the ice bit in the i 2 c bus control register 1 (iccr1). ice pcr23 pin function 0 p23 input pin 0 1 p23 output pin 1 * sda1 i/o pin legend: * don?t care section 10 i/o port rev.2.00 jan. 15, 2007 page 202 of 1174 rej09b0329-0200 p22/sck1: p22/sck1 is switched as shown below according to the pcr22 bit in pcr2, the c/ a bit in smr, and the cke1 and cke0 bits in scr. cke1 c/ a cke0 pcr22 pin function 0 p22 input pin 0 1 p22 output pin 0 1 * sck1 output pin 0 1 * 1 * sck1 input pin legend: * don?t care p21/so1: p21/so1 is switched as shown below according to the pcr21 bit in pcr2 and the te bit in scr. te pcr21 pin function 0 p21 input pin 0 1 p21 output pin 1 * so1 output pin legend: * don?t care p20/si1: p20/si1 is switched as shown below according to the pcr20 bit in pcr2 and the re bit in scr. re pcr20 pin function 0 p20 input pin 0 1 p20 output pin 1 * si1 input pin legend: * don?t care section 10 i/o port rev.2.00 jan. 15, 2007 page 203 of 1174 rej09b0329-0200 10.4.4 pin states table 10.10 shows the port 2 pin states in each operation mode. table 10.10 port 2 pin states pins reset active sleep standby watch subactive subsleep p27/synci p26/scl0 p25/sda0 p24/scl1 p23/sda1 p22/sck1 p21/so1 p20/si1 high- impedance operation holding high- impedance high- impedance operation holding note: because the synci, scl0, sda0, scl1, and sda1 always function, the alternative pin need always be set to the high or low level regardless of active mode or low power consumption mode. if the sck1, and si1 input pins are set, the pin level needs be set to the high or low level regardless of the active mode and low power consumption mode. note that the pin level must not reach an intermediate level. section 10 i/o port rev.2.00 jan. 15, 2007 page 204 of 1174 rej09b0329-0200 10.5 port 3 10.5.1 overview port 3 is an 8-bit i/o port. table 10.11 shows the port 3 configuration. port 3 consists of pins that are used both as standard i/o ports (p37 to p30) and timer j timer output (tmo), buzzer output (buzz), 8-bit pwm outputs (pwm3 to pwm0), sci2 strobe output (strb), or chip select input ( cs ). it is switched by port mode register 3 (pmr3) and port control register 3 (pcr3). port 3 can select the mos pull-up function. table 10.11 port 3 configuration port function alternative function port 3 p37 (standard i/o port) tmo (timer j timer output) p36 (standard i/o port) buzz (timer j buzzer output) p35 (standard i/o port) pwm3 (8-bit pwm output) p34 (standard i/o port) pwm2 (8-bit pwm output) p33 (standard i/o port) pwm1 (8-bit pwm output) p32 (standard i/o port) pwm0 (8-bit pwm output) p31 (standard i/o port) sv2 (servo monitor output) p30 (standard i/o port) sv1 (servo monitor output) note: the h8s/2197s and h8s/2196s do not have pwm3 and pwm2 pin functions. 10.5.2 register configuration table 10.12 shows the port 3 register configuration. table 10.12 port 3 register configuration name abbrev. r/w size initial value address * port mode register 3 pmr3 r/w byte h'00 h'ffd0 port control register 3 pcr3 w byte h'00 h'ffd3 port data register 3 pdr3 r/w byte h'00 h'ffc3 mos pull-up select register 3 pur3 r/w byte h'00 h'ffe3 note: * lower 16 bits of the address. section 10 i/o port rev.2.00 jan. 15, 2007 page 205 of 1174 rej09b0329-0200 port mode register 3 (pmr3) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 0 r/w r/w r/w r/w 6 pmr34 pmr33 pmr32 pmr31 pmr30 pmr37 pmr36 pmr35 bit : initial value : r/w : port mode register 3 (pmr3) controls switching of each pin function of port 3. the switching is specified in a unit of bit. pmr3 is an 8-bit read/write enable register. when reset, pmr3 is initialized to h'00. bit 7 ? p37/tmo pin switching (pmr37): pmr37 sets whether the p37/tmo pin is used as a p37 i/o pin or a tmo pin for the timer j output timer. bit 7 pmr37 description 0 the p37/tmo pin functions as a p37 i/o pin (initial value) 1 the p37/tmo pin functions as a tmo output pin notes: if the tmo pin is used for remote control sending, a careless timer output pulse may be output when the remote control mode is set after the output has been switched to the tmo output. perform the switching and setting in the following order. 1. set the remote control mode. 2. set the tmj-1 and 2 counter data of the timer j. 3. switch the p37/tmo pin to the tmo output pin. 4. set the st bit to 1. bit 6 ? p36/buzz pin switching (pmr36): pmr36 sets whether the p36/buzz pin as a p36 i/o pin or an buzz pin for the timer j buzzer out put. for the selection of the buzz output, see 13.2.2, timer j control register (tmjc). bit 6 pmr36 description 0 the p36/buzz pin functions as a p36 i/o pin (initial value) 1 the p36/buzz pin functions as a buzz output pin section 10 i/o port rev.2.00 jan. 15, 2007 page 206 of 1174 rej09b0329-0200 bits 5 to 2 ? p35/pwm3 to p32/pwm0 pin switching (pmr35 to pmr32): pmr35 to pmr32 set whether the p3n/pwmm pin is used as a p3n i/o pin or a pwmm pin for the 8-bit pwm output. bit n pmr3n description 0 the p3n/pwmm pin functions as a p3n i/o pin (initial value) 1 the p3n/pwmm pin functions as a pwmm output pin notes: 1. n = 5 to 2, m = 3 to 0 2. the h8s/2197s and h8s/2196s do not have pwm3 and pwm2 pin functions. bit 1 ? p31/sv2 pin switching (pmr31): pmr31 sets whether the p31/sv2 pin is used as a p31 i/o pin or an sv2 pin for the servo monitor output. bit 1 pmr31 description 0 the p31/sv2 pin functions as a p31 i/o pin (initial value) 1 the p31/sv2 pin functions as an sv2 output pin bit 0 ? p30/sv1 pin switching (pmr30): pmr30 sets whether the p30/sv1 pin is used as a p30 i/o pin or an sv1 pin for servo monitor output. bit 0 pmr30 description 0 the p30/sv1 pin functions as a p30 i/o pin (initial value) 1 the p30/sv1 pin functions as an sv1 output pin section 10 i/o port rev.2.00 jan. 15, 2007 page 207 of 1174 rej09b0329-0200 port control register 3 (pcr3) 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 0 7 0 w w w w 6 pcr34 pcr33 pcr32 pcr31 pcr30 pcr37 pcr36 pcr35 bit : initial value : r/w : port control register 3 (pcr3) controls the i/os of pins p37 to p30 of port 3 in a unit of bit. when pcr3 is set to 1, the corresponding p37 to p30 pins become output pins, and when it is set to 0, they become input pins. when the relevant pin is set to a general i/o by pmr3, settings of pcr3 and pdr3 become valid. pcr3 is an 8-bit write-only register. when pcr3 is read, 1 is read. when reset, pcr3 is initialized to h'00. bits 7 to 0 ? pin 37 to p30 pin switching (pcr37 to pcr30) bit n pcr3n description 0 the p3n pin functions as an input pin (initial value) 1 the p3n pin functions as an output pin note: n = 7 to 0 port data register 3 (pdr3) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 0 r/w r/w r/w r/w 6 pdr34 pdr33 pdr32 pdr31 pdr30 pdr37 pdr36 pdr35 bit : initial value : r/w : port data register 3 (pdr3) stores the data for the pins p37 to p30 of port 3. when pcr3 is 1 (output), the pdr3 values are directly read if por t 3 is read. accordingly, the pin states are not affected. when pcr3 is 0 (input), the pi n states are read if port 3 is read. pdr3 is an 8-bit read/write enable register. when reset, pdr3 is initialized to h'00. section 10 i/o port rev.2.00 jan. 15, 2007 page 208 of 1174 rej09b0329-0200 mos pull-up select register 3 (pur3) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 0 r/w r/w r/w r/w 6 pur34 pur33 pur32 pur31 pur30 pur37 pur36 pur35 bit : initial value : r/w : mos pull-up selector register 3 (pur3) controls the on and off of the mos pull-up transistor of port 3. only the pin whose corresponding bit of pcr3 was set to 0 (input) becomes valid. if the corresponding bit of pcr3 is set to 1 (output), the corresponding bit of pur3 becomes invalid and the mos pull-up transistor is turned off. pur3 is an 8-bit read/write enable register. when reset, pur3 is initialized to h'00. bits 7 to 0 ? p37 to p30 mos pull-up control (pur37 to pur30) bit n pcr3n description 0 the p3n pin has no mos pull-up transistor (initial value) 1 the p3n pin has a mos pull-up transistor note: n = 7 to 0 10.5.3 pin functions this section describes the port 3 pin functions and their selection methods. p37/tmo: p37/tmo is switched as shown below accord ing to the pmr37 b it in pmr3 and the pcr37 bit in pcr3. pmr37 pcr37 pin function 0 p37 input pin 0 1 p37 output pin 1 * tmo output pin legend: * don?t care section 10 i/o port rev.2.00 jan. 15, 2007 page 209 of 1174 rej09b0329-0200 p36/buzz: p36/buzz is switched as shown below according to the pmr36 bit in pmr3 and the pcr36 bit in pcr3. pmr36 pcr36 pin function 0 p36 input pin 0 1 p36 output pin 1 * buzz output pin legend: * don?t care p35/pwm3: p35/pwm3 is switched as shown below according to the pmr3n bit in pmr3 and the pcr3n bit in pcr3. pmr35 pcr35 pin function 0 p35 input pin 0 1 p35 output pin 1 * pwm3 output pin legend: * don?t care note: the h8s/2197s and h8s/2196s do not have pwm3 pin function. p34/pwm2: p34/pwm2 is switched as shown below according to the pmr34 bit in pcr3 and the pcr34 bit in pcr3. pmr34 pcr34 pin function 0 p34 input pin 0 1 p34 output pin 1 * pwm2 output pin legend: * don?t care note: the h8s/2197s and h8s/2196s do not have pwm2 pin function. p33/pwm1: p33/pwm1 is switched as shown below according to the pmr33 bit in pmr3 and the pcr33 bit in pcr3. pmr33 pcr33 pin function 0 p33 input pin 0 1 p33 output pin 1 * pwm1 input pin legend: * don?t care section 10 i/o port rev.2.00 jan. 15, 2007 page 210 of 1174 rej09b0329-0200 p32/pwm0: p32/pwm0 is switched as shown below according to the pmr32 bit in pmr3 and the pcr32 bit in pcr. pmr32 pcr32 pin function 0 p32 input pin 0 1 p32 output pin 1 * pwm0 output pin p31/sv2: p31/sv2 is switched as shown below according to the pmr31 bit in pmr3 and the pcr31 bit in pcr3. pmr31 pcr3 pin function 0 p31 input pin 0 1 p31 output pin 1 * sv2 output pin p30/sv1: p30/sv1 is switched as shown below according to the pmr30 bit in pmr3 and the pcr30 bit in pcr3. pmr30 pcr30 pin function 0 p30 input pin 0 1 p30 output pin 1 * sv1 output pin legend: * don?t care 10.5.4 pin states table 10.13 shows the port 3 pin states in each operation mode. table 10.13 port 3 pin states pins reset active sleep standby watch subactive subsleep p37/tmo p36/buzz p35/pwm3 to p32/pwm0 p31/sv2 p30/sv1 high- impedance operation holding high- impedance high- impedance operation holding section 10 i/o port rev.2.00 jan. 15, 2007 page 211 of 1174 rej09b0329-0200 10.6 port 4 10.6.1 overview port 4 is an 8-bit i/o port. table 10.14 shows the port 4 configuration. port 4 consists of pins that are used both as standard i/o ports (p47 to p40) and output compare output (ftoa, ftob), input capture input (ftia, ftib, ftic, ftid) or 14-bit pwm output (pwm14). it is switched by port mode register 4 (pmr4), timer output compare control register (tocr), and port control register 4 (pcr4). table 10.14 port 4 configuration port function alternative function port 4 p47 (standard i/o port) rptrg (realtime output port trigger input) p46 (standard i/o port) ftob (timer x1 output compare output) p45 (standard i/o port) ftoa (timer x1 output compare output) p44 (standard i/o port) ftid (timer x1 input capture input) p43 (standard i/o port) ftic (timer x1 input capture input) p42 (standard i/o port) ftib (timer x1 input capture input) p41 (standard i/o port) ftia (timer x1 input capture input) p40 (standard i/o port) pwm14 (14-bit pwm output) note: the h8s/2197s and h8s/2196s do not have pwm14, ftia, ftib, ftic, ftid, ftoa, and ftob pin functions. 10.6.2 register configuration table 10.15 shows the port 4 register configuration. table 10.15 port 4 register configuration name abbrev. r/w size initial value address * port mode register 4 pmr4 r/w byte h'7e h'ffdb port control register 4 pcr4 w byte h'00 h'ffd4 port data register 4 pdr4 r/w byte h'00 h'ffc4 note: * lower 16 bits of the address. section 10 i/o port rev.2.00 jan. 15, 2007 page 212 of 1174 rej09b0329-0200 port mode register 4 (pmr4) 0 0 1 1 2 1 3 1 4 1 1 5 1 7 0 r/w 6 ? ? ? ? ? pmr47 ? ? ? ? ? ? r/w ? pmr40 bit : initial value : r/w : port mode register 4 (pmr4) controls switching of the p47/rptrg pin and the p40/pwm14 pin function. the switchings of the p46/ftob and p45/ftoa functions are controlled by tocr. see section 16, timer x1. the ftia, ftib, ftic, and ftid inputs always function. pmr4 is an 8-bit read/write enable register. when reset, pmr4 is initialized to h'7e. because the rptrg input always function, the altern ative pin need always be set to the high or low level regardless of the active mode and low power consumption mode. note that the pin level must not reach an intermediate level. because the ftia, ftib, ftic, and ftid inputs al ways function, each input uses the input edge to the alternative general i/o pins p44, p43, p42, and p41 as input signals. bit 7 ? p47/rptrg pin switching (pmr47): pmr47 sets whether the p47/rptrg pin is used as a p40 i/o pin or a rptrg pin for the realtime output port trigger input. bit 7 pmr47 description 0 the p47/rptrg pin functions as a p47 i/o pin (initial value) 1 the p47/rptrg pin functions as a rptrg i/o pin bits 6 to 1 ? reserved bits: reserved bits. when th e bits are read, 1 is always read. the write operation is invalid. bit 0 ? p40/pwm14 pin switching (pmr40): pmr40 sets whether the p40/pwm14 pin is used as a p40 i/o pin or a pwm14 pin for the 14-bit pwm square wave output. bit 0 pmr40 description 0 the p40/pwm14 pin functions as a p40 i/o pin (initial value) 1 the p40/pwm14 pin functions as a pwm14 output pin note: the h8s/2197s and h8s/2196s do not have pwm14 pin function. section 10 i/o port rev.2.00 jan. 15, 2007 page 213 of 1174 rej09b0329-0200 port control register 4 (pcr4) 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 0 7 0 w w w w 6 pcr44 pcr43 pcr42 pcr41 pcr40 pcr47 pcr46 pcr45 bit : initial value : r/w : port control register 4 (pcr4) controls the i/os of pins p47 to p40 of port 4 in a unit of bit. when pcr4 is set to 1, the corresponding p47 to p40 pins become output pins, and when it is set to 0, they become input pins. when the relevant pin is set to a general i/o by pmr4, settings of pcr4 and pdr4 become valid. pcr4 is an 8-bit write-only register. when pcr4 is read, 1 is read. when reset, pcr4 is initialized to h'00. bits 7 to 0 ? p47 to p40 pin switching (pcr47 to pcr40) bit n pcr4n description 0 the p4n pin functions as an input pin (initial value) 1 the p4n pin functions as an output pin note: n = 7 to 0 port data register 4 (pdr4) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 0 r/w r/w r/w r/w 6 pdr44 pdr43 pdr42 pdr41 pdr40 pdr47 pdr46 pdr45 bit : initial value : r/w : port data register 4 (pdr4) stores the data for the pins p47 to p40 of port 4. when pcr4 is 1 (output), the pdr4 values are directly read if por t 4 is read. accordingly, the pin states are not affected. when pcr4 is 0 (input), the pi n states are read if port 4 is read. pdr4 is an 8-bit read/write enable register. when reset, pdr4 is initialized to h'00. section 10 i/o port rev.2.00 jan. 15, 2007 page 214 of 1174 rej09b0329-0200 10.6.3 pin functions this section describes the port 4 pin functions and their selection methods. p47/rptrg: p47/rptrg is switched as shown below according to the pmr47 bit in pmr4 and the pmr47 bit in pmr4 and the pcr47 bit in pcr4. pmr47 pcr47 pin function 0 0 p47 input pin 1 p47 output pin 1 * rptrg input pin legend: * don?t care p46/ftob: p46/ftob is switched as shown below according to the pcr46 bit in pcr4 and the oeb bit in tocr. oeb pcr46 pin function 0 p46 input pin 0 1 p46 output pin 1 * ftob output pin legend: * don?t care note: the h8s/2197s and h8s/2196s do not have ftob pin function. p45/ftoa: p45/ftoa is switched as shown below according to the pcr45 bit in pcr4 and the oea bit in tocr. oea pcr45 pin function 0 p45 input pin 0 1 p45 output pin 1 * ftoa output pin legend: * don?t care note: the h8s/2197s and h8s/2196s do not have ftoa pin function. section 10 i/o port rev.2.00 jan. 15, 2007 page 215 of 1174 rej09b0329-0200 p44/ftid: p44/ftid is switched as shown belo w according to the p cr44 bit in pcr4. pcr44 pin function 0 p44 input pin ftid input pin 1 p44 output pin note: the h8s/2197s and h8s/2196s do not have ftid pin function. p43/ftic: p43/ftic is switched as shown belo w according to the p cr43 bit in pcr4. pcr43 pin function 0 p43 input pin ftic input pin 1 p43 output pin note: the h8s/2197s and h8s/2196s do not have ftic pin function. p42/ftib: p42/ftib is switched as shown belo w according to the p cr42 bit in pcr4. pcr42 pin function 0 p42 input pin ftib input pin 1 p42 output pin note: the h8s/2197s and h8s/2196s do not have ftib pin function. p41/ftia: p41/ftia is switched as shown belo w according to the pc r41 bit in pcr4. pcr41 pin function 0 p41 input pin ftia input pin 1 p41 output pin note: the h8s/2197s and h8s/2196s do not have ftia pin function. p40/pwm14: p40/pwm14 is switched as shown below according to the pmr40 bit in pmr4 and the pcr40 bit in pcr4. pmr40 pcr40 pin function 0 p40 input pin 0 1 p40 output pin 1 * pwm14 input pin legend: * don?t care note: the h8s/2197s and h8s/2196s do not have pwm14 pin function. section 10 i/o port rev.2.00 jan. 15, 2007 page 216 of 1174 rej09b0329-0200 10.6.4 pin states table 10.16 shows the port 4 pin states in each operation mode. table 10.16 port 4 pin states pins reset active sleep standby watch subactive subsleep p47/rptrg p46/ftob p45/ftoa p44/ftid p43/ftic p42/ftib p41/ftia p40/pwm14 high- impedance operation holding high- impedance high- impedance operation holding note: if the rptrg input pin is set, the pin level must be set to the high or low level regardless of the active mode or low power consumption mode. note that the pin level must not reach an intermediate level. because the ftia, ftib, ftic, and ftid inputs always function, the alternative pin need be set to the high or low level regardless of the active mode and low power consumption mode. section 10 i/o port rev.2.00 jan. 15, 2007 page 217 of 1174 rej09b0329-0200 10.7 port 6 10.7.1 overview port 6 is an 8-bit i/o port. table 10.17 shows the port 6 configuration. port 6 is a large current i/o port. the sink current is 20 ma maximum (vol = 1.7 v) and four pins can be turned on at the same time. port 6 consists of pins that are used as large current i/o ports (p67 to 60) and realtime output ports (rp7 to rp0). it is switched by port mode register 6 (pmr6), port mode register a (pmra), and port control register 6 (pcr6). the realtime output function can instantaneously switch the output data by an external or internal trigger port. table 10.17 port 6 configuration port function alternative function port 6 p67 (large current i/o port) rp7/tmbi (timer b event input) p66 (large current i/o port) rp6/ adtrg (a/d conversion start external trigger input) p65 (large current i/o port) rp5 (realtime output port pin) p64 (large current i/o port) rp4 (realtime output port pin) p63 (large current i/o port) rp3 (realtime output port pin) p62 (large current i/o port) rp2 (realtime output port pin) p61 (large current i/o port) rp1 (realtime output port pin) p60 (large current i/o port) rp0 (realtime output port pin) section 10 i/o port rev.2.00 jan. 15, 2007 page 218 of 1174 rej09b0329-0200 10.7.2 register configuration table 10.18 shows the port 6 register configuration. table 10.18 port 6 register configuration name abbrev. r/w size initial value address * port mode register 6 pmr6 r/w byte h'00 h'ffdd port mode register a pmra r/w byte h'3f h'ffd9 port control register 6 pcr6 w byte h'00 h'ffd6 port data register 6 pdr6 r/w byte h'00 h'ffc6 realtime output trigger select register 1 rtpsr1 r/w byte h'00 h'ffe5 realtime output trigger edge select register rtpegr * 2 r/w byte h'fc h'ffe4 port control register slave 6 pcrs6 ? byte h'00 ? port data register slave 6 pdrs6 ? byte h'00 ? notes: 1. lower 16 bits of the address. 2. rtpegr is also used by port 7. port mode register 6 (pmr6) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 6 0 7 pmr64 pmr63 pmr62 pmr61 pmr60 0 r/w pmr67 r/w r/w r/w pmr66 pmr65 bit : initial value : r/w : port mode register 6 (pmr6) controls switching of each pin function of port 6. the switching is specified in units of bits. pmr6 is an 8-bit read/write enable register. when reset, pmr6 is initialized to h'00. bits 7 to 0 ? p67/rp7 to p60/rp0 pin switching (pmr67 to pmr60): pmr67 to pmr60 set whether the p6n/rpn pin is used as a p6n i/o pin or an rpn pin for the realtime output port. bit n pmr6n description 0 the p6n/rpn pin functions as a p6n i/o pin (initial value) 1 the p6n/rpn pin functions as an rpn output pin note: n = 7 to 0 section 10 i/o port rev.2.00 jan. 15, 2007 page 219 of 1174 rej09b0329-0200 port mode register a (pmra) 0 1 1 1 ? 2 1 ? 3 1 4 1 ? 1 ? 5 0 7 0 r/w ? ? r/w 6 ????? pmra7 pmra6 ? bit : initial value : r/w : port mode register a (pmra) switches the pin functions in port 6. switching is specified in a unit of bit. pmra is an 8-bit read/write register. when reset, pmra is initialized to h'3f. bit 7 ? p67/rp7/tmbi pin switching (pmra7): pmra7 can be used as a p6n i/o pin or a tmbi pin for timer b event input. bit 7 pmra7 description 0 p67/rp7/tmbi pin functions as a p67/rp7 i/o pin (initial value) 1 p67/rp7/tmbi pin functions as a tmbi pin bit 6 ? timer b event input edge switching (pmra6): pmra6 selects the tmbi edge sense. bit 6 pmra6 description 0 timer b event input detects falling edge 1 timer b event input detects rising edge section 10 i/o port rev.2.00 jan. 15, 2007 page 220 of 1174 rej09b0329-0200 port control register 6 (pcr6) 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 pcr64 pcr63 pcr62 pcr61 pcr60 0 w pcr67 w w w pcr66 pcr65 bit : initial value : r/w : port control register 6 (pcr6) selects the general i/o of port 6 and controls the realtime output in a unit of bit together with pmr6. when pmr6 = 0, the corresponding p67 to p60 pins become general output pins if pcr6 is set to 1, and they become general input pins if it is set to 0. when pmr6 = 1, pcr6 controls the corresponding rp7 to rp0 realtime output pins. for details, see section 10.7.4, operation. pcr6 is an 8-bit write-only register. when pcr6 is read, 1 is read. when reset, pcr6 is initialized to h'00. pmr6 pcr6 bit n bit n pmr6n pcr6n description 0 the p6n/rpn pin functions as a p6n general i/o input pin (initial value) 0 1 the p6n/rpn pin functions as a p6n general output pin 1 * the p6n/rpn pin functions as an rpn realtime output pin legend: * don?t care note: n = 7 to 0 port data register 6 (pdr6) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 6 0 7 pdr64 pdr63 pdr62 pdr61 pdr60 0 r/w pdr67 r/w r/w r/w pdr66 pdr65 bit : initial value : r/w : port data register 6 (pdr6) stores the data for the pins p67 to p60 of port 6. for pmr6 = 0, when pcr6 is 1 (output), the pdr6 values are directly read if port 6 is read. accordingly, the pin states are not affected. when pcr6 is 0 (input), the pin states are read if port 6 is read. for pmr6 = 1, port 6 becomes a realtime output pin. for details, see section 10.7.4, operation. pdr6 is an 8-bit read/write enable register. when reset, pdr6 is initialized to h'00. section 10 i/o port rev.2.00 jan. 15, 2007 page 221 of 1174 rej09b0329-0200 realtime output trigger select register (rtpsr1) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 6 0 7 rtpsr14 rtpsr13 rtpsr12 rtpsr11 rtpsr10 0 r/w rtpsr17 r/w r/w r/w rtpsr16 rtpsr15 bit : initial value : r/w : the realtime output trigger select register (rtpsr1) sets whether the external trigger (rptrg pin input) or the internal trigger (hsw) is used as an trigger input for the r ealtime output in a unit of bit. for the internal trigger hsw, see section 26.4, hsw (head-switch) timing generator. rtpsr1 is an 8-bit read/write enable register. when reset, rtpsr1 is initialized to h'00. bits 7 to 0 ? rp7 to rp0 trigger switching bit n rtpsr1n description 0 selects the external trigger (rptrg pin input) as a trigger input (initial value) 1 selects the internal trigger (hsw) a trigger input note: n = 7 to 0 real time output trigger edge select register (rtpegr) 0 0 1 0 r/w 2 1 3 1 4 1 1 5 6 1 7 ? ? ? ? ? ? ? ? ? ? ? ? rtpegr1 rtpegr0 1 r/w bit : initial value : r/w : the realtime output trigger edge select register (rtpegr) specifies the edge sense of the external or internal trigger input for the realtime output. rtpegr is an 8-bit read/write enable register. when reset, rtpegr is initialized to h'fc. bits 7 to 2 ? reserved bits: reserved bits. when th e bits are read, 1 is always read. the write operation is invalid. section 10 i/o port rev.2.00 jan. 15, 2007 page 222 of 1174 rej09b0329-0200 bits 1 and 0 ? realtime output trigger edge select (rtpegr1, rtpegr0): rtpegr1 and rtpegr0 select the edge sense of the external or internal trigger input for the realtime output. bit 1 bit 0 rtpegr1 rtpegr0 description 0 inhibits a trigger input (initial value) 0 1 selects the rising edge of a trigger input 1 0 selects the falling edge of a trigger input 1 selects both the leading and falling edges of a trigger input 10.7.3 pin functions this section describes the port 6 pin functions and their selection methods. p67/rp7/tmbi: p67/rp7/tmbi is switched as show n below according to the pmra7 bit in pmra, pmr67 bit in pmr6, and pcr67 bit in pcr6. pmra7 pmr67 pcr67 pin function output value value when pdr6n was read 0 p67 input pin ? p67 pin 0 1 p67 output pin pdr67 pdr67 0 hi-z * 1 * 2 0 1 1 rp7 output pin pdrs67 * 2 pdr67 1 * 0 tmbi input pin ? p67 pin 1 pdr67 notes: 1. hi-z: high impedance 2. when pmr67 = 1 (realtime output pin), indicates the state after the pcr67 setup value has been transferred to pcrs67 by a trigger input. section 10 i/o port rev.2.00 jan. 15, 2007 page 223 of 1174 rej09b0329-0200 p66/rp6/ adtrg : p66/rp6/ adtrg is switched as shown below according to the pmr66 bit in pmr6 and pcr66 bit in pcr6. the adtrg pin function switching is controlled by the adtsr. for details, refer to section 24, a/d converter. pmr66 pcr66 pin function output va lue value when pdr66 was read 0 p66 input pin ? p66 pin 0 1 p66 output pin pdr66 pdr66 1 0 rp6 output pin hi-z * 1 * 2 pdr66 1 pdrs66 * 2 notes: 1. hi-z: high impedance 2. when pmr66 = 1 (realtime output pin), indicates the state after the pcr66 setup value has been transferred to pcrs66 by a trigger input. p65/rp5 to p60/rpd: p65/rp5 to p60/rpd are switched be low according to th e pmran bit in pmra, pmr6n bit in pmr6, and pcr6n bit in pcr6. pmr6n pcr6n pin function output value value when pdr6n was read 0 p6n input pin ? p6n pin 0 1 p6n output pin pdr6n pdr6n 1 0 rpn output pin hi-z * 1 * 2 pdr6n 1 rpn output pin pdrs6n * 2 notes: n = 5 to 0 1. hi-z: high impedance 2. when pmr6n = 1 (realtime output pin), indicates the state after the pcr6n setup value has been transferred to pcrs6n by a trigger input. section 10 i/o port rev.2.00 jan. 15, 2007 page 224 of 1174 rej09b0329-0200 10.7.4 operation port 6 can be used as a realtime output port or general i/o output port by pmr6. port 6 functions as a realtime output port when pmr6 = 1 and as a general i/o port when pmr6 = 0. the operation per port 6 function is shown below. (see figure 10.2.) p6/rp rtpegr write legend: pmr6 pcr6 pdr6 pcrs6 pdrs6 rtpsr1 rtpegr hsw rptrg : port mode register 6 : port control register 6 : port data register 6 : port control register slave 6 : port data register slave 6 : realtime output trigger select register : realtime output trigger edge select register : internal trigger signal : external trigger pin rtpsr write rmr6 write rdr6 write rcr6 write rdr6 read rtpegr selection circuit selection circuit internal data bus external trigger rptrg internal trigger hsw ck rtpsr1 ck pmr6 ck pdr6 ck pcr6 ck rdrs6 ck pcrs6 ck figure 10.2 port 6 function block diagram section 10 i/o port rev.2.00 jan. 15, 2007 page 225 of 1174 rej09b0329-0200 ? operation of the realtime output port (pmr6 = 1) when pmr6 is 1, it operates as a realtime output port. when a trigger is input, the pdr6 data is transferred to pdrs6 and the pcr6 is transferred data to pcrs6, respectively. in this case, when pcrs6 is 1, the pdrs6 data of the corresponding bit is output to the rp pin. when pcrs6 is 0, the rp pin of the corresponding bit is output to the high-impedance state. in other words, the pin output state (high or low) or high-impedance state can instantaneously be switched by a trigger input. adversely, when pdr6 is read, the pdr6 values are read regardless of the pcr6 and pcrs6 values. ? operation of the general i/o port (pmr6 = 0) when pmr6 is 0, it operates as a general i/o port. when data is written to pdr6, the same data is also written to pdrs6. accordingly, because both pdr6 and pdrs6 and both pcr6 and pcrs6 can be handled as one register, respectively, they can be used in the same way as a normal general i/o port. in other words, if pcr6 is 1, the pdr6 data of the corresponding bit is output to the p6 pin. if pcr6 is 0, the p6 pin of the corresponding bit becomes an input. adversely, assuming that pdr6 is read, the pdr6 values are read when pcr6 is 1 and the pin values are read when pcr6 is 0. 10.7.5 pin states table 10.19 shows the port 6 pin states in each operation mode. table 10.19 port 6 pin states pins reset active sleep standby watch subactive subsleep p67/rp7/tmbi p66/rp6/ adtrg p65/rp5 to p60/rp0 high- impedance operation holding high- impedance high- impedance operation holding note: if the tmbi and adtrg input pins are set, the pin level must be set to the high or low level regardless of the active mode or low power consumption mode. note that pin level must not reach an intermediate level. section 10 i/o port rev.2.00 jan. 15, 2007 page 226 of 1174 rej09b0329-0200 10.8 port 7 10.8.1 overview port 7 is an 8-bit i/o port. table 10.20 shows the port 7 configuration. port 7 consists of pins that are used both as standard i/o ports (p77 to p70), hsw timing generation circuit (programmable pattern generator: ppg) outputs (ppg7 to ppg0), and realtime output port (rpb to rp8). it is switched by port mode register 7 (pmr7) and port control register 7 (pcr7). for the programmable generator (ppg), see section 26.4, hsw (head-switch) timing generator. table 10.20 port 7 configuration port function alternative function port 7 ppg7 (hsw timing output) p77 (standard i/o port) rpb (realtime output port) ppg6 (hsw timing output) p76 (standard i/o port) rpa (realtime output port) ppg5 (hsw timing output) p75 (standard i/o port) rp9 (realtime output port) ppg4 (hsw timing output) p74 (standard i/o port) rp8 (realtime output port) p73 (standard i/o port) ppg3 (hsw timing output) p72 (standard i/o port) ppg2 (hsw timing output) p71 (standard i/o port) ppg1 (hsw timing output) p70 (standard i/o port) ppg0 (hsw timing output) section 10 i/o port rev.2.00 jan. 15, 2007 page 227 of 1174 rej09b0329-0200 10.8.2 register configuration table 10.21 shows the port 7 register configuration. table 10.21 port 7 register configuration name abbrev. r/w size initial value address * port mode register 7 pmr7 r/w byte h'00 h'ffde port mode register b pmrb r/w byte h'0f h'ffda port control register 7 pcr7 w byte h'00 h'ffd7 port data register 7 pdr7 r/w byte h'00 h'ffc7 realtime output trigger select register 2 rtpsr2 r/w byte h'0f h'ffe6 realtime output trigger edge select register rtpegr r/w byte h'fc h'ffe4 port control register slave 7 pcrs7 ? byte h'00 ? port data register slave 7 pdrs7 ? byte h'00 ? note: * lower 16 bits of the address. port mode register 7 (pmr7) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 6 0 7 pmr74 pmr73 pmr72 pmr71 pmr70 0 r/w pmr77 r/w r/w r/w pmr76 pmr75 bit : initial value : r/w : port mode register 7 (pmr7) controls switching of each pin function of port 7. the switching is specified in a unit of bit. pmr7 is an 8-bit read/write enable register. when reset, pmr7 is initialized to h'00. bits 7 to 0 ? p77/ppg7 to p70/ppg0 pin switching (pmr77 to pmr70): pmr77 to pmr70 set whether the p7n/ppgn pin is used as a p7n i/o pin or a ppgn pin for the hsw timing generation circuit output. bit n pmr7n description 0 the p7n/ppgn pin functions as a p7n i/o pin (initial value) 1 the p7n/ppgn pin functions as a ppgn output pin note: n = 7 to 0 section 10 i/o port rev.2.00 jan. 15, 2007 page 228 of 1174 rej09b0329-0200 port mode register b (pmrb) 0 1 1 1 2 1 3 1 4 ? ? ? pmrb4 ? ? ? r/w 0 0 r/w 5 0 7 0 r/w ? r/w 6 ? pmrb7 pmrb6 pmrb5 bit : initial value : r/w : port mode register b (pmrb) controls switching of each pin function of port 7. the switching is specified in a unit of bit. pmrb is an 8-bit read/write enable register. when reset, pmrb is initialized to h'0f. bits 7 to 4 ? p77/rpb to p74/rp8 pin switching (pmrb7 to pmrb4): p77/rpb to p74/rp8 set whether the p7n/rpm pin is used as a p7n i/o pin or a rpm pin for the realtime output port. (n = 7 to 4 and m = b, a, 9, or 8) bit n pmrbn description 0 p7n/rpm pin functions as a p7n i/o pin (initial value) 1 p7n/rpm pin functions as a rpm i/o pin note: n = 7 to 4 and m = b, a, 9, and 8 bits 3 to 0 ? reserved bits: reserved bits. when th e bits are read, 1 is always read. the write operation is invalid. port control register 7 (pcr7) 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 pcr74 pcr73 pcr72 pcr71 pcr70 0 w pcr77 w w w pcr76 pcr75 bit : initial value : r/w : port control register 7, together with pmrb, enable the general-purpose input/output of port 7 and controls realtime output in bit units. for details, refer to section 10.8.4. operation. pcr7 is an 8-bit write-only register. when the pcr7 is read, 1 is always read. when reset, pcr7 is initialized to h'00. section 10 i/o port rev.2.00 jan. 15, 2007 page 229 of 1174 rej09b0329-0200 bits 7 to 0 ? p77 to p70 pin i/o switching (pcr77 to pcr70) pmrb pcr7 bitn bitn pmrbn pcr7n description 0 p7n/rpm pin functions as a p7n general input pin (initial value) 0 1 p7n/rpm pin functions as a p7n general output pin 1 * p7n/rpm pin functions as a rpm realtime output pin legend: * don?t care note: n = 7 to 4 and m = b, a, 9, and 8 port data register 7 (pdr7) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 6 0 7 pdr74 pdr73 pdr72 pdr71 pdr70 0 r/w pdr77 r/w r/w r/w pdr76 pdr75 bit : initial value : r/w : port data register 7 (pdr7) stores the data for the pins p77 to p70 of port 7. if pcr7 is 1 (output) when pmrb = 0, the pdr7 va lues are directly read when port 7 is read. accordingly, the pin states are not affected. when pcr7 is 0 (input), the pin states are read if port 7 is read. when pmrb = 1, port 7 pin functions as a realtime output pin. for details, refer to section 10.8.4, operation. pdr7 is an 8-bit read/write enable register. when reset, pdr7 is initialized to h'00. realtime output trigger select register 2 (rtpsr2) 0 1 1 1 ? 2 1 ? 3 1 4 0 r/w 0 r/w 5 6 0 7 rtpsr24 ? ? ? ? 0 r/w rtpsr27 ? ? r/w rtpsr26 rtpsr25 bit : initial value : r/w : realtime output trigger select register (rtpsr2) selects whether to use an external trigger (rptrg pin input) or internal trigger (hsw) for the realtime output trigger input by specifying a unit of bit. for details on internal trigger hsw, refer to section 26.4, hsw (head-switch) timing generator. rtpsr2 is an 8-bit read/write enable register. when reset, rtpsr2 is initialized to h'0f. section 10 i/o port rev.2.00 jan. 15, 2007 page 230 of 1174 rej09b0329-0200 bits 7 to 4 ? rpb to rp8 pin trigger switching (rtpsr27 to rtpsr24) bit7 rtpsr2n description 0 selects external trigger (rptrg pin input) for trigger input (initial value) 1 selects internal trigger (hsw) for trigger input note: n = 7 to 4 realtime output trigger edge selection register (rtpegr) 0 0 1 0 r/w 2 1 3 1 4 1 1 5 6 1 7 ? ? ? ? ? ? ? ? ? ? ? ? rtpegr1 rtpegr0 1 r/w bit : initial value : r/w : the realtime output trigger edge selection register (rtpegr) specifies the sensed edge(s) of external or internal trigger input for realtime output. rtpegr is an 8-bit readable/wr itable register. in a reset, rtpegr is initialized to h'fc. bits 7 to 2 ? reserved: these bits are always read as 1 and cannot be modified. bits 1 and 0 ? realtime output trigger edge select (rtpegr1, rtpegr0): these bits select the sensed edge(s) of external or internal trigger input for realtime output. bit 1 bit 0 rtpegr1 rtpegr0 description 0 disables trigger input (initial value) 0 1 selects trigger input rising edge 1 0 selects trigger input falling edge 1 selects trigger input rising and falling edges section 10 i/o port rev.2.00 jan. 15, 2007 page 231 of 1174 rej09b0329-0200 10.8.3 pin functions this section describes the port 7 pin functions and their selection methods. p77/ppg7/rpb to p74/ppg4/rp8: p77/ppg7/rpb to p74/ppg4/rp8 are switched as shown below according to the pmrbn bit in pmrb and the pcr7n bit in pcr7. pmrbn pmr7n pcr7n pin function output value value returned when pdr7n is read 0 p7n input pin ? p7n pin 0 0 1 p7n output pin pdr7n pdr7n 0 p7n pin 0 1 1 ppgn output pin ppgn pdr7n 1 * 0 rpm output pin hi-z * 1 pdr7n 1 pdrs7n * 1 legend: hi-z: high impedance * don?t care notes: n = 7 to 4, m = b, a, 9, 8 1. when pmrbn = 1 (realtime output pin), the state indicated is that after the pcr7n set value has been transferred to pcrs7n by trigger input. p73/ppg3 to p70/ppg0: p73/ppg3 to p70/ppg0 are switched as shown below according to the pmr7n bit in pmr7 and the pcr7n bit in pcr7. pmr7n pcr7n pin function output value value returned when pdr7n is read 0 p7n input pin ? p7n pin 0 1 p7n output pin pdr7n pdr7n 1 0 ppgn output pin ppgn p7n pin 1 pdr7n note: n = 3 to 0 section 10 i/o port rev.2.00 jan. 15, 2007 page 232 of 1174 rej09b0329-0200 10.8.4 operation port 7 can be used by the pmrb as a realtime output port or an i/o port. port 7 functions as a realtime output port when pmrb = 1 and functions as an i/o port when pmrb = 0. figure 10.3 show the block diagram of port 7. p7/rp rtpegr write rtpsr2 write pmra write pdr7 write pcr7 write pdr7 read rtpegr select select external trigger rptrg internal trigger hsw ck rtpsr2 ck pmrb: port mode register b pcr7: port control register 7 pdr7: port data register 7 pcrs7: port control register slave 7 pdrs7: port data register slave 7 legend: rtpsr2: realtime output trigger select register rtpegr: realtime output trigger edge select register hsw: internal trigger signal rptrg: external trigger pin internal data bus pmrb ck pdr7 ck pcr7 ck pdrs7 ck pcrs7 ck figure 10.3 block diagram of port 7 section 10 i/o port rev.2.00 jan. 15, 2007 page 233 of 1174 rej09b0329-0200 port 7 functions as follows: 1. realtime output port function (pmrb = 1) port function as a realtime output port when pmrb is 1. after a trigger input, the pdr7 data is transferred to pdrs7 and pcr7 data is transferre d to pcrs7. in this case, when pcrs7 is 1, the pdrs7 data of the corresponding bit is output from the rp pin. when pcrs7 is 0, the rp pin of the corresponding bit enters high-impedance state. in other words, the realtime output port function can instantaneously switch the pin output state (high or low) or high-impedance by a trigger input. 2. i/o port function (pmrb = 0) port 7 functions as an i/o port when pmrb is 0. after data is written to pdr7, the same data is written to pdrs7. after data is written to p cr7, the same data is written to pcrs7. since pdr7 and pdrs7, and pcr7 and pcrs7 can be used as one register, the registers can be used as the i/o ports. in other words, if pcr7 is 1, the pdr7 data of the corresponding bit is output from the p7 pin. if pcr is 0, the p7 pin of the corresponding bit is an input pin. if pd7 is read, the pdr7 value is read when pcr7 is 1 and the pin value is read when pcr7 is 0. 10.8.5 pin states table 10.22 shows the port 7 pin states in each operation mode. table 10.22 port 6 pin states pins reset active sleep standby watch subactive subsleep p77/ppg7/rpb to p74/ppg4/rp8 p73/ppg3 to p70/ppg0 high- impedance operation holding high- impedance high- impedance operation holding section 10 i/o port rev.2.00 jan. 15, 2007 page 234 of 1174 rej09b0329-0200 10.9 port 8 10.9.1 overview port 8 is an 8-bit i/o port. table 10.23 shows the port 8 configuration. port 8 consists of pins that are used both as standard-current i/o ports (p87 to p80) and an external ctl signal input (exctl), a pre-amplifier output result signal input (comp), color signal outputs (r, g, and b), a pre-amplifier output selection signal output (h.amp sw), a control signal output for processing color signal (c.rotary), a dpg signal input (dpg), a capstan external sync signal input (excap), an osd character display position output (yb0), an osd character data output (yc0), and an external reference signal input (exttrg). it is switched by port mode register 8 (pmr8), port mode register c (pmrc), and port control register 8 (pcr8). table 10.23 port 8 configuration port function alternative function port 8 p87 (standard i/o port) dpg signal input p86 (standard i/o port) external reference signal input pre-amplifier output result signal input p85 (standard i/o port) color signal output pre-amplifier output selection signal output p84 (standard i/o port) color signal output control signal output for processing color signal p83 (standard i/o port) color signal output p82 (standard i/o port) external ctl signal input capstan external sync signal input p81 (standard i/o port) osd character display position output p80 (standard i/o port) osd character data output section 10 i/o port rev.2.00 jan. 15, 2007 page 235 of 1174 rej09b0329-0200 10.9.2 register configuration table 10.24 shows the port 8 register configuration. table 10.24 port 8 register configuration name abbrev. r/w size initial value address * port mode register 8 pmr8 r/w byte h'00 h'ffdf port mode register c pmrc r/w byte h'c5 h'ffe0 port control register 8 pcr8 w byte h'00 h'ffd8 port data register 8 pdr8 r/w byte h'00 h'ffc8 note: * lower 16 bits of the address. port mode register 8 (pmr8) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 0 5 6 0 7 pmr84 pmr85 pmr86 pmr87 r/w r/w r/w r/w pmr83 pmr82 pmr81 pmr80 0 r/w r/w bit : initial value : r/w : port mode register 8 (pmr8) controls switching of each pin function of port 8. the switching is specified in a unit of bit. pmr8 is an 8-bit read/write enable register. when reset, pmr8 is initialized to h'00. if the exctl, comp, dpg and exttrg input pins are set, the pin level need always be set to the high or low level regardless of the active mode and low power consumption mode. note that the pin level must not reach an intermediate level. bit 7 ? p87/dpg pin switching (pmr87): pmr87 sets whether the p87/dpg pin is used as a p87 i/o pin or a dpg signal input pin. bit 7 pmr87 description 0 p87/dpg pin functions as a p87 i/o pin (drum control signals are input as an overlapped signal) (initial value) 1 p87/dpg pin functions as a dpg input pin (drum control signals are input as separate signals) section 10 i/o port rev.2.00 jan. 15, 2007 page 236 of 1174 rej09b0329-0200 bit 6 ? p86/exttrg pin switching (pmr86): pmr86 sets whether the p86/exttrg pin is used as a p86 i/o pin or an external trigger signal input pin. bit 6 pmr86 description 0 p86/exttrg pin functions as a p86 i/o pin (initial value) 1 p86/exttrg pin functions as a exttrg input pin bit 5 ? p85/comp pin switching (pmr85): pmr85 sets whether the p85/comp pin is used as a p85 i/o pin or a comp input pin of the preamplifier output result signal. bit 5 pmr85 description 0 p85/comp pin functions as a p85 i/o pin (initial value) 1 p85/comp pin functions as a comp input pin bit 4 ? p84/h.amp sw pin switching (pmr84): pmr84 sets whether the p84/h.amp sw pin is used as a p84 i/o pin or h.amp sw pin of the preamplifier output select signal output. bit 4 pmr84 description 0 p84/h.amp sw pin functions as a p84 i/o pin (initial value) 1 p84/h.amp sw pin functions as a h.amp sw output pin bit 3 ? p83/c. rotary pin switching (pmr83): pmr83 sets whether the p83/c. rotary pin is used as a p83 i/o pin or a c.rotary pin of a control signal output for processing color signal. bit 3 pmr83 description 0 p83/c.rotary pin functions as a p83 i/o pin (initial value) 1 p83/c.rotary pin functions as a c.rotary output pin section 10 i/o port rev.2.00 jan. 15, 2007 page 237 of 1174 rej09b0329-0200 bit 2 ? p82/exctl pin switching (pmr82): pmr82 sets whether the p82/exctl pin functions as a p82 i/o pin or a exctl input pin of external ctl signal input. bit 2 pmr82 description 0 p82/exctl pin functions as a p82 i/o pin (initial value) 1 p82/exctl pin functions as a exctl input pin bit 1 ? p81/excap pin switching (pmr81): pmr81 sets whether the p81/excap pin functions as a p81 i/o pin or a excap pin of capstan external synchronous signal input. bit 1 pmr81 description 0 p81/excap pin functions as a p81 i/o pin (initial value) 1 p81/excap pin functions as a excap input pin bit 0 ? p80/yco pin switching (pmr80): pmr80 sets whether the p80/yco pin functions as a p80 i/o pin or a yco pin of osd character data output. bit 0 pmr80 description 0 p80/yco pin functions as a p80 i/o pin (initial value) 1 p80/yco pin functions as a yco output pin port mode register c (pmrc) 0 1 1 0 r/w 2 1 ? 3 0 4 0 r/w 0 r/w 5 6 1 7 pmrc4 pmrc3 ? pmrc1 ? 1 ? ? ? r/w ? ? pmrc5 bit : initial value : r/w : port mode register c (pmrc) controls switching of each pin function of port 8. the switching is specified in a unit of a bit. pmrc is an 8-bit read/write enable register. when reset, pmrc is initialized to h'c5. bits 7, 6, 2, and 0 ? reserved bits: reserved bits. when the bits are read, 1 is always read. the write operation is invalid. section 10 i/o port rev.2.00 jan. 15, 2007 page 238 of 1174 rej09b0329-0200 bit 5 ? p85/b pin switching (pmrc5): pmrc5 sets whether to use the p85/b pin as a p85 i/o pin or a b pin of the osd color signal output. bit 5 pmrc5 description 0 p85/b pin functions as a p85 pin (initial value) 1 p85/b pin functions as a b output pin bit 4 ? p84/g pin switching (pmrc4): pmrc4 sets whether to use the p84/g pin as a p84 i/o pin or a g pin of the osd color signal output. bit 4 pmrc4 description 0 p84/g pin functions as a p84 i/o pin (initial value) 1 p84/g pin functions as a g output pin bit 3 ? p83/r pin switching (pmrc3): pmrc3 sets whether to use the p83/r pin as a p83 i/o pin or a r pin of the osd color signal output. bit 3 pmrc3 description 0 p83/r pin functions as a p83 i/o pin (initial value) 1 p83/r pin functions as a r output pin bit 1 ? p81/ybo pin switching (pmrc1): pmrc1 sets whether to use the p81/ybo pin as a p81 i/o pin or a ybo pin of the osd character display position output. bit7 pmr1 description 0 p81/ybo pin functions as a p81 i/o pin (initial value) 1 p81/ybo pin functions as a ybo output pin section 10 i/o port rev.2.00 jan. 15, 2007 page 239 of 1174 rej09b0329-0200 port control register 8 (pcr8) 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 pcr84 pcr83 pcr82 pcr81 pcr80 0 w pcr87 w w w pcr86 pcr85 bit : initial value : r/w : port control register 8 (pcr8) controls i/o of pins p87 to p80 of port 8. the i/o is specified in a unit of bit. when pcr8 is set to 1, the corresponding p87 to p80 pins become output pins, and when it is set to 0, they become input pins. when the pins are set as general i/o pins, the settings of pcr8 and pdr8 become valid. pcr8 is an 8-bit write-only register. when pcr8 is read, 1 is read. when reset pcr8 is initialized to h'00. bits 7 to 0 ? p87 to p80 pin i/o switching bit n pcr8n description 0 p8n pin functions as an input pin (initial value) 1 p8n pin functions as an output pin note: n = 7 to 0 port data register 8 (pdr8) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 6 0 7 pdr84 pdr83 pdr82 pdr81 pdr80 0 r/w pdr87 r/w r/w r/w pdr86 pdr85 bit : initial value : r/w : port data register 8 (pdr8) stores the data of pins p87 to p80 port 8. when pcr is 1 (output), the pin states are read is port 8 is read. accordingly, the pin states are not affected. when pcr8 is 0 (input), the pin states are read it port 8 is read. pdr8 is an 8-bit read/write enable register. when reset, pdr8 is initialized to h'00. section 10 i/o port rev.2.00 jan. 15, 2007 page 240 of 1174 rej09b0329-0200 10.9.3 pin functions this section describes the port 8 pin functions and their selection methods. p87/dpg: p87/dpg is switched as shown below according to the pmr87 bit in pmr8 and pcr87 bit in pcr8. pmr87 pcr87 pin function 0 p87 input pin 0 1 p87 output pin 1 * dpg input pin legend: * don?t care p86/exttrg: p86/exttrg is switched as shown belo w according to the pm r86 bit in pmr8 and pcr86 bit in pcr8. pmr86 pcr86 pin function 0 p86 input pin 0 1 p86 output pin 1 * exttrg input pin legend: * don?t care p85/comp/b: p85/comp/b is switched as shown belo w according to the pm r85 bit in pmr8, pmrc5 bit in pmrc, and pcr85 bit in pcr8. pmrc5 pmr85 pcr85 pin function 0 p85 input pin 0 0 1 p85 output pin * 1 * comp input pin 1 0 * b output pin legend: * don?t care section 10 i/o port rev.2.00 jan. 15, 2007 page 241 of 1174 rej09b0329-0200 p84/h.amp sw/g: p84/h.amp sw/g is switched as s hown below according to the pmr84 bit in pmr8, pmrc4 bit in pmrc, and pcr84 bit in pcr8. pmrc4 pmr84 pcr84 pin function 0 p84 input pin 0 0 1 p84 output pin * 1 * h.amp sw output pin 1 0 * g output pin legend: * don?t care p83/c.rotary/r: p83/c.rotary/r is switched as show n below according to the pmr83bit in pmr8, pmrc3 bit in pmrc, and pcr83 bit in pcr8. pmrc3 pmr83 pcr83 pin function 0 p83 input pin 0 0 1 p83 output pin * 1 * c.rotary output pin 1 0 * r output pin legend: * don?t care p82/exctl: p82/exctl is switched as shown below according to the pmr82 bit in pmr8 and pcr82 bit in pcr8. pmr82 pcr82 pin function 0 p82 input pin 0 1 p82 output pin 1 * exctl input pin legend: * don?t care section 10 i/o port rev.2.00 jan. 15, 2007 page 242 of 1174 rej09b0329-0200 p81/excap/ybo: p81/excap/ybo is switched as show n below according to the pmr81 bit in pmr8, pmrc1 bit in pmrc, and pcr81 bit in pcr8. pmrc1 pmr81 pcr81 pin function 0 p81 input pin 0 0 1 p81 output pin * 1 * excap output pin 1 0 * ybo output pin legend: * don?t care p80/yco: p80/yco is switched as shown below acco rding to the pmr80 bit in pmr8 and pcr80 bit in pcr pmr80 pcr80 pin function 0 p80 input pin 0 1 p80 output pin 1 * yco output pin legend: * don?t care 10.9.4 pin states table 10.25 shows the port 8 pin states in each operation mode. table 10.25 port 8 pin states pins reset active sleep standby watch subactive subsleep p87/dpg p86/exttrg p85/comp/b p84/h.amp sw/g p83/c.rotary/r p82/exctl p81/excap/yb0 p80/yco high- impedance operation holding high- impedance high- impedance operation holding notes: 1. if the exctl, comp, dpg, and exttrg input pins are set, the pin level need always be set to the high or low level regardless of the active mode and low power consumption mode. note that the pin level must not reach an intermediate level. 2. as the dpg always functions, a high or low pin level must be input to the multiplexed pins regardless of whether active mode or power-down mode is in effect. section 11 timer a rev.2.00 jan. 15, 2007 page 243 of 1174 rej09b0329-0200 section 11 timer a 11.1 overview timer a is an 8-bit interval timer. it can be used as a clock timer when connected to a 32.768-khz crystal oscillator. 11.1.1 features features of timer a are as follows: ? choices of eight different types of internal clocks ( /16384, /8192, /4096, /1024, /512, /256, /64 and /16) are available for your selection. ? four different overflowing cycles (1 s, 0.5 s, 0.25 s, and 0.03125 s) are selectable as a clock timer. (when using a 32.768-khz crystal oscillator.) ? requests for interrupt will be output when the counter overflows. section 11 timer a rev.2.00 jan. 15, 2007 page 244 of 1174 rej09b0329-0200 11.1.2 block diagram figure 11.1 shows a block diagram of timer a. le g end: tma 32-khz crystal oscillator overflowin g of the interval timer system clock w w/128 /16384, /8192, /4096, /1024, /512, /256, /64, /16 tca : timer mode re g ister a : timer counter a note: * selectable only when the prescaler w output ( w/128) is workin g as the input clock to the tca. prescaler s (pss) interruptin g circuit prescaler unit prescaler w (psw) tca 1/4 tma interrupt requests internal data bus 8 * 64 * 128 * 256 * figure 11.1 block diagram of timer a 11.1.3 register configuration table 11.1 shows the register configuration of timer a. table 11.1 register configuration name abbrev. r/w size initial value address * timer mode register a tma r/w byte h'30 h'ffba timer counter a tca r byte h'00 h'ffbb note: * lower 16 bits of the address. section 11 timer a rev.2.00 jan. 15, 2007 page 245 of 1174 rej09b0329-0200 11.2 register descriptions 11.2.1 timer mode register a (tma) 0 0 1 0 r/w 2 0 r/w 3 0 4 1 5 ? ? ? ? 1 6 0 7 r/w r/w r/w tmaie 0 r/(w) * tmaov tma3 tma2 tma1 tma0 note: * only 0 can be written to clear the fla g . bit : initial value : r/w : the timer mode register a (tma) works to control the interrupts of timer a and to select the input clock. tma is an 8-bit read/write register. when reset, the tma will be initialized to h'30. bit 7 ? timer a overflow flag (tmaov): this is a status flag indi cating the fact that the tca is overflowing (h'ff h'00). bit 7 tmaov description 0 [clearing condition] (initial value) when 0 is written to the tmaov flag after reading the tmaov flag under the status where tmaov = 1 1 [setting condition] when the tca overflows bit 6 ? enabling interrupt of the timer a (tmaie): this bit works to permit/prohibit occurrence of interrupt of the timer a (tmai) when the tca overflows and when the tmaov of the tma is set to 1. bit 6 tmaie description 0 prohibits occurrence of interrupt of the timer a (tmai) (initial value) 1 permits occurrence of interrupt of the timer a (tmai) bits 5 and 4 ? reserved: these bits cannot be modified and are always read as 1. section 11 timer a rev.2.00 jan. 15, 2007 page 246 of 1174 rej09b0329-0200 bit 3 ? selection of the clock so urce and prescaler (tma3): this bit works to select the pss or psw as the clock source for the timer a. bit 3 tma3 description 0 selects the pss as the clock source for the timer a (initial value) 1 selects the psw as the clock source for the timer a bits 2 to 0 ? clock selection (tma2 to tma0): these bits work to select the clock to input to the tca. in combination with the tma3 bit, the choices are as follows: bit 3 bit 2 bit 1 bit 0 tma3 tma2 tma1 tma0 prescaler division ratio (interval timer) or overflow cycle (time base) operation mode 0 pss, /16384 (initial value) 0 1 pss, /8192 0 pss, /4096 0 1 1 pss, /1024 0 pss, /512 0 1 pss, /256 0 pss, /64 0 1 1 1 pss, /16 interval timer mode 0 1 s 0 1 0.5 s 0 0.25 s 0 1 1 0.03125 s 0 0 1 0 1 1 1 1 works to clear the psw and tca to h'00 clock time base mode note: = f osc section 11 timer a rev.2.00 jan. 15, 2007 page 247 of 1174 rej09b0329-0200 11.2.2 timer counter a (tca) 0 0 1 0 r 2 0 r 3 0 4 5 6 7 r r tca3 0 r tca4 0 r tca5 0 r tca6 0 r tca7 tca2 tca1 tca0 bit : initial value : r/w : the timer counter a (tca) is an 8- bit up-counter that counts up on inputs from the internal clock. the inputting clock can be selected by tma3 to tma0 bits of the tma when the tca overflows, the tmaov bit of the tma is set to 1. the tca can be cleared by setting the tma3 and tma2 bits of the tma to 11. the tca is always readable. when reset, the tca will be initialized into h'00. 11.2.3 module stop control register (mstpcr) 7 1 mstp15 r/w mstpcrh 6 1 mstp14 r/w 5 1 mstp13 r/w 4 1 mstp12 r/w 3 1 mstp11 r/w 2 1 mstp10 r/w 1 1 mstp9 r/w 0 1 mstp8 r/w 7 1 mstp7 r/w 6 1 mstp6 r/w 5 1 mstp5 r/w 4 1 mstp4 r/w 3 1 mstp3 r/w 2 1 mstp2 r/w 1 1 mstp1 r/w 0 1 mstp0 r/w mstpcrl initial value : r/w : bit : the mstpcr are 8-bit read/write twin registers which work to control the module stop mode. when the mstp15 bit is set to 1, the timer a stops its operation at the ending point of the bus cycle to shift to the module stop mode. for more information, see section 4.5, module stop mode. when reset, the mstpcr will be initialized into h'ffff. bit 7 ? module stop (mstp15): this bit works to designate the module stop mode for the timer a. mstpcrh bit 7 mstp15 description 0 cancels the module stop mode of the timer a 1 sets the module stop mode of the timer a (initial value) section 11 timer a rev.2.00 jan. 15, 2007 page 248 of 1174 rej09b0329-0200 11.3 operation timer a is an 8-bit interval timer. it can be used as a clock timer when connected to a 32.768-khz crystal oscillator. 11.3.1 operation as the interval timer when the tma3 bit of the tma is cleared to 0, timer a works as an 8-bit interval timer. after reset, the tca is cleared to h'00 and as the tma3 bit is cleared to 0, the timer a continues counting up as the interval counter w ithout interrupts right after resetting. as the operation clock for timer a, selection can be made from eight different types of internal clocks being output from the pss by the tma2 to tma0 bits of the tma. when the clock signal is input after the reading of the tca reaches h'ff, timer a overflows and the tmaov bit of the tma will be set to 1. an interrupt occurs when the tmaie bit of the tma is 1. when overflowing occurs, the reading of the tca returns to h'00 before resuming counting up. consequently, it works as the interval timer to produce overflow outputs periodically at every 256 input clocks. 11.3.2 operation as clock timer when the tma3 bit of the tma is set to 1, timer a works as a time base for the clock. as the overflow cycles for timer a, selection can be made from four different types by counting the clock being output from the psw by the tma1 bit and tma0 bit of the tma. 11.3.3 initializing the counts when the tma3 and tma2 bits are set to 11, the psw and tca will be cleared to h'00 to come to a stop. at this state, writing 10 to the tma3 bit and tma2 bit makes timer a start counting from h'00 in the time base mode for clocks. after clearing the psw and tca using the tma3 and tma2 bits, writing 00 or 01 to the tma3 bit and tma2 bit to make timer a start counting from h'00 in the interval timer mode. however, the period to the first count is not constant, since the pss is not cleared. section 12 timer b rev.2.00 jan. 15, 2007 page 249 of 1174 rej09b0329-0200 section 12 timer b 12.1 overview timer b is an 8-bit up-counter. timer b is equipped with two different types of functions namely, the interval function and the auto reloading function. 12.1.1 features ? seven different types of internal clocks ( /16384, /4096, /1024, /512, /128, /32, and /8) or an of external clock can be selected. ? when the counter overflows, a interrupt request will be issued. 12.1.2 block diagram figure 12.1 shows a block diagram of timer b. legend: tmb /16384 /4096 /1024 /512 /128 /32 /8 tmbi tcb : timer mode register b : timer counter b tlb tmbi : timer re-loading register b : event input terminal of the timer b re-loading clock sources overflowing timer b interrupt requests internal data bus tcb tmb tlb interrupting circuit figure 12.1 block diagram of timer b section 12 timer b rev.2.00 jan. 15, 2007 page 250 of 1174 rej09b0329-0200 12.1.3 pin configuration table 12.1 shows the pin configuration of timer b. table 12.1 pin configuration name abbrev. i/o function event inputs to timer b tmbi input event input pin for inputs to the tcb 12.1.4 register configuration table 12.2 shows the register configuration of timer b. the tcb and tlb are being allocated to the same address. reading or writing determines the accessing register. table 12.2 register configuration name abbrev. r/w size initial value address * timer mode register b tmb r/w byte h'18 h'd110 timer counter b tcb r byte h'00 h'd111 timer load register b tlb w byte h'00 h'd111 port mode register a pmra r/w byte h'3f h'ffd9 note: * lower 16 bits of the address. section 12 timer b rev.2.00 jan. 15, 2007 page 251 of 1174 rej09b0329-0200 12.2 register descriptions 12.2.1 timer mode register b (tmb) 0 0 1 0 r/w 2 0 r/w 3 1 4 ? ? ? ? 1 5 0 6 0 7 r/w r/w tmbie r/(w) * tmbif 0 r/w tmb17 tmb12 tmb11 tmb10 note: * only 0 can be written to clear the flag. bit : initial value : r/w : the tmb is an 8-bit read/write register which works to control the interrupts, to select the auto reloading function and to select the input clock. when reset, the tmb is initialized to h'18. bit 7 ? selecting the auto reloading function (tmb17): this bit works to select the auto reloading function of the timer b. bit 7 tmb17 description 0 selects the interval function (initial value) 1 selects the auto reloading function bit 6 ? interrupt requesting flag for the timer b (tmbif): this is an interrupt requesting flag for the timer b. it indicates the fact that the tcb is overflowing. bit 6 tmbif description 0 [clearing condition] (initial value) when 0 is written after reading 1 1 [setting condition] when the tcb overflows section 12 timer b rev.2.00 jan. 15, 2007 page 252 of 1174 rej09b0329-0200 bit 5 ? enabling interrupt of the timer b (tmbie): this bit works to permit/prohibit occurrence of interrupt of timer b when the tcb overflows and when the tmbif is set to 1. bit 5 tmbie description 0 prohibits interrupt of timer b (initial value) 1 permits interrupt of timer b bits 4 and 3 ? reserved: these bits cannot be modified and are always read as 1. bits 2 to 0 ? clock selection (tmb12 to tmb10): these bits work to select the clock to input to the tcb. selection of the rising edge or the falling edge is workable with the external event inputs. bit 2 bit 1 bit 0 tmb12 tmb11 tmb10 descriptions 0 0 0 internal clock: counts at /16384 (initial value) 0 0 1 internal clock: counts at /4096 0 1 0 internal clock: counts at /1024 0 1 1 internal clock: counts at /512 1 0 0 internal clock: counts at /128 1 0 1 internal clock: counts at /32 1 1 0 internal clock: counts at /8 1 1 1 counts at the rising edge and the falling edge of external event inputs (tmbi) * note: * the edge selection for the external event inputs is made by setting the pmra6 of the port mode register a (pmra). see section 12.2.4, port mode register a (pmra). section 12 timer b rev.2.00 jan. 15, 2007 page 253 of 1174 rej09b0329-0200 12.2.2 timer counter b (tcb) 0 0 1 0 r 2 0 r 3 4 5 0 6 0 7 r r tcb15 0 r tcb14 0 r tcb13 r tcb16 0 r tcb17 tcb12 tcb11 tcb10 bit : initial value : r/w : the tcb is an 8-bit readable register which works to count up by the internal clock inputs and external event inputs. the input clock can be selected by the tmb12 to tmb10 of the tmb. when the tcb overflows (h'ff h'00 or h'ff tlb setting), a interrupt request of the timer b will be issued. when reset, the tcb is initialized to h'00. 12.2.3 timer load register b (tlb) 0 0 1 0 w 2 0 w 3 4 5 0 6 0 7 w w tlb15 0 w tlb14 0 w tlb13 w tlb16 0 w tlb17 tlb12 tlb11 tlb10 bit : initial value : r/w : the tlb is an 8-bit write only register which works to set the reloading value of the tcb. when the reloading value is set to the tlb, the value will be simultaneously loaded to the tcb and the tcb starts counting up from the set value. also, during an auto reloading operation, when the tcb overflows, the value of the tlb will be loaded to the tcb. consequently, the overflowing cycle can be set within the range of 1 to 256 input clocks. when reset, the tlb is initialized to h'00. section 12 timer b rev.2.00 jan. 15, 2007 page 254 of 1174 rej09b0329-0200 12.2.4 port mode register a (pmra) 0 1 1 ? 2 1 ? 3 4 1 5 6 7 ? ? pmra6 pmra7 ? ? ? ? r/w r/w ? 1 ? ?? 1 1 0 0 bit : initial value : r/w : the port mode register a (pmra) works to changeover the pin functions of the port 6 and to designate the edge sense of the event inputs of timer b (tmbi). the pmra is an 8-bit read/write register. when reset, the pmra will be initialized to h'3f. see section 10.7, port 6 for other information than bit 6. bit 6 ? selecting the edges of the event inputs to the timer b (pmra6): this bit works to select the input edge sense of the tmbi pins. bit 6 pmra6 description 0 detects the falling edge of the event inputs to the timer b (initial value) 1 detects the rising edge of the event inputs to the timer b section 12 timer b rev.2.00 jan. 15, 2007 page 255 of 1174 rej09b0329-0200 12.2.5 module stop control register (mstpcr) 7 1 mstp15 r/w mstpcrh 6 1 mstp14 r/w 5 1 mstp13 r/w 4 1 mstp12 r/w 3 1 mstp11 r/w 2 1 mstp10 r/w 1 1 mstp9 r/w 0 1 mstp8 r/w 7 1 mstp7 r/w 6 1 mstp6 r/w 5 1 mstp5 r/w 4 1 mstp4 r/w 3 1 mstp3 r/w 2 1 mstp2 r/w 1 1 mstp1 r/w 0 1 mstp0 r/w mstpcrl initial value : r/w : bit : the mstpcr are 8-bit read/write twin registers which work to control the module stop mode. when the mstp14 bit is set to 1, the timer b stops its operation at the ending point of the bus cycle to shift to the module stop mode. for more information, see section 4.5, module stop mode. when reset, the mstpcr is initialized to h'ffff. bit 6 ? module stop (mstp14): this bit works to designate the module stop mode for the timer b. mstpcrh bit 6 mstp14 description 0 cancels the module stop mode of the timer b 1 sets the module stop mode of the timer b (initial value) section 12 timer b rev.2.00 jan. 15, 2007 page 256 of 1174 rej09b0329-0200 12.3 operation 12.3.1 operation as the interval timer when the tmb17 bit of the tmb is set to 0, timer b works as an 8-bit interval timer. when reset, since the tcb is cl eared to h'00 and as the tmb17 bit is cleared to 0, timer b continues counting up as the interval timer without interrupts right after resetting. as the clock source for timer b, selection can be made from seven different types of internal clocks being output from the prescaler unit by the tmb12 to tmb10 bits of the tmb or an external clock through the tmbi input pin can be chosen instead. when the clock signal is input after the reading of the tcb reaches h'ff, timer b overflows and the tmbif bit of the tmb will be set to 1. at this time, when the tmbie bit of the tmb is 1, interrupt occurs. when overflowing occurs, the reading of the tcb returns to h'00 before resuming counting up. when a value is set to the tlb while the interval timer is in operation, the value which has been set to the tlb will be loaded to the tcb simultaneously. 12.3.2 operation as the auto reload timer when the tmb17 of the tmb is set to 1, the timer b works as an 8-bit auto reload timer. when a reload value is set in the tlb, the value is loaded onto the tcb at the same time, and the tcb starts counting up from the value. when the clock signal is input after the readi ng of the tcb reaches h'ff, timer b overflows and the tlb value is loaded onto the tcb, then the tcb continues counting up from the loaded value. accordingly, overflow interval can be set within the range of 1 to 256 clocks depending on the tlb value. clock source and interrupts in the auto reload operation are the sa me as those in the interval operation. when the tlb value is re-set while the auto reload timer is in operation, the value which has been set to the tlb will be loaded onto the tcb simultaneously. 12.3.3 event counter timer b works as an event counter using the tmbi pin as the event input pin. when the tmb12 to tmb10 are set to 111, the external event w ill be selected as the clock source and the tcb counts up at the leading edge or the tr ailing edge of the tmbi pin inputs. section 13 timer j rev.2.00 jan. 15, 2007 page 257 of 1174 rej09b0329-0200 section 13 timer j 13.1 overview timer j consists of twin counters. it carries different operation modes such as reloading and event counting. 13.1.1 features timer j consists of an 8-bit reloading timer and an 8-bit/16-bit selectable reloading timer. it has various functions as listed below. the two timers can be used separately, or they can be connected together to operate as a single timer. ? reloading timers ? event counters ? remote-controlled transmissions ? takeup/supply reel pulse division 13.1.2 block diagram figure 13.1 is a block diagram of timer j. timer j consists of two reload timers namely, tmj-1 and tmj-2. section 13 timer j rev.2.00 jan. 15, 2007 page 258 of 1174 rej09b0329-0200 legend: tcj note: * at the low level under the timer mode. tlj : timer counter j : timer load register j tck tlk : timer counter k : timer load register k tmo remoout : tmj-1 timer output : tmj-2 toggle output (remote controller transmission data) buzz reloading register (burst/space width register ps22, 21,20 exn : buzzer output tgl : tmj-2 toggle flag ps22, 21,20 st : tmj-2 input clock selection : starting the remote controlled operation ps11,10 : tmj-1 input clock selection 8/16 t/r exn : 8-bit/16-bit operation changeover : timer output/remote controller output changeover : expansion function switching internal data bus edge detection toggle t/r down-counter (8/16-bit) buzz output control monitor output control toggle reloading register 8/16 st ps11,10 down- counter (8-bit) under flow under- flow tcj tmj-1 tmj-2 tck pb/rec-ctl dvctl tca7 /4096 /8192 tgl remoout tmo tmo buzz clock sources irq2 /64 /128 /1024 /2048 /16384 clock sources irq1 /4 /256 /512 * synchronization tlj reloading reloading tlk tmj-1 interrupting circuit interrupt request by the tmj1i interrupt request by the tmj2i tmj-2 interrupting circuit figure 13.1 block diagram of timer j section 13 timer j rev.2.00 jan. 15, 2007 page 259 of 1174 rej09b0329-0200 13.1.3 pin configuration table 13.1 shows the pin configuration of timer j. table 13.1 pin configuration name abbrev. i/o function event input pin irq1 input event inputs to the tmj-1 event input pin irq2 input event inputs to the tmj-2 13.1.4 register configuration table 13.2 shows the register configuration of timer j. the tcj and tlj or the tck and tlk are being allocated to the same address respectively. reading or writing determines the accessing register. table 13.2 register configuration name abbrev. r/w size initial value address * 2 timer mode register j tmj r/w byte h'00 h'd13a timer j control register tmjc r/w byte h'09 h'd13b timer j status register tmjs r/(w) * 1 byte h'3f h'd13c timer counter j tcj r byte h'ff h'd139 timer counter k tck r byte h'ff h'd138 timer load register j tlj w byte h'ff h'd139 timer load register k tlk w byte h'ff h'd138 notes: 1. only 0 can be written to clear the flag. 2. lower 16 bits of the address. section 13 timer j rev.2.00 jan. 15, 2007 page 260 of 1174 rej09b0329-0200 13.2 register descriptions 13.2.1 timer mode register j (tmj) 0 0 1 0 r 2 0 r/w 3 0 4 0 r/w 5 0 6 0 7 r/w r/w r/w st r/w ps10 0 r/w ps11 8/16 ps21 ps20 tgl t/r bit : initial value : r/w : the timer mode register j (tmj) works to select the inputting clock for the tmj-1 and tmj-2 and to set the operation mode. the tmj is an 8-bit register and bit 1 is for read only. all the remaining bits are applicable to read/write. when reset, the tmj is initialized to h'00. under all other modes than the remote controlling mode, writing into the tmj works to initialize the counters (tcj and tck) to h'ff. bits 7 and 6 ? selecting the inputting clock to the tmj-1 (ps11, ps10): these bits work to select the clock to input to the tmj-1. when the external clock is selected, the counted edge (rising or falling) can also be selected. bit 7 bit 6 ps11 ps10 description 0 counting by the pss, /512 (initial value) 0 1 counting by the pss, /256 1 0 counting by the pss, /4 1 counting at the rising edge or the falling edge of the external clock inputs ( irq1 ) * note: * the edge selection for the external clock inputs is made by setting the irq edge select register (iegr). see section 6.2.4, irq edge select register (iegr) for more information. when using an external clock under the remote controlling mode, set the opposite edge with the irq1 and the irq2 when using an external clock under the remote controlling mode. (when irq1 falling, select irq2 rising and when irq1 rising, select irq2 falling) section 13 timer j rev.2.00 jan. 15, 2007 page 261 of 1174 rej09b0329-0200 bit 5 ? starting the remote controlled operation (st): this bit works to start the remote controlled operations. when this bit is set to 1, clock signal is supplied to the tmj-1 to start signal transmissions. when this bit is cleared to 0, clock supply stops to discontinue the operation. the st bit will be valid under the remote controlling mode, namely, when bit 0 (t/r bit) is 1 and bit 4 (8/16 bit) is 0. under other modes than the remote controlling mode, it will be fixed to 0. when a shift to the low power consumption mode is made during remote controlled operation, the st bit will be cleared to 0. when resuming operation after returning to the active mode, write 1. bit 5 st description 0 works to stop clock signal supply to the tmj-1 under the remote controlling mode (initial value) 1 works to supply clock signal to the tmj-1 under the remote controlling mode bit 4 ? switching over between 8-bit/16-bit operations (8/16): this bit works to choose if using timer j as two units of 8-bit timer/counter or if using it as a single unit of 16-bit timer/counter. even under 16-bit operations, tmj1i interrupt requests from the tmj-1 will be valid. bit 4 8/16 description 0 makes the tmj-1 and tmj-2 operate separately (initial value) 1 makes the tmj-1 and tmj-2 operate altogether as 16-bit timer/counter bits 3 and 2 ? selecting the inputting clock for the tmj-2 (ps21, ps20): these bits, together with the ps22 bit in the timer j control register (tmjc), work to select the clock for the tmj-2. when the external clock is selected, the counted edge (rising or falling) can also be selected. for details, refer to section 13.2.2, timer j control register (tmjc). bit 1 ? tmj-2 toggle flag (tgl): this flag indicates the toggled status of the underflowing with the tmj-2. reading only is workable. it will be cleared to 0 under the low power consumption mode. bit 1 tgl description 0 the toggle output of the tmj-2 is 0 (initial value) 1 the toggle output of the tmj-2 is 1 section 13 timer j rev.2.00 jan. 15, 2007 page 262 of 1174 rej09b0329-0200 bit 0 ? switching over between timer output/remote controlling output (t/r): this bit works to select if using the timer outputs from the tmj-1 as the output signal through the tmo pin or if using the toggle outputs (remote controlled transmission data) from the tmj-2 as the output signal through the tmo pin. bit 0 t/r description 0 timer outputs from the tmj-1 (initial value) 1 toggle outputs from the tmj-2 (remote controlled transmission data) selecting the operation mode the operating mode of timer j is determined by bit 3 (exn) of the timer j control register (tmjc) and bits 4 (8/16) and 0 (t/r) of the timer mode register j (tmj). tmjc tmj bit 3 bit 4 bit 0 exn 8/16 t/r description 0 0 0 8-bit timer + 16-bit timer 1 remote-controlling mode (tmj-2 works as a 16-bit timer) 1 * 24-bit timer 1 0 0 two 8-bit timers (initial value) 1 remote-controlling mode (tmj-2 works as an 8-bit timer) 1 * 16-bit timer legend: * don?t care writing to the tmj in timer mode initializes the counters (tcj and tck) (h'ff). consequently, write to the reloading registers (tlj an tlk) after finishing settings with the tmj. under the remote controlling mode, although the tlj and the tlk will not be initialized even when writing is made into the tmj, follow the sequence listed below when starting a remote controlling operation: 1. make setting to the remote controlling mode with the tmj. 2. write the data into the tlj and tlk. 3. start the remote controlled operation by use of the tmj. (st bit = 1). even under 16-bit operations, tmj1i interrupt requests from the tmj-1 will be valid. section 13 timer j rev.2.00 jan. 15, 2007 page 263 of 1174 rej09b0329-0200 13.2.2 timer j control register (tmjc) 0 1 0 2 0 r/w 3 ps22 exn r/w r/w 4 0 r/w 5 0 6 0 7 r/w r/w mon1 r/w buzz0 0 r/w buzz1 mon0 tmj2ie tmj1ie 11 bit : initial value : r/w : the timer j control register (tmjc) works to se lect the buzzer output frequency and to control permission/prohibition of interrupts. the tmjc is an 8-bit read/write register. when reset, the tmjc is initialized to h'09. bits 7 and 6 ? selecting the buzzer output (buzz1, buzz0): these bits work to select if using the buzzer outputs as the out put signal through the buzz pin or if using the monitor signals as the output signal through the buzz pin. when setting is made to the monitor signals, choose the monitor signal using the mon1 bit and mon0 bit. bit 7 bit 6 buzz1 buzz0 description frequency when = 10 mhz 0 /4096 (initial value) 2.44 khz 0 1 /8192 1.22 khz 1 0 works to output monitor signals 1 works to output buzz signals from timer j section 13 timer j rev.2.00 jan. 15, 2007 page 264 of 1174 rej09b0329-0200 bits 5 and 4 ? selecting the monitor signals (mon1, mon0): these bits work to select the type of signals being output through the buzz pin for monitoring purpose. these settings are valid only when the buzz1 and buzz0 bits are being set to 10. when pb-ctl or rec-ctl is chosen, signal duties will be output as they are. in case of dvctl signals, signals from the ctl dividing circuit will be toggled before being output. signal waveforms divided by the ctl dividing circuit into n-divisions will further be divided into halves. (namely, 2n divisions, 50% duty waveform). in case of tca7, bit 7 of the counter of the timer a will be output. (50% duty) when prescaler w is being used with th e timer a, 1 hz outputs are available. bit 5 bit 4 mon1 mon0 description 0 pb or rec-ctl (initial value) 0 1 dvctl 1 * outputs tca7 legend: * don?t care bit 3 ? expansion function control bit (exn): this bit enables or disables the expansion function of tmj-2. when the expansion function is enabled, tmj-2 works as a 16-bit counter, and further input clock sources and types can be selected. bit 3 exn description 0 enables the tmj-2 expansion function 1 disables the tmj-2 expansion function (initial value bit 2 ? enabling interrupt of the tmj2i (tmj2ie): this bit works to permit/prohibit occurrence of tmj2i interrupt of the tmjs in 1-set of the tmj2i. bit 2 tmj2ie description 0 prohibits occurrence of tmj2i interrupt (initial value) 1 permits occurrence of tmj2i interrupt section 13 timer j rev.2.00 jan. 15, 2007 page 265 of 1174 rej09b0329-0200 bit 1 ? enabling interrupt of the tmj1i (tmj1ie): this bit works to permit/prohibit occurrence of tmj1i interrupt of the tmjs in 1-set of the tmj1i. bit 1 tmj1ie description 0 prohibits occurrence of tmj1i interrupt (initial value) 1 permits occurrence of tmj1i interrupt bit 0 ? tmj-2 input clock selection (ps22): this bit, together with the ps21 and ps20 bits of the timer mode register j (tmj), selects the tmj-2 input clock source. tmjc tmj bit 3 bit 0 bit 3 bit 2 exn ps22 ps21 ps20 description 0 1 0 0 pss; count at /128 1 pss; count at /64 1 0 count at tmj-1 underflow 1 external clock (irq2); count at rising or falling edge * 1 0 * * reserved 1 1 0 0 pss; count at /16384 (initial value) 1 pss; count at /2048 1 0 count at tmj-1 underflow 1 external clock (irq2); count at rising or falling edge * 1 0 0 0 pss; count at /1024 1 pss; count at /1024 1 0 count at tmj-1 underflow 1 external clock (irq2); count at rising or falling edge * 1 legend: * don?t care note: 1. the external clock edge can be selected by the irq edge select register (iegr). for details, refer to section 6.2.4, irq edge select registers (iegr). section 13 timer j rev.2.00 jan. 15, 2007 page 266 of 1174 rej09b0329-0200 13.2.3 timer j status register (tmjs) 0 1 2 3 4 5 ? ? ? ? ? ? ? ? ? ? ? ? 6 0 7 r/(w) * tmj1i 0 r/(w) * tmj2i 11 1 1 11 note: * only 0 can be written to clear the flag. bit : initial value : r/w : the timer j status register (tmjs) works to indi cate issuance of the interrupt request of timer j. the tmjs is an 8-bit read/write register. when reset, the tmjs is initialized to h'3f. bit 7 ? tmj2i interrupt requesting flag (tmj2i): this is the tmj2i interrupt requesting flag. this flag is set out when the tmj-2 underflows. bit 7 tmj2i description 0 [clearing condition] (initial value) when 0 is written after reading 1 1 [setting condition] when the tmj-2 underflows bit 6 ? tmj1i interrupt requesting flag (tmj1i): this is the tmj1i interrupt requesting flag. this flag is set out when the tmj-1 underflows. tmj1i interrupt requests will also be made under a 16-bit operation. bit 6 tmj1i description 0 [clearing condition] (initial value) when 0 is written after reading 1 1 [setting condition] when the tmj-1 underflows bits 5 to 0 ? reserved: these bits cannot be modified and are always read as 1. section 13 timer j rev.2.00 jan. 15, 2007 page 267 of 1174 rej09b0329-0200 13.2.4 timer counter j (tcj) 0 1 1 1 r 2 1 r 3 1 4 1 r 5 1 6 1 7 r r r tdr15 r tdr16 1 r tdr17 tdr14 tdr13 tdr12 tdr11 tdr10 bit : initial value : r/w : the timer counter j (tcj) is an 8-bit readable down-counter which works to count down by the internal clock inputs or external clock inputs. the in putting clock can be se lected by the ps11 and ps10 bits of the tmj. tcj values can be readout always. nonetheless, when the exn bit in tmjc and the 8/16 bit in tmj are both set to 1, (means when setting is made to 16-bit operation), reading is possible under the word command only. at this time, the tck of the tmj-2 can be read by the upper 8 bits and the tcj can be read by the lower 8 bits. when the exn bit in tmjc is 0, tcj can be read only in byte units. when the tcj underflows (h'00 reloading value), regardless of the operation mode setting of the 8/16 bit, the tmj1i bit of the tmjs will be set to 1 bit. the tcj and tlj are being allocated to the same address. when reset, the tcj is initialized to h'ff. 13.2.5 timer counter k (tck) 0 1 1 1 r 2 1 r 3 1 4 1 r 5 1 6 1 7 r r r tdr25 r tdr26 1 r tdr27 tdr24 tdr23 tdr22 tdr21 tdr20 bit : initial value : r/w : the timer counter k (tck) is an 8-bit or a 16-bit readable down-counter which works to count down by the internal clock inputs or external clock inputs. the inputting clock can be selected by the exn and ps22 bits of the tmjc, and the ps21 and ps20 bits of the tmj. tck values can be readout always. nonetheless, when the exn bit in tmjc and the 8/16 bit in tmj are both set to 1, (means when setting is made to 16-bit operation), reading is possible under the word command only. at this time, the tck can be read by the upper 8 bits and the tcj of the tmj-1 can be read by the lower 8 bits. when the exn bit in tmjc is 0, tck works as a 16-bit counter and can be read only in word units. when the tck underflows (h'00 reloading value), the tmj2i bit of the tmjs will be set to 1. the tck and tlk are being allocated to the same address. when reset, the tck is initialized to h'ff. section 13 timer j rev.2.00 jan. 15, 2007 page 268 of 1174 rej09b0329-0200 13.2.6 timer load register j (tlj) 0 1 1 1 w 2 1 w 3 1 4 1 w 5 1 6 1 7 w w w tlr15 w tlr16 1 w tlr17 tlr14 tlr13 tlr12 tlr11 tlr10 bit : initial value : r/w : the timer load register j (tlj) is an 8-bit write only register which works to set the reloading value of the tcj. when the reloading value is set to the tlj, the value will be simultaneously loaded to the tcj and the tcj starts counting down from the set value. also, during an auto reloading operation, when the tcj underflows, the value of the tlj will be loaded to the tcj. consequently, the underflowing cycle can be set within the range of 1 to 256 input clocks. nonetheless, when the exn bit in tmjc and the 8/16 bit in tmj are both set to 1, (means when setting is made to 16-bit operation), writing is possible under the word command only. at this time, the upper 8 bits can be written into the tlk of the tmj-2 and the lower 8 bits can be written into the tlj. when the exn bit in tmjc is 0, tlj can be written to only in byte units; an 8-bit reload value is written to tlj. the tlj and tcj are being allocated to the same address. when reset, the tlj is initialized to h'ff. 13.2.7 timer load register k (tlk) 0 1 1 1 w 2 1 w 3 1 4 1 w 5 1 6 1 7 w w w tlr25 w tlr26 1 w tlr27 tlr24 tlr23 tlr22 tlr21 tlr20 bit : initial value : r/w : the timer load register k (tlk) is an 8-bit or a 16-bit write only register which works to set the reloading value of the tck. when the reloading value is set to the tlk, the value will be simultaneously loaded to the tck and the tck starts counting down from the set value. also, during an auto reloading operation, when the tck underflows, the value of the tlk w ill be loaded to the tc k. consequently, the underflowing cycle can be set within the range of 1 to 256 input clocks. nonetheless, when the exn bit in tmjc and the 8/16 bit in tmj are both set to 1, (means when setting is made to 16-bit operation), writing is possible under the word command only. at this time, the upper 8 bits can be written into the tlk and the lower 8 bits can be written into the tlj of the tmj-1. when the exn bit in tmjc is 0, tlk can be written to only in word units; a 16-bit reload value is written to tlk. the tlk and tck are being allocated to the same address. when reset, the tlk is initialized to h'ff. section 13 timer j rev.2.00 jan. 15, 2007 page 269 of 1174 rej09b0329-0200 13.2.8 module stop control register (mstpcr) 7 1 mstp15 r/w mstpcrh 6 1 mstp14 r/w 5 1 mstp13 r/w 4 1 mstp12 r/w 3 1 mstp11 r/w 2 1 mstp10 r/w 1 1 mstp9 r/w 0 1 mstp8 r/w 7 1 mstp7 r/w 6 1 mstp6 r/w 5 1 mstp5 r/w 4 1 mstp4 r/w 3 1 mstp3 r/w 2 1 mstp2 r/w 1 1 mstp1 r/w 0 1 mstp0 r/w mstpcrl initial value : r/w : bit : the mstpcr are 8-bit read/write twin registers which work to control the module stop mode. when the mstp13 bit is set to 1, timer j stops its operation at the ending point of the bus cycle to shift to the module stop mode. for more information, see section 4.5, module stop mode. when reset, the mstpcr is initialized to h'ffff. bit 5 ? module stop (mstp13): this bit works to designate the module stop mode for the timer j. mstpcrh bit 5 mstp13 description 0 cancels the module stop mode of timer j 1 sets the module stop mode of timer j (initial value) section 13 timer j rev.2.00 jan. 15, 2007 page 270 of 1174 rej09b0329-0200 13.3 operation 13.3.1 8-bit reload timer (tmj-1) the tmj-1 is an 8-bit reload timer. as the clock source, dividing clock or edge signals through the irq1 pin are being used. by selecting the edge signals through the irq1 pin, it can also be used as an event counter. while it is working as an event counter, its reloading function is workable simultaneously. when data are written into the reloading register, these data will be written into the counters (event counter, timer counter) simultaneously. also, when the event counter underflows, the event counter value is reset to the reload register value, and a tmj1i interrupt request occurs. every time the counter underflows, the output level toggles. this output can be used as a buzzer or the carrier frequency at remote-controlled transmission by selecting an appropriate divided clock. the tmj-1 and tmj-2, in combination, can be used as a 16-bit or a 24-bit reload timer. nonetheless, when they are bei ng used, in combination, as a 16-bit timer, word command only is valid and the tck works as the down counter for the upper 8 bits and the tcj works as the down counter for the lower 8 bits, means a reloading register of total 16 bits. when data are written into a 16-bit reloading register, the same data will be written into the 16-bit down counter. also, when the 16-bit down counter underflow signals, the data of the 16-bit reloading register will be reloaded into the down counter. when the exn bit of tmjc is set to 0, the expansion function of tmj-2 is enabled, that is, tmj-2 works as a 16-bit reloading timer, and it can be connected to tmj-1 to be a 24-bit reloading timer. in this case, tck works as the upper 16-bit part and tcj works as the lower 8-bit part of a 24-bit down counter, and tlk works as the upper 16-bit part and tlj works as the lower 8-bit part of a 24-bit reloading register. even when they are making a 16-bit or a 24-bit operation, the tmj1i interrupt requests of the tmj-1 and buzzer outputs are effective. in case these functions are not necessary, make them invalid by programming. the tmj-1 and tmj-2, in combination, can be used for remote controlled data transmission. regarding the remote controlled data transmission, see section 13.3.3, remote controlled data transmission. 13.3.2 8-bit reload timer (tmj-2) the tmj-2 is an 8-bit or a 16-bit down-counting reload timer. as the clock source, dividing clock, edge signals through the irq2 pin or the underflow signals from the tmj-1 are being used. by selecting the edge signals through the irq2 pin, it can also be used as an event counter. while it is working as an event counter, its reloading function is workable simultaneously. when data are written into the reloading register, these data will be written into the counter simultaneously. also, when the counter underflows, re loading will be made to the data counter of section 13 timer j rev.2.00 jan. 15, 2007 page 271 of 1174 rej09b0329-0200 the reloading register. when the counter underflows, tmj2i interrupt requests will be issued. the tmj-2 and tmj-1, in combination, can be used as a 16-bit or a 24-bit reload timer. for more information on the 16-bit or 24-bit reload timer, see section 13.3.1, 8-bit reload timer (tmj-1). the tmj-2 and tmj-1, in combination, can be ope rated by remote controlled data transmission. regarding the remote controlled data transmission, see section 13.3.3, remote controlled data transmission. 13.3.3 remote controlled data transmission the timer j is capable of making remote controlled data transmission. the carrier frequencies for the remote controlled data transmission can be generated by the tmj-1 and the burst width duration and the space width durati on can be setup by the tmj-2. the data having been written into the reloading register tmj-1 and into the burst/space duration register (tlk) of the tmj-2 will be loaded to the counter at the same time as the remote controlled data transmission starts. (remote controlled data transmission starting bit (st) 1) while remote controlled data transmission is bei ng made, the contents of the burst/space duration register will be loaded to the counter only while reloading is being made by underflow signals. even when a writing is made to the burst/space duration register while remote controlled data transmission is being made, reloading operatio n will not be made until an underflow signal is issued. the tmj-2 issues tmj2i interrupt requests by the underflow signals. the tmj-1 performs normal reloading operation (including the tmj1i interrupt requests). figure 13.2 shows the output waveform for the remote controlled data transmission function. when a shift to the low power consumption mode is effected while remote controlled data transmission is being made, the st bit will be cleared to 0. when resuming the remote controlled data transmission after returning to the active mode, write 1. section 13 timer j rev.2.00 jan. 15, 2007 page 272 of 1174 rej09b0329-0200 burst width space width burst width tmj-2 toggle output = 1 tmj-2 toggle output = 0 tmj-2 toggle output = 1 setting the space width setting the burst width setting the space width st bit 1 underflow underflow underflow tmj-1 can generate the carrier frequencies remote controlled data transmission outputs setting the remote controlled mode setting the burst width figure 13.2 remote controlled data transmission output waveform section 13 timer j rev.2.00 jan. 15, 2007 page 273 of 1174 rej09b0329-0200 tmj-1 udf tmo (buzz) tmj-2 udf remoout tmo remote controlled data transmission output figure 13.3 timer output timing section 13 timer j rev.2.00 jan. 15, 2007 page 274 of 1174 rej09b0329-0200 when the timer j is set to the remote controlled operation mode, since the start bit (st) is being set or cleared in synchronization with the inputting clock to the tmj-2, a delay upto a cycle of the inputting clock at the maximum occurs, namely, after the st bit has been set to 1 until the remote controlled data transmission starts. consequently, when the tlk is updated during the period after setting the st bit to 1 until the next cycle of the inputting clock comes, the initial burst width will be changed as shown in figure 13.4. therefore, when making remote controlled data transmission, determine 1/0 of the tgl bit at the time of the first burst width control operation w ithout fail. (or, set the space width to the tlk after waiting for a cycle of the inputting clock.) after that, operations can be continued by interrupts. similarly, pay attention to the control works when ending remote controlled data transmission. example: 1) set the burst width with the tlk. 2) st bit 1. 3) execute the procedure 4) if the tgl flag = 1. 4) set the space width with the tlk under the status where the tgl flag = 1. 5) make tmj-2 interrupt. 6) set the burst width with the tlk. : n) after making tmj-2 interrupt, make setting of the st 0 under the status where the tgl flag = 0. the period during which the space width settig can be made. (s) delay interrupt interrupt tlk setting (burst width) (b) burst width according to (b) space width according to (s) stopping the remote controlled data transmission tgl flag inputting clock to the tmj-2 st 0 delay st 1 remote controlled data transmission starts here. if an updating is made with the tlk during this period, the burst width will be changed. figure 13.4 controls of the remote controlled data transmission section 13 timer j rev.2.00 jan. 15, 2007 page 275 of 1174 rej09b0329-0200 13.3.4 tmj-2 expansion function the tmj-2 expansion function is enabled by setting the exn bit in the timer j control register (tmjc) to 0. this function makes tmj-2, which usually works as an 8-bit counter, work as a 16- bit counter. when this function is selected, timer counter k (tck) and timer load register k (tlk) must be accessed as follows: tck read: to read tck, use the word-length mov instruction. in this case, the upper 8 bits of tck are read out to the lower byte of the on-chip data bus, and the lower 8 bits are read out to the upper byte of the on-chip data bus. that is, when mov.w @tck, rn is executed, the lower 8 bits of tck are stored in rnh and the upper 8 bits are stored in rnl. tlk write: to write to tlk, use the word-length mov instruction. in this case, the upper 8 bits are written to the lower byte of tlk, and the lower 8 bits are written to the upper byte of tlk. that is, when mov.w rn, @tlk is executed, the rnh data is written to the lower byte of tlk, and the rnl data is written to the upper byte of tlk. section 13 timer j rev.2.00 jan. 15, 2007 page 276 of 1174 rej09b0329-0200 section 14 timer l rev.2.00 jan. 15, 2007 page 277 of 1174 rej09b0329-0200 section 14 timer l 14.1 overview timer l is an 8-bit up/down counter using the control pulses or the cfg division signals as the clock source. 14.1.1 features features of timer l are as follows: ? two types of internal clocks ( /128 and /64), dvcfg2 (cfg division signal 2), pb and rec-ctl (control pulses) are available for your selection. ? when the pb-ctl is not available, such as when reproducing un-recorded tapes, tape count can be made by the dvcfg2. ? selection of the rising edge or the falling edge is workable with the ctl pulse counting. ? interrupts occur when the counter overflows or underflows and at occurrences of compare match clear. ? capable to switch over between the up-counting and down-counting functions with the counter. section 14 timer l rev.2.00 jan. 15, 2007 page 278 of 1174 rej09b0329-0200 14.1.2 block diagram figure 14.1 shows a block diagram of timer l. legend: internal data bus dvcfg2 : division signal 2 of the cfg pb and rec-ctl : control pluses necessary when making reproduction and storage lmr : timer l mode register ltc : linear time counter rcr : reload/compare match register ovf : overflow udf : underflow lmr ltc rcr comparator write ovf/udf reloading match clear interrupt request interrupting circuit dvcfg2 pb and rec-ctl internal clock /128 /64 read figure 14.1 block diagram of timer l section 14 timer l rev.2.00 jan. 15, 2007 page 279 of 1174 rej09b0329-0200 14.1.3 register configuration table 14.1 shows the register configuration of timer l. the linear tim e counter (ltc) and the reload compare patch register (rcr) are being allocated to the same address. reading or writing determines the accessing register. table 14.1 register configuration name abbrev. r/w size initial value address * timer l mode register lmr r/w byte h'30 h'd112 linear time counter ltc r byte h'00 h'd113 reload/compare match register rcr w byte h'00 h'd113 note: * lower 16 bits of the address. section 14 timer l rev.2.00 jan. 15, 2007 page 280 of 1174 rej09b0329-0200 14.2 register descriptions 14.2.1 timer l mode register (lmr) 0 0 1 0 r/w 2 0 r/w 3 0 4 1 5 ? ? ? ? 1 6 0 7 r/w r/w r/w lmie 0 r /(w) * lmif lmr3 lmr2 lmr1 lmr0 note: * only 0 can be written to clear the flag. bit : initial value : r/w : the timer l mode register a (lmr) is an 8-bit read/write register which works to control the interrupts, to select between up-counting and down-counting and to select the clock source. when reset, the lmr is initialized to h'30. bit 7 ? timer l interrupt requesting flag (lmif): this is the timer l interrupt requesting flag. it indicates occurrence of overflow or underflow of the ltc or occurrence of compare match clear. bit 7 lmif description 0 [clearing condition] (initial value) when 0 is written after reading 1 1 [setting condition] when the ltc overflows, underflows or when compare match clear has occurred bit 6 ? enabling interrupt of the timer l (lmie): when the ltc overflows, underflows or when compare match clear has occurred, then lmif is set to 1, this bit works to permit/prohibit the occurrence of an in terrupt of timer l. bit 6 lmie description 0 prohibits occurrence of interrupt of timer l (initial value) 1 permits occurrence of interrupt of timer l bits 5 and 4 ? reserved: these bits cannot be modified and are always read as 1. bit 3 ? up-count/down-count control (lmr3): this bit is for selection if timer l is to be controlled to the up-counting function or down-counting function. section 14 timer l rev.2.00 jan. 15, 2007 page 281 of 1174 rej09b0329-0200 1. when controlled to the up-counting function ? when any other values than h'00 are input to the rcr, the ltc will be cleared to h'00 before starting counting up. when the ltc value and the rcr value match, the ltc will be cleared to h'00. also, interrupt requests will be issued by the match signal. (compare match clear function) ? when h'00 is set to the rcr, the counter makes 8-bit interval timer operation to issue a interrupt request when overflowing occurs. (interval timer function) 2. when controlled to the down-counting function ? when a value is set to the rcr, the set value is reloaded to the ltc and counting down starts from that value. when the ltc underflows, the value of the rcr will be reloaded to the ltc. also, when the ltc underflows, a inte rrupt request will be issued. (auto reload timer function) bit 3 lmr3 description 0 controlling to the up-counting function (initial value) 1 controlling to the down-counting function bits 2 to 0 ? clock selection (lmr2 to lmr0): the bits lmr2 to lmr0 work to select the clock to input to timer l. selection of the leading edge or the trailing edge is workable for counting by the pb and the rec-ctl. bit 2 bit 1 bit 0 lmr2 lmr1 lmr0 description 0 counts at the rising edge of the pb and rec-ctl (initial value) 0 1 counts at the falling edge of the pb and rec-ctl 0 1 * counts the dvcfg2 1 0 * counts at /128 of the internal clock 1 * counts at /64 of the internal clock legend: * don't care. section 14 timer l rev.2.00 jan. 15, 2007 page 282 of 1174 rej09b0329-0200 14.2.2 linear time counter (ltc) 0 0 1 0 r 2 0 3 0 4 5 6 0 7 r rr r ltc6 0 r ltc5 0 r ltc4 0 r ltc7 ltc3 ltc2 ltc1 ltc0 bit : initial value : r/w : the linear time counter (ltc) is a readable 8-bit up/down-counter. the inputting clock can be selected by the lmr2 to lmr0 bits of the lmr. when reset, the ltc is initialized to h'00. 14.2.3 reload/compare match register (rcr) 0 0 1 0 w 2 0 3 0 4 5 6 0 7 w ww w rcr6 0 w rcr5 0 w rcr4 0 w rcr7 rcr3 rcr2 rcr1 rcr0 bit : initial value : r/w : the reload/compare match register (rcr) is an 8-bit write only register. when timer l is being controlled to the up-counting function, when a compare match value is set to the rcr, the ltc will be cleared at the same time and the ltc will then start c ounting up from the initial value (h'00). while, when the timer l is being controlled to the down-counting function, when a reloading value is set to the rcr, the same value will be loaded to the ltc at the same time and the ltc will then start counting up from said value. al so, when the ltc underflows, the value of the rcr will be reloaded to the ltc. when reset, the rcr is initialized to h'00. section 14 timer l rev.2.00 jan. 15, 2007 page 283 of 1174 rej09b0329-0200 14.2.4 module stop control register (mstpcr) 7 1 mstp15 r/w mstpcrh 6 1 mstp14 r/w 5 1 mstp13 r/w 4 1 mstp12 r/w 3 1 mstp11 r/w 2 1 mstp10 r/w 1 1 mstp9 r/w 0 1 mstp8 r/w 7 1 mstp7 r/w 6 1 mstp6 r/w 5 1 mstp5 r/w 4 1 mstp4 r/w 3 1 mstp3 r/w 2 1 mstp2 r/w 1 1 mstp1 r/w 0 1 mstp0 r/w mstpcrl bit : initial value : r/w : the mstpcr are 8-bit read/write twin registers which work to control the module stop mode. when the mstp12 bit is set to 1, timer l stops its operation at the ending point of the bus cycle to shift to the module stop mode. for more information, see section 4.5, module stop mode. when reset, the mstpcr is initialized to h'ffff. bit 4 ? module stop (mstp12): this bit works to designate the module stop mode for timer l. mstpcrh bit 4 mstp12 description 0 cancels the module stop mode of timer l 1 sets the module stop mode of timer l (initial value) section 14 timer l rev.2.00 jan. 15, 2007 page 284 of 1174 rej09b0329-0200 14.3 operation timer l is an 8-bit up/down counter. the inputting clock for timer l can be selected by the lmr2 to lmr0 bits of the lmr from the choices of the internal clock ( /128 and /64), dvcdg2, pb and rec-ctl. timer l is provided with three different type s of operation modes, namely, the compare match clear mode when controlled to the up-counting function, the auto reloading mode when controlled to the down-counting function and the interval timer mode. respective operation modes and operation methods will be explained below. 14.3.1 compare match clear operation when the lmr3 bit of the lmr is cleared to 0, timer l will be controlled to the up-counting function. when any other values than h'00 are written into the rcr, the ltc will be cleared to h'00 simultaneously before starting counting up. figure 14.2 shows rcr writing and ltc clearing timing. when the ltc value and the rcr value match (compare match), the ltc readings will be cleared to h'00 to resume counting from h'00. figure 14.3 indicated on the next page shows the compare match clear timing. rcr ltc write signal 1 state n h' 00 figure 14.2 rcr writing and ltc clearing timing chart section 14 timer l rev.2.00 jan. 15, 2007 page 285 of 1174 rej09b0329-0200 ltc rcr n h' 00 n-1 n interrupt request count-up signal compare match clear signal pb-ctl figure 14.3 compare matc h clearing timing chart (in case the rising edge of the pb-ctl is selected) 14.3.2 auto-reload operation when 1 is written in bit lmr3 of lmr, ltc enters down-counting control mode. when a reload value is written in rcr, ltc is reloaded with the same value and starts counting down from that value. figure 14.4 shows the timing of the writing and reloading of rcr. at underflow, ltc is reloaded with the rcr value. figure 14.5 shows the reload timing. 1 state write signal rcr ltc n n figure 14.4 timing of writing and reloading of rcr section 14 timer l rev.2.00 jan. 15, 2007 page 286 of 1174 rej09b0329-0200 pb-ctl rcr ltc n h'00 h'01 n count-down signal interrupt request reload underflow figure 14.5 reload timing (rising edge of pb-ctl selected) 14.3.3 interval timer operation when bit lmr3 is cleared to 0 in lmr, the timer l enters up-counting control mode. if h'00 is written in rcr, compare-match operations are not carried out. the counter functions as an interval timer (up-counter). 14.3.4 interrupt request the timer l generates an interrupt request when any of the following occurs: ? compare-match clear under up-counting control ? underflow under down-counting control ? overflow or underflow when the reload/compare-match register (rcr) value is h'00 section 14 timer l rev.2.00 jan. 15, 2007 page 287 of 1174 rej09b0329-0200 14.4 typical usage figure 14.6 shows a typical usage of the timer l. h'ff value written in rcr h'00 * ** ltc = rcr compare match clear underflow (reload) underflow (reload) value other than h'00 written in rcr under up-counting control down-counting control (1 written in bit lmr3) (rewind, reverse, etc.) (record, playback, fast-forward, etc.) note: * a downward-pointing arrow indicates an interrupt request. figure 14.6 typical usage of linear time counter 14.5 reload timer interr upt request signal the timer counters with reload registers generate an underflow or overflow in the last cycle before being decremented or incremented. the underflow or overflow generates a reload signal and an interrupt request signal. if the value in the reload register is rewritten at the same time as the underflow or overflow (at the reload timing), an interrupt request is generated and the counter is reloaded at the same time. when rewriting the reload value in order to avoid an interrupt, leave an ample timing margin around the write to the reload register. section 14 timer l rev.2.00 jan. 15, 2007 page 288 of 1174 rej09b0329-0200 figure 14.7 shows a sample timing diagram of contention between an underflow and the rewriting of the reload register. 1 bus cycle write reload register counter udf h'01 h'00 h'nn h'nn-1 irr h'zz h'nn reload: disabled by write legend: write: reload: udf: irr: reload register rewrite signal reload signal counter underflow interrupt request signal figure 14.7 contention between reload timer underflow and rewriting of reload register section 15 timer r rev.2.00 jan. 15, 2007 page 289 of 1174 rej09b0329-0200 section 15 timer r 15.1 overview timer r consists of triple 8-bit down-counters. it carries vcr mode identification function and slow tracking function in addition to the reloading function and event counter function. 15.1.1 features the timer r consists of triple 8-bit reloading timers. by combining the functions of three units of reloading timers/counters and by combining three units of timers, it can be used for the following applications: ? applications making use of the functions of three units of reloading timers. ? for identification of the vcr mode. ? for reel controls. ? for acceleration and braking of the capstan motor when being applied to intermittent movements. ? slow tracking mono-multi applications. 15.1.2 block diagram timer r consists of three units of reload timer counters, namely, two units of reload timer counters equipped with capturing function (tmr u-1 and tmru-2) and a unit of reload timer counter (tmru-3). figure 15.1 is a block diagram of timer r. section 15 timer r rev.2.00 jan. 15, 2007 page 290 of 1174 rej09b0329-0200 notes: internal bus internal bus clock sources dvctl cfg clock selection (2 bits) reloadin g re g ister (8 bits) down-counter (8 bits) capture re g ister (8 bits) tmri2 interrupt request tmri1 interrupt request tmri3 interrupt request tmru-1 tmrcp1 * 2 under flow tmru-3 underflow * 1 tmrl3 ps31,30 external si g nals irq3 /1024 /2048 /4096 clock source /64 /128 /256 clock sources /4 /256 /512 down-counter (8 bits) latch clock selection clock selection (2 bits) resettin g available/ not available cp/ slm slw capf capture re g ister (8 bits) down-counter (8 bits) reloadin g re g ister (8 bits) acceleration/ brakin g reloadin g available/ not available reloadin g clock selection reloadin g re g ister (8 bits) rld/ cap clock selection (2 bits) cps lat ps21,20 clr2 res res tmrcp2 under flow tmru-2 cfg mask f/f r s q r s q acceleration brakin g ac/br tmrl2 rld rlck tmrl1 ps11,10 interruptin g circuit 1. when the dvctl is bein g used as the clock source, reloadin g will be made when the counter underflows and when the dividin g clock is bein g used as the clock source, reloadin g will be made by the dvctl. 2. when the lat bit = 0, the capture si g nal a g ainst the tmru-1 will not be output. figure 15.1 block diagram of timer r section 15 timer r rev.2.00 jan. 15, 2007 page 291 of 1174 rej09b0329-0200 15.1.3 pin configuration table 15.1 shows the pin configuration of timer r. table 15.1 pin configuration name abbrev. i/o function input capture inputting pin irq3 input input capture inputting for the timer r 15.1.4 register configuration table 15.2 shows the register configuration of timer r. table 15.2 register configuration name abbrev. r/w size initial value address timer r mode register 1 tmrm1 r/w byte h'00 h'd118 timer r mode register 2 tmrm2 r/w byte h'00 h'd119 timer r control/status register tmrcs r/w byte h'03 h'd11f timer r capture register 1 tmrcp1 r byte h'ff h'd11a timer r capture register 2 tmrcp2 r byte h'ff h'd11b timer r load register 1 tmrl1 w byte h'ff h'd11c timer r load register 2 tmrl2 w byte h'ff h'd11d timer r load register 3 tmrl3 w byte h'ff h'd11e note: memories of respective registers will be preserved even under the low power consumption mode. nonetheless, the capf flag and slw flag of the tmrm2 will be cleared to 0. section 15 timer r rev.2.00 jan. 15, 2007 page 292 of 1174 rej09b0329-0200 15.2 register descriptions 15.2.1 timer r mode register 1 (tmrm1) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 5 0 6 0 7 r/w r/w r/w rld r/w ac/br 0 r/w clr2 rlck ps21 ps20 rld/cap cps bit : initial value : r/w : the timer r mode register 1 (tmrm1) works to control the acceleration and braking processes and to select the inputting clock for the tmru-2. this is an 8-bit read/write register. when reset, the tmrm1 is initialized to h'00. bit 7 ? selecting clearing/not cl earing of tmru-2 (clr2): this bit is used for selecting if the tmru-2 counter reading is to be cleared or not as it is captured. bit 7 clr2 description 0 tmru-2 counter reading is not to be cleared as soon as it is captured. (initial value) 1 tmru-2 counter reading is to be cleared as soon as it is captured bit 6 ? acceleration/braking pr ocessing (ac/br): this bit works to control occurrences of interrupt requests to detect co mpletion of acceleration or braki ng while the capstan motor is making intermittent revolutions. for more information, see section 15.3.6, accel eration and braking processes of the capstan motor. bit 6 ac/br description 0 braking (initial value) 1 acceleration section 15 timer r rev.2.00 jan. 15, 2007 page 293 of 1174 rej09b0329-0200 bit 5 ? using/not using the tmru-2 for reloading (rld): this bit is used for selecting if the tmru-2 reload function is to be turned on or not. bit 5 rld description 0 not using the tmru-2 as the reload timer (initial value) 1 using the tmru-2 as the reload timer bit 4 ? reloading timing for the tmru-2 (rlck): this bit works to select if the tmru-2 is reloading by the cfg or by underflowing of the tmru-2 counter. this choice is valid only when the bit 5 (rld) is being set to 1. bit 4 rlck description 0 reloading at the rising edge of the cfg (initial value) 1 reloading by underflowing of the tmru-2 bits 3 and 2 ? clock source for the tm ru-2 (ps21, ps20): these bits work to select the inputting clock to the tmru-2. bit 3 bit 2 ps21 ps20 description 0 counting by underflowing of the tmru-1 (initial value) 0 1 counting by the pss, /256 1 0 counting by the pss, /128 1 counting by the pss, /64 bit 1 ? operation mode of the tmru-1 (rld/cap): this bit works to select if the operation mode of the tmru-1 is reload timer mode or capture timer mode. under the capture timer mode, reloading operatio n will not be made. also, the counter reading will be cleared as soon as capture has been made. bit 1 rld/cap description 0 the tmru-1 works as the reloading timer (initial value) 1 the tmru-1 works as the capture timer section 15 timer r rev.2.00 jan. 15, 2007 page 294 of 1174 rej09b0329-0200 bit 0 ? capture signals of the tmru-1 (cps): in combination with the lat bit (bit 7) of the tmrm2, this bit works to select the capture signals of the tmru-1. this bit becomes valid when the lat bit is being set to 1. it will also become valid when the rld/cap bit (bit 1) is being set to 1. nonetheless, it will be invalid when the rld/cap bit (bit 1) is being set to 0. bit 0 cps description 0 capture signals at the rising edge of the cfg (initial value) 1 capture signals at the edge of the irq3 15.2.2 timer r mode register 2 (tmrm2) 0 0 1 0 r/(w) * 2 0 r/w 3 0 4 0 r/w 5 0 6 0 7 r/(w) * r/w r/w ps10 r/w ps11 0 r/w lat ps31 ps30 cp/slm capf slw bit : initial value : r/w : the timer r mode register 2 (tmrm2) is an 8-bit read/write register which works to identify the operation mode and to control the slow tracking processing. when reset, the tmrm2 is initialized to h'00. note: * the capf bit and the slw bit, respectively, works to latch the interrupt causes and writing 0 only is valid. consequently, when these bits are being set to 1, respective interrupt requests will not be issued. therefore, it is necessary to check these bits during the course of the interrupt processing routine to have them cleared. also, priority is given to the set and, when an interrupt cause occur while the a clearing command (bclr, mov, etc.) is being execu ted, the capf bit and the slw bit will not be cleared respectively and it thus becomes necessary to pay attention to the clearing timing. section 15 timer r rev.2.00 jan. 15, 2007 page 295 of 1174 rej09b0329-0200 bit 7 ? capture signals of the tmru-2 (lat): in combination with the cps bit (bit 0) of the tmrm1, this bit works to select the capture signals of the tmru-2. tmrm2 tmrm1 bit 7 bit 0 lat cps description 0 * captures when the tmru-3 underflows (initial value) 1 0 captures at the rising edge of the cfg 1 captures at the edge of the irq3 legend: * don't care. bits 6 and 5 ? clock source for the tm ru-1 (ps11, ps10): these bits work to select the inputting clock to the tmru-1. bit 6 bit 5 ps11 ps10 description 0 counting at the rising edge of the cfg (initial value) 0 1 counting by the pss, /4 1 0 counting by the pss, /256 1 counting by the pss, /512 bits 4 and 3 ? clock source for the tm ru-3 (ps31, ps30): these bits work to select the inputting clock to the tmru-3. bit 4 bit 3 ps31 ps30 description 0 counting at the rising edge of the dvctl from the dividing circuit. (initial value) 0 1 counting by the pss, /4096 1 0 counting by the pss, /2048 1 counting by the pss, /1024 section 15 timer r rev.2.00 jan. 15, 2007 page 296 of 1174 rej09b0329-0200 bit 2 ? interrupt causes (cp/slm): this bit works to select the interrupt causes for the tmri3. bit 2 cp/slm description 0 makes interrupt requests upon the capture signals of the tmru-2 valid (initial value) 1 makes interrupt requests upon ending of the slow tracking mono-multi valid bit 1 ? capture signal flag (capf): this is a flag being set out by the capture signal of the tmru-2. although both reading/ writing are possible, 0 only is valid for writing. also, priority is being given to the set and, when the capture signal and writing 0 occur simultaneously, this flag bit remains being set to 1 and the interrupt request will not be issued and it is necessary to be attentive about this fact. when the cp/slm bit (bit 2) is being set to 1, this capf bit should always be set to 0. the capf flag is cleared to 0 under the low power consumption mode. bit 1 capf description 0 [clearing condition] (initial value) when 0 is written after reading 1 1 [setting condition] at occurrences of the tmru-2 capture signals while the cp/slm bit is set to 0 bit 0 ? slow tracking mono-multi flag (slw): this is a flag being set out when the slow tracking mono-multi processing ends. although both reading/writing are possible, 0 only is valid for writing. also, priority is being given to the set and, when ending of the slow tracking mono-multi processing and writing 0 occur simultaneously, this flag bit remains being set to 1 and the interrupt request will not be issued and it is nece ssary to be attentive about this fact. when the cp/slm bit (bit 2) is being set to 0, this slw bit should always be set to 0. the slw flag is cleared to 0 under the low power consumption mode. bit 0 slw description 0 [clearing condition] (initial value) when 0 is written after reading 1 1 [setting condition] when the slow tracking mono-multi processing ends while the cp/slm bit is set to 1 section 15 timer r rev.2.00 jan. 15, 2007 page 297 of 1174 rej09b0329-0200 15.2.3 timer r control/status register (tmrcs) 0 1 1 ? ? ? ? 1 2 0 r/(w) * 3 0 4 0 r/(w) * 5 0 6 0 7 r/(w) * r/w tmri1e r/w tmri2e 0 r/w tmri3e tmri3 tmri2 tmri1 note: * only 0 can be written to clear the fla g . bit : initial value : r/w : the timer r control/status register (tmrcs) works to control the interrupts of timer r. the tmrcs is an 8-bit read/write register. when reset, the tmrcs is initialized to h'03. bit 7 ? enabling the tmri3 interrupt (tmri3e): this bit works to permit/prohibit occurrence of the tmri3 interrupt when an interrupt cause being selected by the cp/slm bit of the tmrm2 has occurred, such as occurrences of the tmru -2 capture signals or when the slow tracking mono-multi processing ends, and the tmri3 has been set to 1. bit 7 tmri3e description 0 prohibits occurrences of tmri3 interrupts (initial value) 1 permits occurrences of tmri3 interrupts bit 6 ? enabling the tmri2 interrupt (tmri2e): this bit works to permit/prohibit occurrence of the tmri2 interrupt when the tmri2 has been set to 1 by issuance of the underflow signal of the tmru-2 or by ending of the slow tracking mono-multi processing. bit 6 tmri2e description 0 prohibits occurrences of tmri2 interrupts (initial value) 1 permits occurrences of tmri2 interrupts bit 5 ? enabling the tmri1 interrupt (tmri1e): this bit works to permit/prohibit occurrence of the tmri1 interrupt when the tmri1 has been set to 1 by issuance of the underflow signal of the tmru-1. bit 5 tmri1e description 0 prohibits occurrences of tmri1 interrupts (initial value) 1 permits occurrences of tmri1 interrupts section 15 timer r rev.2.00 jan. 15, 2007 page 298 of 1174 rej09b0329-0200 bit 4 ? tmri3 interrupt requesting flag (tmri3): this is the tmri3 interrupt requesting flag. it indicates occurrence of an in terrupt cause being selected by the cp/slm bit of the tmrm2, such as occurrences of the tmru-2 capture signals or ending of the slow tracking mono-multi processing. bit 4 tmri3 description 0 [clearing condition] (initial value) when 0 is written after reading 1 1 [setting condition] at occurrence of the interrupt cause being selected by the cp/slm bit of the tmrm2 bit 3 ? tmri2 interrupt requesting flag (tmri2): this is the tmri2 interrupt requesting flag. it indicates occurrences of the tmru-2 underflow signals or ending of the acceleration/braking processing of the capstan motor. bit 3 tmri2 description 0 [clearing condition] (initial value) when 0 is written after reading 1 1 [setting condition] at occurrences of the tmru-2 underflow signals or ending of the acceleration /braking processing of the capstan motor bit 2 ? tmri1 interrupt requesting flag (tmri1): this is the tmri1 interrupt requesting flag. it indicates occurrences of the tmru-1 underflow signals. bit 2 tmri1 description 0 [clearing condition] (initial value) when 0 is written after reading 1. 1 [setting condition] when the tmru-1 underflows. section 15 timer r rev.2.00 jan. 15, 2007 page 299 of 1174 rej09b0329-0200 bits 1 and 0 ? reserved: these bits cannot be modified and are always read as 1. 15.2.4 timer r capture register 1 (tmrcp1) 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 r tmrc17 r tmrc16 r tmrc15 r tmrc14 r tmrc13 r tmrc12 r tmrc11 r tmrc10 bit : initial value : r/w : the timer r capture register 1 (tmrcp1) work s to store the captured data of the tmru-1. during the course of the capturing operation, the tmru-1 counter readings are captured by the tmrcp1 at the cfg edge or the irq3 edge. the capturing operation of the tmru-1 is performed using 16 bits, in combination with the capturing operation of the tmru-2. the tmrcp1 is an 8-bit read only register. when reset, the tmrcs is initialized to h'ff. notes: 1. when the tmrcp1 is readout while th e capture signal is being received, the reading data become unstable. pay attention to the timing for reading out. 2. when a shift to the low power consumption mode is made while the capturing operating is in progress, the counter reading becomes unstable. after returning to the active mode, always write h'ff into the tmrl1 to initialize the counter. 15.2.5 timer r capture register 2 (tmrcp2) 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 r tmrc27 r tmrc26 r tmrc25 r tmrc24 r tmrc23 r tmrc22 r tmrc21 r tmrc20 bit : initial value : r/w : the timer r capture register 2 (t mrcp2) works to store the capture data of the tmru-2. at each cfg edge, irq3 edge, or at occurrence of underflow of the tmru-3, the tmru-2 counter readings are captured by the tmrcp2. the tmrcp2 is an 8-bit read only register. when reset, the tmrcs will be initialized into h'ff. notes: 1. when the tmrcp2 is readout while th e capture signal is being received, the reading data become unstable. pay attention to the timing for reading out. 2. when a shift to the low power consumption mode is made, the counter reading becomes unstable. after returning to the active mode, always write h'ff into the tmrl2 to initialize the counter. section 15 timer r rev.2.00 jan. 15, 2007 page 300 of 1174 rej09b0329-0200 15.2.6 timer r load register 1 (tmrl1) 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 w tmr17 w tmr16 w tmr15 w tmr14 w tmr13 w tmr12 w tmr11 w tmr10 bit : initial value : r/w : the timer r load register 1 (tmrl1) is an 8-bit write-only register which works to set the load value of the tmru-1. when a load value is set to the tmrl1, the same value will be set to the tmru-1 counter simultaneously and the counter starts counting down from the set value. also, when the counter underflows during the course of the reload timer operation, the tmrl1 value will be set to the counter. when reset, the tmrl1 is initialized to h'ff. 15.2.7 timer r load register 2 (tmrl2) 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 w tmr27 w tmr26 w tmr25 w tmr24 w tmr23 w tmr22 w tmr21 w tmr20 bit : initial value : r/w : the timer r load register 2 (tmrl2) is an 8-bit write only register which works to set the load value of the tmru-2. when a load value is set to the tmrl2, the same value will be set to the tmru-2 counter simultaneously and the counter starts counting down from the set value. also, when the counter underflows or a cfg edge is detected during the course of the reload timer operation, the tmrl2 value will be set to the counter. when reset, the tmrl2 is initialized to h'ff. section 15 timer r rev.2.00 jan. 15, 2007 page 301 of 1174 rej09b0329-0200 15.2.8 timer r load register 3 (tmrl3) 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 w tmr37 w tmr36 w tmr35 w tmr34 w tmr33 w tmr32 w tmr31 w tmr30 bit : initial value : r/w : the timer r load register 3 (tmrl3) is an 8-bit write only register which works to set the load value of the tmru-3. when a load value is set to the tmrl3, the same value will be set to the tmru-3 counter simultaneously and the counter starts counting down from the set value. also, when the counter underflows or a dvctl edge is detected, the tmrl 2 value will be set to the counter. (reloading will be made by the underflowing signals when th e dvctl signal is selected as the clock source, and reloading will be made by the dvctl signals when the dividing clock is selected as the clock source.) when reset, the tmrl3 is initialized to h'ff. 15.2.9 module stop control register (mstpcr) 7 1 mstp15 r/w mstpcrh 6 1 mstp14 r/w 5 1 mstp13 r/w 4 1 mstp12 r/w 3 1 mstp11 r/w 2 1 mstp10 r/w 1 1 mstp9 r/w 0 1 mstp8 r/w 7 1 mstp7 r/w 6 1 mstp6 r/w 5 1 mstp5 r/w 4 1 mstp4 r/w 3 1 mstp3 r/w 2 1 mstp2 r/w 1 1 mstp1 r/w 0 1 mstp0 r/w mstpcrl bit : initial value : r/w : the mstpcr are 8-bit read/write twin registers which work to control the module stop mode. when the mstp11 bit is set to 1, timer r stops its operation at the ending point of the bus cycle to shift to the module stop mode. for more information, see section 4.5, module stop mode. when reset, the mstpcr is initialized to h'ffff. bit 3 ? module stop (mstp11): this bit works to designate the module stop mode for the timer r. mstpcrh bit 3 mstp11 description 0 cancels the module stop mode of timer r 1 sets the module stop mode of timer r (initial value) section 15 timer r rev.2.00 jan. 15, 2007 page 302 of 1174 rej09b0329-0200 15.3 operation 15.3.1 reload timer counter equipped with capturing function tmru-1 tmru-1 is a reload timer counter equipped with capturing function. it consists of an 8-bit down- counter, a reloading register and a capture register. the clock source can be selected from among the leading edge of the cfg signals and three types of dividing clocks. it is also selectable whether using it as a reload counter or as a capture counter. even when the capturing function is selected, the counter readings can be updated by writing the values into the reloading register. when the counter underflows, the tmri 1 interrupt request will be issued. the initial values of the tmru-1 counter, reloading register and capturing register are all h'ff. ? operation of the reload timer when a value is written into to the reloading register, the same value will be written into the counter simultaneously. also, when the counter underflows, the reloading register value will be reloaded to the counter. the tmru-1 is a dividing circuit for the cfg. in combination with the tmru-2 and tmru-3, it can also be used for the mode identification purpose. ? capturing operation capturing operation is carried out in combination with the tmru-2 using the combined 16 bits. it can be so programmed that the counter may be cleared by the capture signal. the cfg edges or irq3 edges are used as the capture signa ls. it is possible to issue the tmri3 interrupt request by the capture signal. in addition to the capturing function being worked out in combination with the tmru-2, the tmru-1 can be used as a 16-bit cfg counter. selecting the irq3 as the capture signal, the cfg within the duration of the reel pulse being input into the irq3 pin can be counted by the tmru-1. 15.3.2 reload timer counter equipped with capturing function tmru-2 tmru-2 is a reload timer counter equipped with capturing function. it consists of an 8-bit down- counter, a reloading register and a capture register. the clock source can be selected from among the undedrflowing signal of the tmru-1 and three types of dividing clocks. also, although the reloading function is workable during its capturing operation, equipping or not of the reloading function is selectable. even when without-reloading- function is chosen, the counter reading can be updated by writing the values to the reloading register. when the counter underflows, the tmri 2 interrupt request will be issued. the initial values of the tmru-2 counter, reloading register and capturing register are all h'ff. section 15 timer r rev.2.00 jan. 15, 2007 page 303 of 1174 rej09b0329-0200 ? operation of the reload timer when a value is written into to the reloading register, the same value will be written into the counter, simultaneously. also, when the counter underflows or when a cfg edge is detected, the reloading register value w ill be reloaded to the counter. the tmru-2 can make acceleration and braking wo rk for the capstan motor using the reload timer operation. ? capturing operation using the capture signals, the counter reading can be latched into the capturing register. as the capture signal, you can choose from among edges of the cfg, edges of the irq3 or the underflow signals of the tmru-3. it is possible to issue the tmri3 interrupt request by the capture signal. the capturing function (stopping the reloading function) of the tmru-2, in combination with the tmru-1 and tmru-3, can also be used for the mode identification purpose. 15.3.3 reload counter timer tmru-3 the reload counter timer tmru-3 consists of an 8-bit down-counter and a reloading register. its clock source can be selected from between the undedrflowing signal of the counter and the edges of the dvctl signals. (when the dvctl signal is sel ected as the clock source, reloading will be effected by the underflowing signals and when the dividing clock is selected as the clock source, reloading will be effected by the dvctl signals.) the reloading signal works to reload the reloading register value into the counter. also, when a value is written into to th e reloading register, the same value will be written into the counter, simultaneously. the initial values of the counter and the reloading register are h'ff. the underflowing signals can be used as the capturing signal for the tmru-2. the tmru-3 can also be used as a dividing circuit for the dvctl. also, in combination with the tmru-1 and tmru-2 (capturing function), the tmru-3 can be used for the mode identification purpose. since the divided signals of the dvctl are being used as the clock source, ctl signals (dvctl) conforming to the double speed can be input when making searches. these dvctl signals can also be used for phase controls of the capstan motor. also, by selecting the dividing clock as the clock source, it is possible to make a delay with the edges of the dvctl to provide the slow tracking mono-multi function. section 15 timer r rev.2.00 jan. 15, 2007 page 304 of 1174 rej09b0329-0200 15.3.4 mode identification when making mode identification (2/4/6 identification) of the sp/lp/ep modes of reproducing tapes, the tmru-1 (cfg dividing circuit), tmru-2 (capturing function/without reloading function) and tmru-3 (dvctl dividing circuit) of timer r should be used. timer r will become to the aforementioned status after a reset. under the aforementioned status, the divided cfg s hould be written into the reloading register of the tmru-1 and divided dvctl should be written into the reloading regi ster of the tmru-3. when the tmru-3 underflows, the counter value of the tmru-2 is captured. such capturing register value represents the number of the cfg within the dvctl cycle. as aforementioned, the timer r can work to count the number of the cfg corresponding to n times of dvctl's or to identify the mode being searched. for register settings, see section 15.5.1, mode identification. 15.3.5 reeling controls cfg counts can be captured by making 16-bit capturing operation combining the tmru-1 and tmru-2. choosing the irq3 as the capture signal and counting the cfg within the duration of the reel pulse being input through the irq3 pin affect reeling controls. for register settings, see section 15.5.2, reeling controls. 15.3.6 acceleration and braking processes of the capstan motor when making intermittent movements such as those for slow reproductions or for still reproductions, it is necessary to conduct quick accelerations and abrupt stoppings of the capstan motor. the acceleration and braking processes func tions to check if the revolution of a capstan motor has reached the prescribed rate when accelerated or braked . for this purpose, the tmru-2 (reloading function) should be used. when making accelerations: ? set the ac/br bit of the tmrm1 to acceleration (s et to 1). also, use the rising edge of the cfg as the reloading signal. ? set the prescribed tim e on the cfg frequency to determ ine if the acceleration has been finished, into the reloading register. ? the tmru-2 will work to do wn-count the reloading data. ? in case the acceleration has not been finished (i n case the cfg signal is not input even when the prescribed time has elapsed = underflowing of down-counting has occurred), such underflowing works to set to cfg mask f/f (mas king movement) and the reload timer will be cleared by the cfg. section 15 timer r rev.2.00 jan. 15, 2007 page 305 of 1174 rej09b0329-0200 ? when the acceleration has been finished (when th e cfg signal is input before the prescribed time has elapsed = reloading movement has been made before the down counter underflows), an interrupt request will be issued because of the cfg. when making breaking: ? set the ac/br bit of the tmrm1 to braking (clear to 0). also, use the rising edge of the cfg as the reloading signal. ? set the prescribed time on the cfg frequency to determine if the braking has been finished, into the reloading register. ? the tmru-2 will work to do wn-count the reloading data. ? if the braking has not finished (when the cfg signal is input before the prescribed time has elapsed and reloading movement has been ma de before the down counter underflows), the reload timer movement will continue. ? when the acceleration has finished (when th e cfg signal is not input even when the prescribed time has elapsed and underflowing of down-counting has occurred), interrupt request will be issued because of the underflowing signal. the acceleration and braking processes should be employed when making special reproductions, in combination with the slow tracking mono-multi function outlined in section 15.3.7, slow tracking mono-multi function. for register settings, see section 15.5.4, accelera tion and braking processes of the capstan motor. 15.3.7 slow tracking mono-multi function when performing slow reproductions or still reproductions, the braking timing for the capstan motor is determined by use of the edge of the dvctl signal. the slow tracking mono-multi function works to measure the time from the rising edge of the dvctl signal down to the desired point to issue the interrupt request. in actual programming, this interrupt should be used to activate the brake of the capstan motor. the tmru-3 should be used to perform time measurements for the slow tracking mono-multi function. also, the braking process can be made using the tmru-2. figure 15.2 shows the time series movements when a slow reproduction is being performed. for register settings, see section 15.5.3, slow tracking mono-multi function. section 15 timer r rev.2.00 jan. 15, 2007 page 306 of 1174 rej09b0329-0200 hsw fg acceleration detection compensation for vertical vibrations (supplementary v-pulse) dvctl interrupt reloading reverse rotation frame feeds compensation for horizontal vibrations compensation for horizontal vibrations braking process acceleration process slow tracking delay c.rotary h.ampsw accelerating the capstan motor braking the drum motor slow tracking mono-multi braking the capstan motor servo hi-z legend: hi-z : high impedance state in case of 4-head sp mode. in case of 2-head application, h.ampsw and c.rotary should be "low". fg stopping detection forward rotation figure 15.2 time series movements when a slow reproduction is being performed section 15 timer r rev.2.00 jan. 15, 2007 page 307 of 1174 rej09b0329-0200 15.4 interrupt cause in timer r, bits tmri1 to tmri3 of the timer r control/status register cause interrupts. the following are descriptions of the interrupts. 1. interrupts caused by the underflowing of the tmru-1 (tmri1) these interrupts will constitute the timing for reloading with the tmru-1. 2. interrupts caused by the underflowing of the tmru-2 or by an end of the acceleration or braking process (tmri2) when interrupts occur at the reload timing of the tmru-2, clear the ac/br (acceleration/braking) bit of the timer r mode register 1 (tmrm1) to 0. 3. interrupts caused by the capture signals of the tmru-2 and by ending the slow tracking mono-multi process (tmri3) since these two interrupt causes are constituting the or, it becomes necessary to determine which interrupt cause is occurring using the software. respective interrupt causes are being set to the capf flag or the slw flag of the timer r mode register 2 (tmrm2), have the software determine which. since the capf flag and the slw flag will not be cleared automatically, program the software to clear them. (writing 0 only is valid for these flags.) unless these flag s are cleared, detection of the next cause becomes unworkable. also, if the cp/slm bit is changed leaving these flags uncleared as they are, these flags will get cleared. section 15 timer r rev.2.00 jan. 15, 2007 page 308 of 1174 rej09b0329-0200 15.5 settings for respective functions 15.5.1 mode identification when making mode identification (2/4/6 identification) of the sp/lp/ep modes of reproducing tapes, the tmru-1 (cfg dividing circuit), tmru-2 (capturing function/without reloading function) and tmru-3 (dvctl dividing circuit) of the timer r should be used. timer r will be initialized to this mode identification status after a reset. under this status, the divided cfg should be writte n into the reloading re gister of the tmru-1 and divided dvctl should be written into the re loading register of the tmru-3. when the tmru-3 underflows, the counter value of the tmru-2 is captured. such capturing register value represents the number of the cfg within the dvctl cycle. thus, timer r can work to count the number of the cfg corresponding to n times of dvctl's or to identify the mode being searched. settings ? setting the timer r mode register 1 (tmrm1) ? clr2 bit (bit 7) = 1: works to clear after making the tmru-2 capture. ? rld bit (bit 5) = 0: sets the tmru-2 without reloading function. ? ps21 and ps20 (bits 3 and 2) = (0 and 0): the underflowing signals of the tmru-1 are to be used as the clock source for the tmru-2. ? rld/cap bit (bit 1) = 0: the tmru-1 has been set to make the reload timer operation. ? setting the timer r mode register 2 (tmrm2) ? lat bit (bit 7) = 0: the underflowing signals of the tmru-3 are to be used as the capture signal for the tmru-2. ? ps11 and ps10 (bits 6 and 5) = (0 and 0): the leading edge of the cfg signal is to be used as the clock source for the tmru-1. ? ps31 and ps30 (bits 4 and 3) = (0 and 0): the leading edge of the dvctl signal is to be used as the clock source for the tmru-3. ? cp/slm bit (bit 2) = 0: the capture signal is to work to issue the tmri3 interrupt request. ? setting the timer r load register 1 (tmrl1) ? set the dividing value for the cfg. the set value should become (n ? 1) when divided by n. ? setting the timer r load register 3 (tmrl3) ? set the dividing value for the dvctl. the set value should become (n ? 1) when divided by n. section 15 timer r rev.2.00 jan. 15, 2007 page 309 of 1174 rej09b0329-0200 15.5.2 reeling controls cfg counts can be captured by making 16-bit capturing operation combining the tmru-1 and tmru-2. by choosing the irq3 as the capture signal, and by counting the cfg within the duration of the reel pulse being input through the irq3 pin, reeling controls, etc. can be effected. settings ? setting p13/ irq3 pin as the irq3 pin ? set the pmr13 bit (bit 3) of the port mode register 1 (pmr1) to 1. see section 6.2.6, port mode register (pmr1). ? setting the timer r mode register 1 (tmrm1) ? clr2 bit (bit 7) = 1: works to clear after making the tmru-2 capture. ? ps21 and ps20 (bits 3 and 2) = (0 and 0): the underflowing signals of the tmru-1 are to be used as the clock source for the tmru-2. ? rld/cap bit (bit 1) = 1: the tmru-1 has been set to make the capturing operation. ? cps bit (bit 0) = 1: the edge of the irq3 signal is to be used as the capture signal for the tmru-1 and tmru-2. ? setting the timer r mode register 2 (tmrm2) ? lat bit (bit 7) = 1: the edge of the irq3 signal is to be used as the capture signal for the tmru-1 and tmru-2. ? ps11 and ps10 (bits 6 and 5) = (0 and 0): the rising edge of the cfg signal is to be used as the clock source for the tmru-1. ? cp/slm bit (bit 2) = 0: the capture signal is to work to issue the tmri3 interrupt request. section 15 timer r rev.2.00 jan. 15, 2007 page 310 of 1174 rej09b0329-0200 15.5.3 slow tracking mono-multi function when performing slow reproductions or still reproductions, the braking timing for the capstan motor is determined by use of the edge of the dvctl signal. the slow tracking mono-multi function works to measure the time from the leading edge of the dvctl signal down to the desired point to issue the interrupt request. in actual programming, this interrupt should be used to activate the brake of the caps tan motor. the tmru-3 should be used to perform time measurements for the slow tracking mono-multi function. also, the braking process can be made using the tmru-2. settings ? setting the timer r mode register 2 (tmrm2) ? ps31 and ps30 (bits 4 and 3) = other than (0, 0): the dividing clock is to be used as the clock source for the tmru-3. ? cp/slm bit (bit 2) = 1: the slow tracking delay signal is to work to issue the tmri3 interrupt request. ? setting the timer r load register 3 (tmrl3) ? set the slow tracking delay value. when the delay count is n, the set value should be (n ? 1). ? regarding the delaying duration, see figure 15.2. section 15 timer r rev.2.00 jan. 15, 2007 page 311 of 1174 rej09b0329-0200 15.5.4 acceleration and braking processes of the capstan motor when making intermittent movements such as those for slow reproductions or for still reproductions, it is necessary to conduct quick accelerations and abrupt stoppings of the capstan motor. the acceleration and braking processes will function to check if the revolution of a capstan motor has reached the prescribed rate when accelerated or braked . for this purpose, the tmru-2 (reloading function) should be used. the acceleration and braking processes should be employed when making special reproductions, in combination with the slow tracking mono-multi function. settings for the acceleration process ? setting the timer r mode register 1 (tmrm1) ? ac/br bit (bit 6) = 1: acceleration process ? rld bit (bit 5) = 1: the tmru-2 is to be used as the reload timer. ? rlck bit (bit 4) = 0: the tmru-2 is to reload at the rising edge of the cfg. ? ps21 and ps20 (bits 3 and 2) = other than (0, 0): the dividing clock is to be used as the clock source for the tmru-2. ? setting the timer r load register 2 (tmrl2) ? set the count reading for the duration until the acceleration process finishes. when the count is n, the set value should be (n ? 1). ? regarding the duration until the acceleration process finishes, see figure 15.2. settings for the braking process ? setting the timer r mode register 1 (tmrm1) ? ac/br bit (bit 6) = 0: braking process ? rld bit (bit 5) = 1: the tmru-2 is to be used as the reload timer. ? rlck bit (bit 4) = 0: the tmru-2 is to reload at the rising edge of the cfg. ? ps21 and ps20 (bits 3 and 2) = other than (0, 0): the dividing clock is to be used as the clock source for the tmru-2. ? setting the timer r load register 2 (tmrl2) ? set the count reading for the duration until the braking process finishes. when the count is n, the set value should be (n ? 1). ? regarding the duration until the braking process finishes, see figure 15.2. section 15 timer r rev.2.00 jan. 15, 2007 page 312 of 1174 rej09b0329-0200 section 16 timer x1 rev.2.00 jan. 15, 2007 page 313 of 1174 rej09b0329-0200 section 16 timer x1 note: the timer x1 is not (incorporated in) provided for the h8s/2197s and h8s/2196s. 16.1 overview timer x1 is capable of outputting two different types of independent waveforms using a 16-bit free running counter (frc) as the basic means and it is also applicable to measurements of the durations of input pulses and the cycles external clocks. 16.1.1 features timer x1 has the following features: ? four different types of counter inputting clocks. three different types of internal clocks ( /4, /16 and /64) and the dvcfg. ? two independent output comparing functions capable of outputting two different types of independent waveforms. ? four independent input capturing functions the rising edge or falling edge can be selected for use. the buffer operation can also be designated. ? counter clearing designation is workable. the counter readings can be cleared by compare match a. ? seven types of interrupt causes comparing match 2 causes, input capture 4 causes and overflow 1 cause are available for use and they can make respective interrupt requests independently. section 16 timer x1 rev.2.00 jan. 15, 2007 page 314 of 1174 rej09b0329-0200 16.1.2 block diagram figure 16.1 shows a block diagram of the timer x1. internal data bus le g end: tier icra icrb icrc icrd tcrx ocrb comparison circuit frc comparison circuit ocra tocr tcsrx tier input capture control output comparin g output interrupt request 7 ftoa ftob ftia * (hsw) ftib * (vd) ftic * (dvctl) ftid * (nhsw) (dvcfg) /4 /16 /64 tcsrx frc ocra ocrb tcrx tocr icra icrb icrc icrd : timer interrupt enablin g re g ister : timer control/status re g ister x : free runnin g counter : output comparin g re g ister a : output comparin g re g ister b : timer control re g ister x : output comparin g control re g ister : input capture re g ister a : input capture re g ister b : input capture re g ister c : input capture re g ister d note: * stands for the external terminal. ( ) stands for the internal si g nal. figure 16.1 block diagram of timer x1 section 16 timer x1 rev.2.00 jan. 15, 2007 page 315 of 1174 rej09b0329-0200 16.1.3 pin configuration table 16.1 shows the pin configuration of timer x1. table 16.1 pin configuration name abbrev. i/o function output comparing a output-pin ftoa output output pin for the output comparing a output comparing b output-pin ftob output output pin for the output comparing b input capture a input-pin ftia input input-pin for the input capture a input capture b input-pin ftib input input-pin for the input capture b input capture c input-pin ftic input input-pin for the input capture c input capture d input-pin ftid input input-pin for the input capture d section 16 timer x1 rev.2.00 jan. 15, 2007 page 316 of 1174 rej09b0329-0200 16.1.4 register configuration table 16.2 shows the register configuration of timer x1. table 16.2 register configuration name abbrev. r/w initial value address * 3 timer interrupt enabling register tier r/w h'00 h'd100 timer control/status register x tcsrx r/ (w) * 1 h'00 h'd101 free running counter h frch r/w h'00 h'd102 free running counter l frcl r/w h'00 h'd103 output comparing register ah ocrah r/w h'ff h'd104 * 2 output comparing register al ocral r/w h'ff h'd105 * 2 output comparing register bh ocrbh r/w h'ff h'd104 * 2 output comparing register bl ocrbl r/w h'ff h'd105 * 2 timer control register x tcrx r/w h'00 h'd106 timer output comparing control register tocr r/w h'00 h'd107 input capture register ah icrah r h'00 h'd108 input capture register al icral r h'00 h'd109 input capture register bh icrbh r h'00 h'd10a input capture register bl icrbl r h'00 h'd10b input capture register ch icrch r h'00 h'd10c input capture register cl icrcl r h'00 h'd10d input capture register dh icrdh r h'00 h'd10e input capture register dl icrdl r h'00 h'd10f notes: 1. only 0 can be written to clear the flag for bits 7 to 1. bit 0 is readable/writable. 2. the addresses of the ocra and ocrb are the same. changeover between them are to be made by use of the tocr bit and ocrs bit. 3. lower 16 bits of the address. section 16 timer x1 rev.2.00 jan. 15, 2007 page 317 of 1174 rej09b0329-0200 16.2 register descriptions 16.2.1 free running counter (frc) free running counter h (frch) free running counter l (frcl) 0 3 0 r/w 5 0 r/w 7 0 9 0 r/w 11 0 13 0 15 r/w r/w r/w 0 r/w r/w 1 0 2 0 r/w 4 0 r/w 6 0 8 0 r/w 10 0 12 0 14 frc frch frcl r/w r/w r/w r/w 0 r/w 0 bit : initial value : r/w : the frc is a 16-bit read/write up-counter which counts up by the inputting internal clock/external clock. the inputting clock is to be selected from the cks1 and cks0 of the tcrx. by the setting of the cclra bit of the tcsrx, the frc can be cleared by comparing match a. when the frc overflows (h'ffff h'0000), the ovf of the tcsrx will be set to 1. at this time, when the ovie of the tier is being set to 1, an interrupt request will be issued to the cpu. reading/writing can be made from and to the frc through the cpu at 8-bit or 16-bit. the frc is initialized to h'0000 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode. 16.2.2 output comparing registers a and b (ocra and ocrb) output comparing register ah and bh (ocrah and ocrbh) output comparing register al and bl (ocral and ocrbl) 1 3 1 r/w 5 1 r/w 7 1 9 1 r/w 11 1 13 1 15 r/w r/w r/w 1 r/w r/w 1 1 2 1 r/w 4 1 r/w 6 1 8 1 r/w 10 1 12 1 14 ocra, ocrb ocrah, ocrbh ocral, ocrbl r/w r/w r/w r/w 1 r/w 0 bit : initial value : r/w : the ocr consists of twin 16-bit read/write registers (ocra and ocrb). the contents of the ocr are always being compared with the frc and, when the value of these two match, the ocfa and ocrb of the tcsrx will be set to 1. at this time, if the ociae and ocib of the tier are section 16 timer x1 rev.2.00 jan. 15, 2007 page 318 of 1174 rej09b0329-0200 being set to 1, an interrupt request will be issued to the cpu. when performing compare matching, if the oea and oeb of the tocr are set to 1, the level value set to the olvla and olvlb of the to cr will be output through the ftoa and ftob pins. after resetting, 0 will be output through the ftoa and ftob pins until the first compare matching occurs. reading/writing can be made from and to the ocr through the cpu at 8-bit or 16-bit. the ocr is cleared to h'ffff when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode. 16.2.3 input capture registers a through d (icra through icrd) input capture register ah to dh (icrah to icrdh) input capture register al to dl (icral to icrdl) 0 3 0 r 5 0 r 7 0 9 0 r 11 0 13 0 15 r r r 0 rr 1 0 2 0 r 4 0 r 6 0 8 0 r 10 0 12 0 14 icra, icrb, icrc, icrd icrah, icrbh, icrch, icrdh icral, icrbl, icrcl, icrdl r r r r 0 r 0 bit : initial value : r/w : the icr consists of four 16-bit read-only registers (icra through icrd). when the falling edge of the input capture input signal is detected, the value is transferred to the icra through icrd. the icfa through icfd of the tcsrx are set to 1 simultaneously. if the idiae through idide of the tcrx are all set to 1, an interrupt request will be issued to the cpu. the edge of the input signal can be selected by setting the iedga through iedgd of the tcrx. the icrc and icrd can also be used as the bu ffer register, of the icra and icrb, respectively by setting the bufea and bufeb of the tcrx to perform buffer operations. figure 16.2 shows the connections necessary when using the icrc as the buffer register of the icra. (bufea = 1) when the icrc is used as the buffer of the icra, by setting iedga iedgc, both of the rising and falling edges can be designated for use. in case of iedga = iedgc, either one of the rising edge or the falling edge only is usable. regarding selection of the input signal edge, see table 16.3. note: transference from the frc to the icr will be performed regardless of the value of the icf. section 16 timer x1 rev.2.00 jan. 15, 2007 page 319 of 1174 rej09b0329-0200 ed g e detection and capture si g nal g eneratin g circuit. bufea iedga ftia iedgc icrc icra frc figure 16.2 buffer operation (example) table 16.3 input signal edge selection when making buffer operation iedga iedgc selection of the input signal edge 0 captures at the falling edge of the input capture input a (initial value) 0 1 1 0 captures at both rising and falling edges of the input capture input a 1 captures at the rising edge of the input capture input a reading can be made from the icr through the cpu at 8-bit or 16-bit. for stable input capturing operation, maintain the pulse duration of the input capture input signals at 1.5 system clock ( ) or more in case of single edge capturing and at 2.5 system clock ( ) or more in case of both edge capturing. the icr is initialized to h'0000 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode. 16.2.4 timer interrupt enabling register (tier) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 5 0 6 0 7 r/w r/w r/w icice r/w icibe 0 r/w iciae icide ociae ocibe ovie icsa bit : initial value : r/w : the tier is an 8-bit read/write register that controls permission/prohibition of interrupt requests. the tier is initialized to h'00 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode. section 16 timer x1 rev.2.00 jan. 15, 2007 page 320 of 1174 rej09b0329-0200 bit 7 ? enabling the input capture interrupt a (iciae): this bit works to permit/prohibit interrupt requests (icia) by the icfa when the icfa of the tcsrx is being set to 1. bit 7 iciae description 0 prohibits interrupt requests (icia) by the icfa (initial value) 1 permits interrupt requests (icia) by the icfa bit 6 ? enabling the input capture interrupt b (icibe): this bit works to permit/prohibit interrupt requests (icib) by the icfb when the icfb of the tcsrx is being set to 1. bit 6 icibe description 0 prohibits interrupt requests (icib) by the icfb (initial value) 1 permits interrupt requests (icib) by the icfb bit 5 ? enabling the input capture interrupt c (icice): this bit works to permit/prohibit interrupt requests (icic) by the icfc when the icfc of the tcsrx is being set to 1. bit 5 icice description 0 prohibits interrupt requests (icic) by the icfc (initial value) 1 permits interrupt requests (icic) by the icfc bit 4 ? enabling the input capture interrupt d (icide): this bit works to permit/prohibit interrupt requests (icid) by the icfd when the icfd of the tcsrx is being set to 1. bit 4 icide description 0 prohibits interrupt requests (icid) by the icfd (initial value) 1 permits interrupt requests (icid) by the icfd section 16 timer x1 rev.2.00 jan. 15, 2007 page 321 of 1174 rej09b0329-0200 bit 3 ? enabling the output comparing interrupt a (ociae): this bit works to permit/prohibit interrupt requests (ocia) by the ocfa when the ocfa of the tcsrx is being set to 1. bit 3 ociae description 0 prohibits interrupt requests (ocia) by the ocfa (initial value) 1 permits interrupt requests (ocia) by the ocfa bit 2 ? enabling the output comparing interrupt b (ocibe): this bit works to permit/prohibit interrupt requests (ocib) by the ocfb when the ocfb of the tcsrx is being set to 1. bit 2 ocibe description 0 prohibits interrupt requests (ocib) by the ocfb (initial value) 1 permits interrupt requests (ocib) by the ocfb bit 1 ? enabling the timer overflow interrupt (ovie): this bit works to permit/prohibit interrupt requests (fovi) by the ovf when the ovf of the tcsrx is being set to 1. bit 1 ovie description 0 prohibits interrupt requests (fovi) by the ovf (initial value) 1 permits interrupt requests (fovi) by the ovf bit 0 ? selecting the input capture a signals (icsa): this bit works to select the input capture a signals. bit 0 icsa description 0 selects the ftia pin for inputting of the input capture a signals (initial value) 1 selects the hsw for inputting of the input capture a signals section 16 timer x1 rev.2.00 jan. 15, 2007 page 322 of 1174 rej09b0329-0200 16.2.5 timer control/status register x (tcsrx) 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 r/w r/(w) * icfb 0 r/(w) * icfa r/(w) * icfd r/(w) * icfc r/(w) * ocfb r/(w) * ocfa cclra r/(w) * ovf note: * only 0 can be written to clear the fla g for bits 7 to 1. bit : initial value : r/w : the tcsrx is an 8-bit register which works to select counter clearing timing and to control respective interrupt requesting signals. the tcsrx is initialized to h'00 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode. meanwhile, as for the timing, see section 16.3, operation. the ftia through ftid pins are for fixed inputs inside the lsi under the low power consumption mode excluding the sleep mode. consequen tly, when such shifts as active mode low power consumption mode active mode are made, wrong edges may be detected depending on the pin status or on the type of the detecting edge. to avoid such error, clear the interrupt requesti ng flag once immediately after shifting to the active mode from the low power consumption mode. bit 7 ? input capture flag a (icfa): this is a status flag indicating the fact that the value of the frc has been transferred to th e icra by the input capture signals. when the bufea of the tcrx is being set to 1, the icfa indicates the status that the frc value has been transferred to the icra by the input capture signals and that the icra value before being updated has been transferred to the icrc. this flag should be cleared by use of of the so ftware. such setting should only be made by use of the hardware. it is not possible to make this setting using a software. bit 7 icfa description 0 [clearing condition] (initial value) when 0 is written into the icfa after reading the icfa under the setting of icfa = 1 1 [setting condition] when the value of the frc has been transferred to the icra by the input capture signals section 16 timer x1 rev.2.00 jan. 15, 2007 page 323 of 1174 rej09b0329-0200 bit 6 ? input capture flag b (icfb): this status flag indicates th e fact that the value of the frc has been transferred to the icrb by the i nput capture signals. when the bufeb of the tcrx is being set to 1, the icfb indicates the status that the frc value has been transferred to the icrb by the input capture signals and that the i crb value before being updated has been transferred to the icrc. this flag should be cleared by use of the softwa re. such setting should only be made by use of the hardware. it is not possible to make this setting using a software. bit 6 icfb description 0 [clearing condition] (initial value) when 0 is written into the icfb after reading the icfb under the setting of icfb = 1 1 [setting condition] when the value of the frc has been transferred to the icrb by the input capture signals bit 5 ? input capture flag c (icfc): this status flag indicates th e fact that the value of the frc has been transferred to the icrc by the i nput capture signals. when an input capture signal occurs while the bufea of the tcrx is being set to 1, although the icfc will be set out, data transference to the icrc will not be performed. therefore, in buffer operation, the icfc can be used as an external interrupt by setting the icice bit to 1. this flag should be cleared by use of the softwa re. such setting should only be made by use of the hardware. it is not possible to make this setting using a software. bit 5 icfc description 0 [clearing condition] (initial value) when 0 is written into the icfc after reading the icfc under the setting of icfc = 1 1 [setting condition] when the input capture signal has occurred section 16 timer x1 rev.2.00 jan. 15, 2007 page 324 of 1174 rej09b0329-0200 bit 4 ? input capture flag d (icfd): this status flag indicates th e fact that the value of the frc has been transferred to the icrd by the input capture signals. when an input capture signal occurs while the bufeb of the tcrx is being set to 1, although the icfd will be set out, data transference to the icrd will not be performed. therefore, in buffer operation, the icfd can be used as an external interrupt by setting the icide bit to 1. this flag should be cleared by use of the softwa re. such setting should only be made by use of the hardware. it is not possible to make this setting using a software. bit 4 icfd description 0 [clearing condition] (initial value) when 0 is written into the icfd after reading the icfd under the setting of icfd = 1 1 [setting condition] when the input capture signal has occurred bit 3 ? output comparing flag a (ocfa): this status flag indicates the fact that the frc and the ocra have come to a comparing match. this flag should be cleared by use of the softwa re. such setting should only be made by use of the hardware. it is not possible to make this setting using a software. bit 3 ocfa description 0 [clearing condition] (initial value) when 0 is written into the ocfa after reading the ocfa under the setting of ocfa = 1 1 [setting condition] when the frc and the ocra have come to the comparing match section 16 timer x1 rev.2.00 jan. 15, 2007 page 325 of 1174 rej09b0329-0200 bit 2 ? output comparing flag b (ocfb): this status flag indicates the fact that the frc and the ocrb have come to a comparing match. this flag should be cleared by use of the softwa re. such setting should only be made by use of the hardware. it is not possible to make this setting using a software. bit 2 ocfb description 0 [clearing condition] (initial value) when 0 is written into the ocfb after reading the ocfb under the setting of ocfb = 1 1 [setting condition] when the frc and the ocrb have come to the comparing match bit 1 ? timer over flow (ovf): this is a status flag indi cating the fact that the frc overflowed. (h'ffff h'0000). this flag should be cleared by use of the softwa re. such setting should only be made by use of the hardware. it is not possible to make this setting using a software. bit 1 ovf description 0 [clearing condition] (initial value) when 0 is written into the ovf after reading the ovf under the setting of ovf = 1 1 [setting condition] when the frc value has become h'ffff h'0000 bit 0 ? counter clearing (cclra): this bit works to select if or not to clear the frc by occurrence of comparing match a (matching signal of the frc and ocra). bit 0 cclra description 0 prohibits clearing of the frc by occurrence of comparing match a (initial value) 1 permits clearing of the frc by occurrence of comparing match a section 16 timer x1 rev.2.00 jan. 15, 2007 page 326 of 1174 rej09b0329-0200 16.2.6 timer control register x (tcrx) 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 r/w r/w iedgb 0 r/w iedga r/w iedgd r/w iedgc r/w bufeb r/w bufea cks0 r/w cks1 bit : initial value : r/w : the tcrx is an 8-bit read/write register that selects the input capture signal edge, designates the buffer operation, and selects the inputting clock for the frc. the tcrx is initialized to h'00 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode. bit 7 ? input capture signal edge selection a (iedga): this bit works to select the rising edge or falling edge of the input capture signal a (ftia). bit 7 iedga description 0 captures the falling edge of the input capture signal a (initial value) 1 captures the rising edge of the input capture signal a bit 6 ? input capture signal edge selection b (iedgb): this bit works to select the rising edge or falling edge of the input capture signal b (ftib). bit 6 iedgb description 0 captures the falling edge of the input capture signal b (initial value) 1 captures the rising edge of the input capture signal b bit 5 ? input capture signal edge selection c (iedgc): this bit works to select the rising edge or falling edge of the input capture signal c (ftic). however, when the dvctl has been selected as the signal for the input capture signal edge selection c, this bit will not influence the operation. bit 5 iedgc description 0 captures the falling edge of the input capture signal c (initial value) 1 captures the rising edge of the input capture signal c section 16 timer x1 rev.2.00 jan. 15, 2007 page 327 of 1174 rej09b0329-0200 bit 4 ? input capture signal edge selection d (iedgd): this bit works to select the rising edge or falling edge of the input capture signal d (ftid). bit 4 iedgd description 0 captures the falling edge of the input capture signal d (initial value) 1 captures the rising edge of the input capture signal d bit 3 ? buffer enabling a (bufea): this bit works to select whether or not to use the icrc as the buffer register for the icra. bit 3 bufea description 0 not using the icrc as the buffer register for the icra (initial value) 1 using the icrc as the buffer register for the icra bit 2 ? buffer enabling b (bufeb): this bit works to select whether or not to use the icrd as the buffer register for the icrb. bit 2 bufeb description 0 not using the icrd as the buffer register for the icrb (initial value) 1 using the icrd as the buffer register for the icrb bits 1 and 0 ? clock select (cks1, cks0): these bits work to select the inputting clock to the frc from among three types of internal clocks and the dvcfg. the dvcfg is the edge detecting pulse selected by the cfg dividing timer. bit 1 bit 0 cks1 cks0 description 0 0 internal clock: counts at /4 (initial value) 0 1 internal clock: counts at /16 1 0 internal clock: counts at /64 1 1 dvcfg: the edge detecting pulse selected by the cfg dividing timer section 16 timer x1 rev.2.00 jan. 15, 2007 page 328 of 1174 rej09b0329-0200 16.2.7 timer output comparing control register (tocr) 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 r/w r/w icsc 0 r/w icsb r/w ocrs r/w icsd r/w oeb r/w oea olvlb r/w olvla bit : initial value : r/w : the tocr is an 8-bit read/write register that select input capture signals and output comparing output level, permits output comp aring outputs, and controls switching over of the access of the ocra and ocrb. see section 16.2.4, timer interrupt enabling register (tier) regarding the input capture inputs a. the tocr is initialized to h'00 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode. bit 7 ? selecting the input capture b signals (icsb): this bit works to select the input capture b signals. bit 7 icsb description 0 selects the ftib pin for inputting of the input capture b signals (initial value) 1 selects the vd as the input capture b signals bit 6 ? selecting the input capture c signals (icsc): this bit works to select the input capture c signals. the dvctl is the edge detecting pulse selected by the ctl dividing timer. bit 6 icsc description 0 selects the ftic pin for inputting of the input capture c signals (initial value) 1 selects the dvctl as the input capture c signals bit 5 ? selecting the input capture d signals (icsd): this bit works to select the input capture d signals. bit 5 icsd description 0 selects the ftid pin for inputting of the input capture d signals (initial value) 1 selects the nhsw as the input capture d signals section 16 timer x1 rev.2.00 jan. 15, 2007 page 329 of 1174 rej09b0329-0200 bit 4 ? selecting the output comparing register (ocrs): the addresses of the ocra and ocrb are the same. the ocrs wo rks to control which register to choose when reading/writing this address. the choice will not influence the operation of the ocra and ocrb. bit 4 ocrs description 0 selects the ocra register (initial value) 1 selects the ocrb register bit 3 ? enabling the output a (oea): this bit works to control the output comparing a signals. bit 3 oea description 0 prohibits the output comparing a signal outputs (initial value) 1 permits the output comparing a signal outputs bit 2 ? enabling the output b (oeb): this bit works to control the output comparing b signals. bit 2 oeb description 0 prohibits the output comparing b signal outputs (initial value) 1 permits the output comparing b signal outputs bit 1 ? output level a (olvla): this bit works to select the output level to output through the ftoa pin by use of the comparing match a (matching signal between the frc and ocra). bit 1 olvla description 0 low level (initial value) 1 high level section 16 timer x1 rev.2.00 jan. 15, 2007 page 330 of 1174 rej09b0329-0200 bit 0 ? output level b (olvlb): this bit works to select the output level to output through the ftob pin by use of the comparing match b (matching signal between the frc and ocrb). bit 0 olvlb description 0 low level (initial value) 1 high level 16.2.8 module stop control register (mstpcr) 7 0 mstp15 r/w mstpcrh 6 0 mstp14 r/w 5 1 mstp13 r/w 4 1 mstp12 r/w 3 1 mstp11 r/w 2 1 mstp10 r/w 1 1 mstp9 r/w 0 1 mstp8 r/w 7 1 mstp7 r/w 6 1 mstp6 r/w 5 1 mstp5 r/w 4 1 mstp4 r/w 3 1 mstp3 r/w 2 1 mstp2 r/w 1 1 mstp1 r/w 0 1 mstp0 r/w mstpcrl initial value : r/w : bit : the mstpcr consists of twin 8-bit read/write registers that control the module stop mode. when the mstp10 bit is set to 1, the timer x1 stops its operation at the ending point of the bus cycle to shift to the module stop mode. for more information, see section 4.5, module stop mode. when reset, the mstpcr is initialized to h'ffff. bit 2 ? module stop (mstp10): this bit works to designate the module stop mode for timer x1. mstpcrh bit 2 mstp10 description 0 cancels the module stop mode of the timer x1 1 sets the module stop mode of the timer x1 (initial value) section 16 timer x1 rev.2.00 jan. 15, 2007 page 331 of 1174 rej09b0329-0200 16.3 operation 16.3.1 operation of timer x1 ? output comparing operation right after resetting, the frc is initialized to h'0000 to start counting up. the inputting clock can be selected from among three different types of internal clocks or the external clock by setting the cks1 and cks0 of the tcrx. the contents of the frc are always being comp ared with the ocra and ocrb and, when the value of these two match, the level set by the the olvla and olvlb of the tocr is output through the ftoa pin and ftob pin. after resetting, 0 will be output through the ftoa and ftob pins until the first compare matching occurs. also, when the cclra of the tcsrx is being set to 1, the frc will be cleared to h'0000 when the comparing match a occurs. ? input capturing operation right after resetting, the frc is initialized to h'0000 to start counting up. the inputting clock can be selected from among three different types of internal clocks or the external clock by setting the cks1 and cks0 of the tcrx. the inputs are transferred to the iedga th rough iedgd of the tcrx through the ftia through ftid pins and, at the same time, the icfa through icfd of the tcsrx are set to 1. at this time, if the iciae through icied of the tier are being set to 1, due interrupt request will be issued to the cpu. when the bufea and bufeb of the tcrx are se t to 1, the icrc and icrd work as the buffer register, respectively, of the icra and icrb. when the edge selected by setting the iedga through iedgd of the tcrx is input thro ugh the ftia and ftib pins, the value at the time of the frc is transferred to the icra and icrb and, at the same time, the values of the icra and icrb before updating are transferred to the icrc and icrd. at this time, when the icfa and icfb are being set to 1 and if the iciae and icibe of the tier are being set to 1, due interrupt request will be issued to the cpu. section 16 timer x1 rev.2.00 jan. 15, 2007 page 332 of 1174 rej09b0329-0200 16.3.2 counting timing of the frc the frc is counted up by the inputting clock. by setting the cks1 and cks0 of the tcrx, the inputting clock can be selected from among three different types of clocks ( /4, /16 and /64) and the dvcfg. ? internal clock operation by setting the cks1 and cks0 bits of the tcrx, three types of internal clocks ( /4, /16 and /64), generated by dividing the system clock ( ) can be selected. figure 16.3 shows the timing chart. frc internal clock frc input clock n n ? 1 n + 1 figure 16.3 count timing for internal clock operation ? dvcfg clock operation by setting the cks1 and cks0 bits of the tcrx to 1, dvcfg clock input can be selected. the dvcfg clock makes counting by use of the edge detecting pulse being selected by the cfg dividing timer. figure 16.4 shows the timing chart. frc cfg frc input clock n n + 1 dvcfg figure 16.4 count timing for cfg clock operation section 16 timer x1 rev.2.00 jan. 15, 2007 page 333 of 1174 rej09b0329-0200 16.3.3 output comparing signal outputting timing when a comparing match occurs, the output level having been set by the olvl of the tocr is output through the output comparing signal outputting pins (ftoa and ftob). figure 16.5 shows the timing chart for the output comparing signal outputting a. frc olvla ftoa output comparing signal outputting a pin n n clearing * n n n + 1 n + 1 comparing match signal ocra note: * execution of the command is to be designated by the software. figure 16.5 output comparing signal outputting a timing 16.3.4 frc clearing timing the frc can be cleared when th e comparing match a occurs. figure 16.6 shows the timing chart. frc comparing match a signal n h' 0000 figure 16.6 clearing timing by occurrence of the comparing match a section 16 timer x1 rev.2.00 jan. 15, 2007 page 334 of 1174 rej09b0329-0200 16.3.5 input capture signal inputting timing ? input capture signa l inputting timing as for the input capture signal inputting, rising or falling edge is selected by settings of the iedga through iedgd bits of the tcrx. figure 16.7 shows the timing chart when the rising edge is selected (iedga through iedgd = 1). input capture signal inputting pin input capture signal figure 16.7 input capture signal inputting timing (under normal state) ? input capture signal inputting timi ng when making buffer operation buffer operation can be made using the icrc or icrd as the buffer of the icra or icrb. figure 16.8 shows the input capture signal inputting timing chart in case both of the rising and falling edges are designated (iedga = 1 and iedgc = 0, or iedga = 0 and iedgc = 1), using the icrc as the buffer register for the icra (bufea = 1). input capture signal ftia frc icra icrc n n + 1 n mn mm n m n n figure 16.8 input capture signal inputting timing chart under the buffer mode (under normal state) section 16 timer x1 rev.2.00 jan. 15, 2007 page 335 of 1174 rej09b0329-0200 even when the icrc or icrd is used as the buffer register, the i nput capture flag will be set up corresponding to the designated edge cha nge of respective input capture signals. for example, when using the icrc as the buffer register for th e icra, when an edge change having been designated by the iedgc bit is detected with the input capture signals c and if the iciec bit is duly set, an interrupt request will be issued. however, in this case, the frc value will not be transferred to the icrc. 16.3.6 input capture flag (icfa through icfd) setting up timing the input capture signal works to set the icfa through icfd to 1 and, simultaneously, the frc value is transferred to the corresponding icra through icrd. figure 16.9 shows the timing chart. input capture signal icfa to icfd icra to icrd frc n n figure 16.9 icfa through icfd setting up timing section 16 timer x1 rev.2.00 jan. 15, 2007 page 336 of 1174 rej09b0329-0200 16.3.7 output comparing flag (ocfa and ocfb) setting up timing the ocfa and ocfb are being set to 1 by the comparing match signal being output when the values of the ocra, ocrb and frc match. the comparing match signal is generated at the last state of the value match (the timing of the frc's updating the matching count reading). after the values of the ocra, ocrb and frc match, up until the count up clock signal is generated, the comparing match signal will not be issued. figure 16.10 shows the ocfa and ocfb setting timing chart. comparing match signal ocfa, ocfb ocra, ocrb frc n n n + 1 figure 16.10 ocf setting up timing 16.3.8 overflow flag (cvf) setting up timing the ovf is set to when the frc overflows (h'ffff h'0000). figure 16.11 shows the timing chart. overflowing signal frc h'ffff h'0000 ovf figure 16.11 ovf setting up timing section 16 timer x1 rev.2.00 jan. 15, 2007 page 337 of 1174 rej09b0329-0200 16.4 operation mode of timer x1 table 16.4 indicated below shows the operation mode of timer x1. table 16.4 operation mode of timer x1 operation mode reset active sleep watch subactive standby subsleep module stop frc reset functions functions reset reset reset reset reset ocra, ocrb reset functions functions reset reset reset reset reset icra to icrd reset functions functions reset reset reset reset reset tier reset functions functions reset reset reset reset reset tcrx reset functions functions reset reset reset reset reset tocr reset functions functions reset reset reset reset reset tcsrx reset functions functions reset reset reset reset reset 16.5 interrupt causes total seven interrupt causes exist with timer x1, namely, icia through icid, ocia, ocib and fovi. table 16.5 lists the contents of interrupt causes. interrupt requests can be permitted or prohibited by setting interrupt enabling bits of the tier. also, independent vector addresses are allocated to respective interrupt causes. table 16.5 interrupt causes of timer x1 abbreviations of the interrupt ca uses priority degree contents icia interrupt request by the icfa icib interrupt request by the icfb icic interrupt request by the icfc icid interrupt request by the icfd ocia interrupt request by the ocfa ocib interrupt request by the ocfb fovi interrupt request by the ovf high low section 16 timer x1 rev.2.00 jan. 15, 2007 page 338 of 1174 rej09b0329-0200 16.6 exemplary uses of timer x1 figure 16.12 shows an example of outputting at optional phase difference of the pulses of the 50% duty. for this setting, follow the procedures listed below. 1. set the cclra bit of the tcsrx to 1. 2. each time a comparing match o ccurs, the olvla bit and the ol vlb bit are reversed by use of the software. h'ffff ocra ocrb h'0000 ftoa ftob clearing the counter frc figure 16.12 pulse outputting example section 16 timer x1 rev.2.00 jan. 15, 2007 page 339 of 1174 rej09b0329-0200 16.7 precautions when using timer x1 pay great attention to the fact that the following competitions and operations occur during operation of timer x1. 16.7.1 competition between writin g and clearing with the frc when a counter clearing signal is issued under the t2 state where the frc is under the writing cycle, writing into the frc will not be effected and the priority will be given to clearing of the frc. figure 16.13 shows the timing chart. address frc address internal writing signal counter clearing signal frc n h'0000 t1 t2 writing cycle with the frc figure 16.13 competition between writing and clearing with the frc section 16 timer x1 rev.2.00 jan. 15, 2007 page 340 of 1174 rej09b0329-0200 16.7.2 competition between writin g and counting up with the frc when a counting up cause occurs under the t2 st ate where the frc is unde r the writing cycle, the counting up will not be effected and the priority will be given to count writing. figure 16.14 shows the timing chart. address frc address internal writing signal inputting clock to the frc writing data frc n m t1 t2 writing cycle with the frc figure 16.14 competition between writing and counting up with the frc section 16 timer x1 rev.2.00 jan. 15, 2007 page 341 of 1174 rej09b0329-0200 16.7.3 competition between writing and comparing match with the ocr when a comparing match occurs under the t2 state where the ocra and ocrb are under the writing cycle, the priority will be given to writing of the ocr and the comparing match signal will be prohibited. figure 16.15 shows the timing chart. address ocr address internal writing signal comparing match signal frc writing data will be prohibited ocr n m n n + 1 t1 t2 writing cycle with the ocr figure 16.15 competition between writing and comparing match with the ocr section 16 timer x1 rev.2.00 jan. 15, 2007 page 342 of 1174 rej09b0329-0200 16.7.4 changing over the internal clocks and counter operations depending on the timing of changing over the internal clocks, the frc may count up. table 16.6 shows the relations between the timing of changing over the internal clocks (re-writing of the cks1 and cks0) and the frc operations. when using an internal clock, the counting clock is being generated detecting the falling edge of the internal clock dividi ng the system clock ( ). for this reason, like item no. 3 of table 16.6, count clock signals are issued deeming the timing before the changeover as the falling edge to have the frc to count up. also, when changing over between an internal clock and the external clock, the frc may count up. table 16.6 changing over the intern al clocks and the frc operation no. rewriting timing for the cks1 and cks0 frc operation 1 low low level changeover clock before the changeover clock after the changeover count clock frc rewriting of the cks1 and cks0 n n + 1 2 low high level changeover clock before the changeover clock after the changeover count clock frc rewriting of the cks1 and cks0 n n + 1 n + 2 section 16 timer x1 rev.2.00 jan. 15, 2007 page 343 of 1174 rej09b0329-0200 no. rewriting timing for the cks1 and cks0 frc operation 3 high low level changeover clock before the changeover clock after the changeover count clock frc rewriting of the cks1 and cks0 n * n + 1 n + 2 4 high high level changeover clock before the changeover clock after the changeover count clock frc rewriting of the cks1 and cks0 n n + 1 n + 2 note: * the count clock signals are issued determining the changeover timing as the falling edge to have the frc to count up. section 16 timer x1 rev.2.00 jan. 15, 2007 page 344 of 1174 rej09b0329-0200 section 17 watchdog timer (wdt) rev.2.00 jan. 15, 2007 page 345 of 1174 rej09b0329-0200 section 17 watchdog timer (wdt) 17.1 overview this lsi has an on-chip watchdog timer with one channel (wdt) for monitoring system operation. the wdt outputs an overflow signal if a system crash prevents the cpu from writing to the timer counter, allowing it to overflow. at the same time, the wdt can also generate an internal reset signal or internal nmi interrupt signal. when this watchdog function is not needed, the wdt can be used as an interval timer. in interval timer mode, an interval timer interrupt is generated each time the counter overflows. 17.1.1 features wdt features are listed below. ? switchable between watchdog timer mode and interval timer mode ? wovi interrupt generation in interval timer mode ? internal reset or internal interrupt generated when the timer counter overflows ? choice of internal reset or nmi interrupt generation in watchdog timer mode ? choice of 8 counter input clocks ? maximum wdt interval: system clock period 131072 256 section 17 watchdog timer (wdt) rev.2.00 jan. 15, 2007 page 346 of 1174 rej09b0329-0200 17.1 . 2 block diagram figure 17.1 shows block diagram of wdt. overflow interrupt control reset control wovi (interrupt request signal) internal reset signal * wtcnt wtcsr /2 /64 /128 /512 /2048 /8192 /32768 /131072 clock clock select internal clock source bus interface module bus wtcsr wtcnt note: * the internal reset signal can be generated by means of a register setting. : timer control/status register : timer counter internal bus wdt legend: internal nmi interrupt request signal figure 17.1 block diagram of wdt section 17 watchdog timer (wdt) rev.2.00 jan. 15, 2007 page 347 of 1174 rej09b0329-0200 17.1.3 register configuration the wdt has two registers, as described in table 17.1. these registers control clock selection, wdt mode switching, the reset signal, etc. table 17.1 wdt registers address * 1 name abbrev. r/w initial value write * 2 read watchdog timer control/status register wtcsr r/ (w) * 3 h'00 h'ffbc h'ffbc watchdog timer counter wtcnt r/w h'00 h'ffbc h'ffbd system control register syscr r/w h'09 h'ffe8 h'ffe8 notes: 1. lower 16 bits of the address. 2. for details of write operations, see section 17.2.4, notes on register access. 3. only 0 can be written in bit 7, to clear the flag. 17.2 register descriptions 17.2.1 watchdog timer counter (wtcnt) 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit : initial value : r/w : wtcnt is an 8-bit readable/writable* up-counter. when the tme bit is set to 1 in wtcsr, wtcnt starts counting pulses generated from the internal clock source selected by bits cks2 to cks0 in wtcsr. when the count overflows (changes from h'ff to h'00), the ovf flag in wtcsr is set to 1. wtcnt is initialized to h'00 by a reset, or when the tme bit is cleared to 0. note: * wtcnt is write-protected by a password to prevent accidental overwriting. for details see section 17.2.4, notes on register access. section 17 watchdog timer (wdt) rev.2.00 jan. 15, 2007 page 348 of 1174 rej09b0329-0200 17.2.2 watchdog timer control/status register (wtcsr) 7 ovf 0 r/(w) * 6 wt/ it 0 r/w 5 tme 0 r/w 4 ? 0 ? 3 rst/ nmi 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w note: * only 0 can be written to clear the flag. bit : initial value : r/w : wtcsr is an 8-bit readable/writable* register. its functions include selecting the clock source to be input to wtcnt, and the timer mode. wtcsr is initialized to h'00 by a reset. note: * wtcsr is write-protected by a password to prevent accidental overwriting. for details see section 17.2.4, notes on register access. bit 7 ? overflow flag (ovf): a status flag that indicates that wtcnt has overflowed from h'ff to h'00. bit 7 ovf description 0 [clearing conditions] (initial value) 1. write 0 in the tme bit 2. read wtcsr when ovf = 1 * , then write 0 in ovf 1 [setting condition] when wtcnt overflows (changes from h'ff to h'00) when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset note: * when ovf is polled and the interval timer interrupt is disabled, ovf=1 must be read at least twice. section 17 watchdog timer (wdt) rev.2.00 jan. 15, 2007 page 349 of 1174 rej09b0329-0200 bit 6 ? timer mode select (wt/ it ): selects whether the wdt is used as a watchdog timer or interval timer. if used as an interval timer, the wdt generates an interval timer interrupt request (wovi) when wtcnt overflows. if used as a watchdog timer, the wdt generates a reset or nmi interrupt when wtcnt overflows. bit 6 wt/ it description 0 interval timer mode: sends the cpu an interval timer interrupt request (wovi) when wtcnt overflows (initial value) 1 watchdog timer mode: sends the cpu a reset or nmi interrupt request when wtcnt overflows bit 5 ? timer enable (tme): selects whether wtcnt runs or is halted. bit 5 tme description 0 wtcnt is initialized to h'00 and halted (initial value) 1 wtcnt counts bit 4 ? reserved: this bit should not be set to 1. bit 3 ? reset or nmi (rst/ nmi ): specifies whether an internal reset or nmi interrupt is requested on wtcnt overflow in watchdog timer mode. bit 3 rst/ nmi description 0 an nmi interrupt request is generated (initial value) 1 an internal reset request is generated section 17 watchdog timer (wdt) rev.2.00 jan. 15, 2007 page 350 of 1174 rej09b0329-0200 bits 2 to 0 ? clock select 2 to 0 (cks2 to cks0): these bits select an internal clock source, obtained by dividing the system clock ( ) for input to wtcnt. wdt input clock selection bit 2 bit 1 bit 0 description csk2 csk1 csk0 clock overflow period * (when = 10 mhz) 0 /2 (initial value) 51.2 s 0 1 /64 1.6 ms 0 /128 3.3 ms 0 1 1 /512 13.1 ms 1 0 /2048 52.4 ms 0 1 /8192 209.7 ms 1 0 /32768 838.9 ms 1 /131072 3.36 s note: * the overflow period is the time from when wtcnt starts counting up from h'00 until overflow occurs. 17.2.3 system control register (syscr) 7 ? 0 ? 6 ? 0 ? 5 intm1 0 r 4 intm0 0 r/w 3 xrst 1 r 0 ? 1 ? 2 ? 0 ? 1 ? 0 ? bit : initial value : r/w : only bit 3 is described here. for details on functions not related to the watchdog timer, see sections 3.2.2 and 6.2.1, system control register (syscr), and the descriptions of the relevant modules. bit 3 ? external reset (xrst): indicates the reset source. when the watchdog timer is used, a reset can be generated by watchdog timer overflow in addition to external reset input. xrst is a read-only bit. it is set to 1 by an external reset, and cleared to 0 by watchdog timer overflow. bit 3 xrst description 0 reset is generated by watchdog timer overflow 1 reset is generated by external reset input (initial value) section 17 watchdog timer (wdt) rev.2.00 jan. 15, 2007 page 351 of 1174 rej09b0329-0200 17.2.4 notes on register access the watchdog timer's wtcnt and wtcsr registers differ from other registers in being more difficult to write to. the procedures for writing to and reading these registers are given below. ? writing to wtcnt and wtcsr these registers must be written to by a word transfer instruction. they cannot be written to with byte transfer instructions. figure 17.2 shows the format of data writte n to wtcnt and wtcs r. wtcnt and wtcsr both have the same write address. for a write to wtcnt, the upper byte of the written word must contain h'5a and the lower byte must cont ain the write data. for a write to wtcsr, the upper byte of the written word must contain h'a5 and the lower byte must contain the write data. this transfers the write data from the lower byte to wtcnt or wtcsr. section 17 watchdog timer (wdt) rev.2.00 jan. 15, 2007 page 352 of 1174 rej09b0329-0200 17.3 operation 17.3.1 watchdog timer operation to use the wdt as a watchdog timer, set the wt/ it and tme bits in wtcsr to 1. software must prevent wtcnt overflows by rewriting the wtcnt value (normally by writing h'00) before overflow occurs. this ensures that wtcnt does not overflow while the system is operating normally. if wtcnt overfl ows without being rewritten because of a system crash or other error, the chip is reset, or an nmi interrupt is generated, for 518 system clock periods (518 ). this is illustrated in figure 17.3. an internal reset request from the watchdog timer and reset input from the res pin are handled via the same vector. the reset s ource can be identified from the value of the xrst bit in syscr. if a reset caused by an input signal from the res pin and a reset caused by wdt overflow occur simultaneously, the res pin reset has priority, and the xrst bit in syscr is set to 1. wtcnt value h'00 time h'ff wt/ it = 1 tme = 1 h'00 written to wtcnt wt/ it = 1 tme = 1 h'00 written to wtcnt 518 system clock period internal reset signal wt/ it tme legend: overflow internal reset generated ovf = 1 * : timer mode select bit : timer enable bit note: * cleared to 0 by an internal reset when ovf is set to 1. xrst is cleared to 0. figure 17.3 operation in watchdog timer mode (when reset) section 17 watchdog timer (wdt) rev.2.00 jan. 15, 2007 page 353 of 1174 rej09b0329-0200 17.3.2 interval timer operation to use the wdt as an inte rval timer, clear the wt/ it bit in wtcsr to 0 and set the tme bit to 1. an interval timer interrupt (wovi) is ge nerated each time wtcnt overflows, provided that the wdt is operating as an interval timer, as shown in figure 17.4. this function can be used to generate interrupt requests at regular intervals. wtcnt value h'00 time h'ff wt/it = 0 tme = 1 wovi overflow overflow overflow overflow wovi : interval timer interrupt request generation wovi wovi wovi figure 17.4 operation in interval timer mode section 17 watchdog timer (wdt) rev.2.00 jan. 15, 2007 page 354 of 1174 rej09b0329-0200 17.3.3 timing of setting of overflow flag (ovf) the ovf bit in wtcsr is set to 1 if wtcnt overflows during interval timer operation. at the same time, an interval timer interrupt (wovi) is requested. this timing is shown in figure 17.5. if nmi request generation is selected in watchdog timer mode, when wtcnt overflows the ovf bit in wtcsr is set to 1 and at the same time an nmi interrupt is requested. ck wtcnt h'ff h'00 overflow signal (internal signal) ovf figure 17.5 timing of ovf setting 17.4 interrupts during interval timer mode operation, an overflow generates an interval timer interrupt (wovi). the interval timer interrupt is requested whenever the ovf flag is set to 1 in wtcsr. ovf must be cleared to 0 in the interrupt handling routine. when nmi interrupt request generation is selected in watchdog timer mode, an overflow generates an nmi interrupt request. section 17 watchdog timer (wdt) rev.2.00 jan. 15, 2007 page 355 of 1174 rej09b0329-0200 17 . 5 usage notes 17.5.1 contention between watchdog ti mer counter (wtcnt) write and increment if a timer counter clock pulse is generated during the t2 state of a wtcnt write cycle, the write takes priority and the timer counter is not incremented. figure 17.6 shows this operation. internal address internal internal write signal wtcnt input clock wtcnt n m t 1 t 2 wtcnt write cycle counter write data figure 17.6 contention betw een wtcnt write and increment 17.5.2 changing value of cks2 to cks0 if bits cks2 to cks0 in wtcsr are written to while the wdt is operating, errors could occur in the incrementation. software must stop the watchdog timer (by clearing the tme bit to 0) before changing the value of bits cks2 to cks0. section 17 watchdog timer (wdt) rev.2.00 jan. 15, 2007 page 356 of 1174 rej09b0329-0200 17.5.3 switching between watchdog timer mode and interval timer mode if the mode is switched from watchdog timer to interval timer, or vice versa, while the wdt is operating, correct operation cannot be guaranteed. software must stop the watchdog timer (by clearing the tme bit to 0) before switching the mode. section 18 8-bit pwm rev.2.00 jan. 15, 2007 page 357 of 1174 rej09b0329-0200 section 18 8-bit pwm 18.1 overview the 8-bit pwm incorporates 4 channels of the duty control method (h8s/2197s and h8s/2196s: 2 channels). its outputs can be used to control a reel motor or loading motor. 18.1.1 features ? conversion period: 256-state ? duty control method 18.1.2 block diagram figure 18.1 shows a block diagram of the 8-bit pwm (1 channel). pwmn 2 0 2 7 ovf match si g nal le g end: pwrn pw8cr : 8-bit pwm data re g ister n : 8-bit pwm control re g ister pwmn ovf note: n = 3 to 0 (h8s/2197s and h8s/2196s: n = 1 and 0) : 8-bit pwm square-wave output pin n : overflow si g nal from frc lower 8-bit pwrn free-runnin g counter (frc) comparator pw8cr polarity specification internal data bus r s q figure 18.1 block diagram of 8-bit pwm (1 channel) section 18 8-bit pwm rev.2.00 jan. 15, 2007 page 358 of 1174 rej09b0329-0200 18.1.3 pin configuration table 18.1 shows the 8-bit pwm pin configuration. table 18.1 pin configuration name abbrev. i/o function 8-bit pwm square-wave output pin 0 pwm0 output 8-bit pwm square-wave output 0 8-bit pwm square-wave output pin 1 pwm1 output 8-bit pwm square-wave output 1 8-bit pwm square-wave output pin 2 pwm2 output 8-bit pwm square-wave output 2 8-bit pwm square-wave output pin 3 pwm3 output 8-bit pwm square-wave output 3 18.1.4 register configuration table 18.2 shows the 8-bit pwm register configuration. table 18.2 8-bit pwm registers name abbrev. r/w size initial value address * 8-bit pwm data register 0 pwr0 w byte h'00 h'd126 8-bit pwm data register 1 pwr1 w byte h'00 h'd127 8-bit pwm data register 2 pwr2 w byte h'00 h'd128 8-bit pwm data register 3 pwr3 w byte h'00 h'd129 8-bit pwm control register pw8cr r/w byte h'f0 h'd12a port mode register 3 pmr3 r/w byte h'00 h'ffd0 note: * lower 16 bits of the address. section 18 8-bit pwm rev.2.00 jan. 15, 2007 page 359 of 1174 rej09b0329-0200 18.2 register descriptions 18.2.1 8-bit pwm data registers 0, 1, 2 and 3 (pwr0, pwr1, pwr2, pwr3) pwr0 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 pw04 pw03 pw02 pw01 pw00 0 w pw07 w w w pw06 pw05 bit : initial value : r/w : pwr1 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 pw14 pw13 pw12 pw11 pw10 0 w pw17 w w w pw16 pw15 bit : initial value : r/w : pwr2 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 pw24 pw23 pw22 pw21 pw20 0 w pw27 w w w pw26 pw25 bit : initial value : r/w : pwr3 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 pw34 pw33 pw32 pw31 pw30 0 w pw37 w w w pw36 pw35 bit : initial value : r/w : 8-bit pwm data registers 0, 1, 2 and 3 (pwr0, pwr1, pwr2, pwr3) control the duty cycle at 8- bit pwm pins. the data written in pwr0, pwr1 , pwr2 and pwr3 correspond to the high-level width of one pwm output waveform cycle (256 states). when data is set in pwr0, pwr1, pwr2 and pwr3, the contents of the data are latched in the pwm waveform generators, updating the pwm waveform generation data. pwr0, pwr1, pwr2 and pwr3 are 8-bit write-only registers. when read, all bits are always read as 1. pwr0, pwr1, pwr2 and pwr3 are initialized to h'00 by a reset. note: the h8s/2197s and h8s/2196s do not have pwr2 and pwr3. section 18 8-bit pwm rev.2.00 jan. 15, 2007 page 360 of 1174 rej09b0329-0200 18.2.2 8-bit pwm control register (pw8cr) 0 0 1 0 r/w 2 0 r/w 3 0 4 5 6 7 ? ? ? ? ? ? ? ? pwc3 pwc2 pwc1 pwc0 r/w r/w 1111 bit : initial value : r/w : the 8-bit pwm control register (pw8cr) is an 8-bit readable/writable register that controls pwm functions. pw8cr is initialized to h'f0 by a reset. bits 7 to 4 ? reserved: these bits cannot be modified and are always read as 1. bits 3 to 0 ? output polarity select (pwc3 to pwc0): these bits select the output polarity of pwmn pin between positive or negative (reverse). bit n pwcn description 0 pwmn pin output has positive polarity (initial value) 1 pwmn pin output has negative polarity note: n = 3 to 0 (h8s/2197s and h8s/2196s: n = 1 and 0). 18.2.3 port mode register 3 (pmr3) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 6 0 7 pmr34 pmr33 pmr32 pmr31 pmr30 0 r/w pmr37 r/w r/w r/w pmr36 pmr35 bit : initial value : r/w : the port mode register 3 (pmr3) controls function switching of each pin in the port 3. switching is specified for each bit. the pmr3 is a 8-bit readable/writable register and is initialized to h'00 by a reset. for bits other than 5 to 2, see section 10.5, port 3. section 18 8-bit pwm rev.2.00 jan. 15, 2007 page 361 of 1174 rej09b0329-0200 bits 5 to 2 ? p35/pwm3 to p32/pwm0 pin switching (pmr35 to pmr32): these bits set whether the p3n/pwmm pin is used as i/o pin or it is used as 8-bit pwm output pwmm pin. bit n pmr3n description 0 p3n/pmwm pin functions as p3n i/o pin (initial value) 1 p3n/pmwm pin functions as pwmm output pin note: n = 5 to 2, m = 3 to 0. the h8s/2197s and h8s/2196s do not have pwm2 and pwm3 pin functions. 18.2.4 module stop control register (mstpcr) 7 1 mstp15 r/w mstpcrh 6 1 mstp14 r/w 5 1 mstp13 r/w 4 1 mstp12 r/w 3 1 mstp11 r/w 2 1 mstp10 r/w 1 1 mstp9 r/w 0 1 mstp8 r/w 7 1 mstp7 r/w 6 1 mstp6 r/w 5 1 mstp5 r/w 4 1 mstp4 r/w 3 1 mstp3 r/w 2 1 mstp2 r/w 1 1 mstp1 r/w 0 1 mstp0 r/w mstpcrl bit : initial value : r/w : the mstpcr consists of two 8-bit readable/writable registers that control module stop mode. when mstp4 bit is set to 1, the 8-bit pwm stops its operation upon completion of the bus cycle and transits to the module stop mode. for details, see section 4.5, module stop mode. the mstpcr is initialized to h'ffff by a reset. bit 4 ? module stop (mstp4): this bit sets the module stop mode of the 8-bit pwm. mstpcrl bit 4 mstp4 description 0 8-bit pwm module stop mode is released 1 8-bit pwm module stop mode is set (initial value) section 18 8-bit pwm rev.2.00 jan. 15, 2007 page 362 of 1174 rej09b0329-0200 18.3 8-bit pwm operation the 8-bit pwm outputs pwm pulses having a cycle length of 256 states and a pulse width determined by the data registers (pwr). the output pwm pulse can be converted to a dc voltage through integration in a low-pass filter. figure 18.2 shows the output waveform example of 8-bit pwm. the pulse width (twidth) can be obtained by the following expression: twidth = (1/ ) (pwr setting value) t width pulse width t width pulse cycle (256 states) t width pulse width t width pulse cycle (256 states) h'00 pwrn setting value h'ff frc lower 8-bit value pwrn pin output (positive polarity) (n = 3 to 0) (negative polarity) figure 18.2 8-bit pwm output waveform (example) section 19 12-bit pwm rev.2.00 jan. 15, 2007 page 363 of 1174 rej09b0329-0200 section 19 12-bit pwm 19.1 overview the 12-bit pwm incorporates 2 channels of the pulse pitch control method and functions as the drum and capstan motor controller. 19.1.1 features two on-chip 12-bit pwm signal generators are provided to control motors. these pwms use the pulse-pitch control method (periodically overriding part of the output). this reduces low- frequency components in the pulse output, enabling a quick response without increasing the clock frequency. the pitch of the pwm signal is modified in response to error data (representing lead or lag in relation to a preset speed and phase). section 19 12-bit pwm rev.2.00 jan. 15, 2007 page 364 of 1174 rej09b0329-0200 19.1.2 block diagram figure 19.1 shows a block diagram of the 12-bit pwm (1 channel). the pwm signal is generated by combining quantizing pulses from a 12-bit pulse generator with quantizing pulses derived from the contents of a data register. low-frequency components are reduced because the two quantizing pulses have different frequencies. the error da ta is represented by an unsigned 12-bit binary number. internal data bus legend: note: * refer to section 26, servo circuits. cappwm or drmpwm cappwm /2 /4 /8 /16 /32 /64 /128 drmpwm : capstan mix pin : drum mix pin pwm control register digital filter circuit error data pton pwm data register output control circuit pulse generator counter dfucr * cp/ dp figure 19.1 block diagram of 12-bit pwm (1 channel) section 19 12-bit pwm rev.2.00 jan. 15, 2007 page 365 of 1174 rej09b0329-0200 19.1.3 pin configuration table 19.1 shows the 12-bit pwm pin configuration. table 19.1 pin configuration name abbrev. i/o function capstan mix cappwm output 12-bit pwm square-wave output drum mix drmpwm 19.1.4 register configuration table 19.2 shows the 12-bit pwm register configuration. table 19.2 12-bit pwm registers name abbrev. r/w size initial value address * cpwcr w byte h'42 h'd07b 12-bit pwm control register dpwcr w byte h'42 h'd07a 12-bit pwm data register cpwdr r/w word h'f000 h'd07c dpwdr r/w word h'f000 h'd078 note: * lower 16 bits of the address. section 19 12-bit pwm rev.2.00 jan. 15, 2007 page 366 of 1174 rej09b0329-0200 19.2 register descriptions 19.2.1 12-bit pwm control registers (cpwcr, dpwcr) cpwcr 0 0 1 1 w 2 0 w 3 0 4 0 w 0 w 5 6 1 7 ch/l csf/df cck2 cck1 cck0 0 w cpol w w w cdc chiz bit : initial value : r/w : dpwcr 0 0 1 1 w 2 0 w 3 0 4 0 w 0 w 5 6 1 7 dh/l dsf/df dck2 dck1 dck0 0 w dpol w w w ddc dhiz bit : initial value : r/w : cpwcr is the pwm output control register for the capstan motor. dpwcr is the pwm output control register for the drum motor. both are 8-bit writable registers. cpwcr and dpwcr are initialized to h'42 by a rese t, or when in a power-down state except for active medium-speed mode. bit 7 ? polarity invert (pol): this bit can invert the polarity of the modulated pwm signal for noise suppression and other purposes. this bit is invalid when fixed output is selected (when bit dc is set to 1). bit 7 pol description 0 output with positive polarity (initial value) 1 output with inverted polarity bit 6 ? output select (dc): selects either pwm modulated output, or fixed output controlled by the pin output bits (bits 5 and 4). section 19 12-bit pwm rev.2.00 jan. 15, 2007 page 367 of 1174 rej09b0329-0200 bits 5 and 4 ? pwm pin output (hi-z, h/l): when bit dc is set to 1, the 12-bit pwm output pins (cappwm, drmpwm) output a value determined by the hi-z and h/l bits. the output is not affected by bit pol. in power-down modes, the 12-bit pwm circuit and pin statuses are retained. before making a transition to a power-down mode, first set bits 6 (dc), 5 (hi-z), and 4 (h/l) of the 12-bit pwm control registers (cpwcr and dpwcr) to select a fixed output level. choose one of the following settings: bit 6 bit 5 bit 4 dc hi-z h/l output state 0 low output (initial value) 0 1 high output 1 1 * high-impedance 0 * * modulation signal output legend: * don't care bit 3 ? output data select (sf/df): selects whether the data to be converted to pwm output is taken from the data register or from the digital filter circuit. bit 3 sf/df description 0 modulation by error data from the digital filter circuit (initial value) 1 modulation by error data written in the data register note: when pwms output data from the digital filter circuit, the data consisting of the speed and phase filtering results are modulated by pwms and output from the cappwm and drmpwm pins. however, it is possible to output only drum phase filter results from cappwm pin and only capstan phase filter result from drmpwm pin, by dfucr settings of the digital filter circuit. see section 26.11, digital filters. section 19 12-bit pwm rev.2.00 jan. 15, 2007 page 368 of 1174 rej09b0329-0200 bits 2 to 0 ? carrier frequency select (ck2 to ck0): selects the carrier frequency of the pwm modulated signal. do not set them to 111. bit 2 bit 1 bit 0 ck2 ck1 ck0 description 0 2 0 1 4 0 8 (initial value) 0 1 1 16 0 32 0 1 64 0 128 1 1 1 (do not set) 19.2.2 12-bit pwm data registers (dpwdr, cpwdr) cpwdr 1 0 r/w cpwdr1 0 0 r/w cpwdr0 3 0 r/w cpwdr3 2 0 r/w cpwdr2 5 0 r/w cpwdr5 4 0 r/w cpwdr4 7 0 r/w cpwdr7 6 0 r/w cpwdr6 9 0 r/w cpwdr9 8 0 r/w cpwdr8 11 0 r/w cpwdr11 10 0 r/w cpwdr10 12 1 13 1 14 1 15 ? ? ? ? ? ? ? ? 1 bit : initial value : r/w : dpwdr 1 0 r/w dpwdr1 0 0 r/w dpwdr0 3 0 r/w dpwdr3 2 0 r/w dpwdr2 5 0 r/w dpwdr5 4 0 r/w dpwdr4 7 0 r/w dpwdr7 6 0 r/w dpwdr6 9 0 r/w dpwdr9 8 0 r/w dpwdr8 11 0 r/w dpwdr11 10 0 r/w dpwdr10 12 1 13 1 14 1 15 1 ? ? ? ? ? ? ? ? bit : initial value : r/w : the 12-bit pwm data registers (dpwdr and cpwdr) are 12-bit readable/writable registers in which the data to be converted to pwm output is written. the data in these registers is converted to pwm output only when bit sf/df of the corresponding control register is set to 1. when the sf/df bit is 0, the error data from the digital filter circuit is written in the data register, and then modulated by pwm. at this time, the error data from the digital filter circuit can be monitored by reading the data register. these registers can be accessed by word only, and cannot be accessed by byte. byte access gives unassured results. section 19 12-bit pwm rev.2.00 jan. 15, 2007 page 369 of 1174 rej09b0329-0200 both registers are initialized to h'f000 by a re set or in a power-down state except for active medium speed mode. 19.2.3 module stop control register (mstpcr) 7 1 mstp15 r/w mstpcrh 6 1 mstp14 r/w 5 1 mstp13 r/w 4 1 mstp12 r/w 3 1 mstp11 r/w 2 1 mstp10 r/w 1 1 mstp9 r/w 0 1 mstp8 r/w 7 1 mstp7 r/w 6 1 mstp6 r/w 5 1 mstp5 r/w 4 1 mstp4 r/w 3 1 mstp3 r/w 2 1 mstp2 r/w 1 1 mstp1 r/w 0 1 mstp0 r/w mstpcrl bit : initial value : r/w : the mstpcr consists of two 8-bit readable/writable registers that control module stop mode. when mstp1 bit is set to 1, the 12-bit pwm stops its operation upon completion of the bus cycle and transits to the module stop mode. for details, see section 4.5, module stop mode. the mstpcr is initialized to h'ffff by a reset. bit 1 ? module stop (mstp1): this bit sets the module stop mode of the 12-bit pwm. mstpcrl bit 1 mstp1 description 0 12-bit pwm and servo circuit module stop mode is released 1 12-bit pwm and servo circuit module stop mode is set (initial value) section 19 12-bit pwm rev.2.00 jan. 15, 2007 page 370 of 1174 rej09b0329-0200 19.3 operation 19.3.1 output waveform the pwm signal generator combines the error data with the output from an internal pulse generator to produce a pulse-width modulated signal. when vcc/2 is set as the reference va lue, the following conditions apply: 1. when the motor is running at the correct speed and phase, the pwm signal is output with a 50% duty cycle. 2. when the motor is running behind the correct speed or phase, it is corrected by periodically holding part of the pwm signal low. the part held low depends on the size of the error. 3. when the motor is running ahead of the correct speed or phase, it is corrected by periodically holding part of the pwm signal high. the part held high depends on the size of the error. when the motor is running at the correct speed and phase, the error data is a 12-bit value representing 1/2 (1000 0000 0000), and the pwm output has the same frequency as the selected division clock. after the error data has been converted into a pwm signal, the pwm signal can be smoothed into a dc voltage by an external low-pass filter (lpf). the smoothe error data can be used to control the motor. figure 19.2 shows sample waveform outputs. the 12-bit pwm pin outputs a low-level signal upon reset, in power-down mode or at module- stop. section 19 12-bit pwm rev.2.00 jan. 15, 2007 page 371 of 1174 rej09b0329-0200 1 counter pulse generator pwm data register c10 c11 c12 c13 corresponds to pwr3 = 1 corresponds to pwr2 = 1 corresponds to pwr1 = 1 corresponds to pwr0 = 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 pwr3 2 1 0 "l" 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 figure 19.2 sample waveform output by 12-bit pwm (4 bits) section 19 12-bit pwm rev.2.00 jan. 15, 2007 page 372 of 1174 rej09b0329-0200 section 20 14-bit pwm rev.2.00 jan. 15, 2007 page 373 of 1174 rej09b0329-0200 section 20 14-bit pwm note: the 14-bit pwm is not (incorporated in) provided for the h8s/2197s and h8s/2196s. 20.1 overview the 14-bit pwm is a pulse division type pwm that can be used for electronic tuner control, etc. 20.1.1 features features of the 14-bit pwm are given below: ? choice of two conversion periods a conversion period of 32768/ with a minimum modulation width of 2/ , or a conversion period of 16384/ with a minimum modulation width of 1/ , can be selected. ? pulse division method for less ripple section 20 14-bit pwm rev.2.00 jan. 15, 2007 page 374 of 1174 rej09b0329-0200 20.1.2 block diagram figure 20.1 shows a block diagram of the 14-bit pwm. legend: pwcr /4 /2 pwdrl : pwm control register : pwm data register l pwdru pwm14 : pwm data register u : pwm14 output pin internal data bus pwcr pwdrl pwdru pwm waveform generator pwm14 figure 20.1 block diagram of 14-bit pwm 20.1.3 pin configuration table 20.1 shows the 14-bit pwm pin configuration. table 20.1 pin configuration name abbrev. i/o function pwm 14-bit square-wave output pin pwm14 * output 14-bit pwm square-wave output note: * this pin also functions as p40 general i/o pin. when using this pin, set the pin function by the port mode register 4 (pmr4). for details, see section 10.6, port 4. section 20 14-bit pwm rev.2.00 jan. 15, 2007 page 375 of 1174 rej09b0329-0200 20.1.4 register configuration table 20.2 shows the 14-bit pwm register configuration. table 20.2 14-bit pwm registers name abbrev. r/w size initial value address * pwm control register pwcr r/w byte h'fe h'd122 pwm data register u pwdru w byte h'c0 h'd121 pwm data register l pwdrl w byte h'00 h'd120 note: * lower 16 bits of the address. 20.2 register descriptions 20.2.1 pwm control register (pwcr) 0 0 1 1 2 1 3 1 4 1 5 1 6 1 7 ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w pwcr0 1 bit : initial value : r/w : the pwm control register (pwcr) is an 8-bit read/write register that controls the 14-bit pwm functions. pwcr is initialized to h'fe by a reset. bits 7 to 1 ? reserved: these bits cannot be modified and are always read as 1. bit 0 ? clock select (pwcr0): selects the clock supplied to the 14-bit pwm. bit 0 pwcr0 description 0 the input clock is /2 (t = 2/ ) (initial value) the conversion period is 16384/ , with a minimum modulation width of 1/ 1 the input clock is /4 (t = 4/ ) the conversion period is 32768/ , with a minimum modulation width of 2/ note: t/ : period of pwm clock input section 20 14-bit pwm rev.2.00 jan. 15, 2007 page 376 of 1174 rej09b0329-0200 20.2.2 pwm data registers u and l (pwdru, pwdrl) pwdru 0 0 1 0 2 0 3 0 4 0 5 0 6 1 7 ? ? ? ? w pwdru0 w pwdru1 w pwdru2 w pwdru3 w pwdru4 w pwdru5 1 bit : initial value : r/w : pwdrl 0 0 1 0 2 0 3 0 4 0 5 0 6 7 w pwdrl0 w pwdrl1 w pwdrl2 w pwdrl3 w pwdrl4 w pwdrl5 0 w pwdrl6 w pwdrl7 0 bit : initial value : r/w : pwm data registers u and l (pwdru and pwdrl) indicate high level width in one pwm waveform cycle. pwdru and pwdrl form a 14-bit write-only register, with the upper 6 bits assigned to pwdru and the lower 8 bits to pwdrl. the value wr itten in pwdru and pwdrl gives the total high- level width of one pwm waveform cycle. both pwdru and pwdrl are accessible by byte access only. word access gives unassured results. when 14-bit data is written in pwdru and pw drl, the contents are latched in the pwm waveform generator and the pwm waveform gene ration data is updated. when writing the 14-bit data, follow these steps: 1. write the lower 8 bits to pwdrl. 2. write the upper 6 bits to pwdru. write the data first to pwdrl and then to pwdru. pwdru and pwdrl are write-only registers. when read, all bits always read 1. pwdru and pwdrl are initialized to h'c000 by a reset. section 20 14-bit pwm rev.2.00 jan. 15, 2007 page 377 of 1174 rej09b0329-0200 20.2.3 module stop control register (mstpcr) 7 1 mstp15 r/w mstpcrh 6 1 mstp14 r/w 5 1 mstp13 r/w 4 1 mstp12 r/w 3 1 mstp11 r/w 2 1 mstp10 r/w 1 1 mstp9 r/w 0 1 mstp8 r/w 7 1 mstp7 r/w 6 1 mstp6 r/w 5 1 mstp5 r/w 4 1 mstp4 r/w 3 1 mstp3 r/w 2 1 mstp2 r/w 1 1 mstp1 r/w 0 1 mstp0 r/w mstpcrl bit : initial value : r/w : the module stop control register (mstpcr) consists of two 8-bit readable/writable registers that control the module stop mode functions. when the mstp5 bit is set to 1, the 14-bit pwm operation stops at the end of the bus cycle and a transition is made to module stop mode. for details, see section 4.5, module stop mode. mstpcr is initialized to h'ffff by a reset. bit 5 ? module stop (mstp5): specifies the module stop mode of the 14-bit pwm. mstpcrl bit 5 mstp5 description 0 14-bit pwm module stop mode is released 1 14-bit pwm module stop mode is set (initial value) section 20 14-bit pwm rev.2.00 jan. 15, 2007 page 378 of 1174 rej09b0329-0200 20.3 14-bit pwm operation when using the 14-bit pwm, set the registers in this sequence: 1. set bit pwm40 to 1 in port mode register 4 (pmr4) so that pin p40/pwm14 is designated for pwm output. 2. set bit pwcr0 in the pwm control register (pwcr) to select a conversion period of either 32768/ (pwcr0 = 1) or 16384/ (pwcr0 = 0). 3. set the output waveform data in pwm data registers u and l (pwdru, pwdrl). be sure to write byte data first to pwdrl and then to pw dru. when the data is written in pwdru, the contents of these registers are latched in the pwm waveform generator, and the pwm waveform generation data is updated in synchronization with internal signals. one conversion period consists of 64 pulses, as shown in figure 20.2. the total high-level width during this period (t h ) corresponds to the data in pwdru and pwdrl. this relation can be expressed as follows: t h = (data value in pwdru and pwdrl + 64) t /2 where to is the period of pwm clock input: 2/ (bit pwcr0 = 0) or 4/ (bit pwcr0 = 1). if the data value in pwdru and pwdrl is from h'3fc0 to h'3fff, the pwm output stays high. when the data value is h'c000, t h is calculated as follows: t h = 64 t /2 = 32 ? t t h64 t h63 t h3 t h2 t h1 t h = t h1 + t h2 + t h3 + ... + t h64 t f1 = t f2 = t f3 = ... = t f64 t f1 t f2 t f63 t f64 1 conversion period figure 20.2 waveform output by 14-bit pwm section 21 prescalar unit rev.2.00 jan. 15, 2007 page 379 of 1174 rej09b0329-0200 section 21 prescalar unit 21.1 overview the prescalar unit (psu) has a 18-bit free running counter (frc) that uses as a clock source and a 5-bit counter that uses w as a clock source. 21.1.1 features ? prescalar s (pss) generates frequency division clocks that are input to peripheral functions. ? prescalar w (psw) when a timer a is used as a clock time ba se, the psw frequency-divides subclocks and generates input clocks. ? stable oscillation wait time count during the return from the low power consumption mode excluding the sleep mode, the frc counts the stable oscillation wait time. ? 8-bit pwm the lower 8 bits of the frc is used as 8-bit pwm cycle and duty cycle generation counters. (conversion cycle: 256 states) ? 8-bit input capture by ic pins catches the 8 bits of 2 15 to 2 8 of the frc according to the edge of the ic pin for remote control receiving. ? frequency division clock output can output the frequency division clock for the system clock or the frequency division clock for the subclock from the frequency division clock output pin (tmow). section 21 prescalar unit rev.2.00 jan. 15, 2007 page 380 of 1174 rej09b0329-0200 21.1.2 block diagram figure 21.1 shows a block diagram of the prescalar unit. pwm3 icr1 pcsr 18-bit free running counter (frc) w/128 prescalar w /131072 to /2 prescalar s internal data bus msb lsb w/4 w/8 w/16 w/32 /32 /16 /8 /4 interrupt request 5-bit counter ic pin stable oscillation wait time count output 2 12 2 15 2 8 2 17 2 7 2 0 tmow pin msb lsb 8 bits 6 bits 8 bits pwm2 pwm1 pwm0 legend: icr1 pcsr : input capture register 1 : prescalar unit control/status register ic tmow : input capture input pin : frequency division clock output pin figure 21.1 block diagram of prescalar unit section 21 prescalar unit rev.2.00 jan. 15, 2007 page 381 of 1174 rej09b0329-0200 21.1.3 pin configuration table 21.1 shows the pin configuration of the prescalar unit. table 21.1 pin configuration name abbrev. i/o function input capture input ic input prescalar unit input capture input pin frequency division clock output tmow output prescalar unit frequency division clock output pin 21.1.4 register configuration table 21.2 shows the register configuration of the prescalar unit. table 21.2 register configuration name abbrev. r/w size initial value address * input capture register 1 icr1 r byte h'00 h'd12c prescalar unit control/status register pcsr r/w byte h'08 h'd12d note: * lower 16 bits of the address. section 21 prescalar unit rev.2.00 jan. 15, 2007 page 382 of 1174 rej09b0329-0200 21.2 registers 21.2.1 input capture register 1 (icr1) 0 0 1 0 r 2 0 r 3 0 4 0 r 0 r 5 6 0 7 icr14 icr13 icr12 icr11 icr10 0 r icr17 r r r icr16 icr15 bit : initial value : r/w : input capture register 1 (icr1) captures 8-bit data of 2 15 to 2 8 of the frc according to the edge of the ic pin. icr1 is an 8-bit read-only register. the write operation becomes invalid. the icr1 values are undefined until the first capture is generated afte r the mode has been set to the standby mode, watch mode, subactive mode, and subsleeve mode. when reset, icr1 is initialized to h'00. 21.2.2 prescalar unit cont rol/status register (pcsr) 0 0 1 0 r/w 2 0 r/w 3 ? ? 1 4 0 r/w 5 0 6 0 7 r/w r/w iceg r/w icie 0 r/(w) * icif ncon/off dcs2 dcs1 dcs0 note: * only 0 can be written to clear the flag. bit : initial value : r/w : the prescalar unit control/status register (pcsr) controls the input capture function and selects the frequency division clock that is output from the tmow pin. pcsr is an 8-bit read/write enable register . when reset, pcsr is initialized to h'08. bit 7 ? input capture interrupt flag (icif): input capture interrupt request flag. this indicates that the input capture was performed according to the edge of the ic pin. bit 7 icif description 0 [clear condition] (initial value) when 0 is written after 1 has been read 1 [set condition] when the input capture was performed according to the edge of the ic pin section 21 prescalar unit rev.2.00 jan. 15, 2007 page 383 of 1174 rej09b0329-0200 bit 6 ? input capture interrupt enable (icie): when icif was set to 1 by the input capture according to the edge of the ic pin, icie enables and disables the generation of an input capture interrupt. bit 6 icie description 0 disables the generation of an input capture interrupt (initial value) 1 enables the generation of an input capture interrupt bit 5 ? ic pin edge select (iceg): iceg selects the input edge sense of the ic pin. bit 5 iceg description 0 detects the falling edge of the ic pin input (initial value) 1 detects the rising edge of the ic pin input bit 4 ? noise cancel on/off (ncon/off): ncon/off selects enable/dis able of the noise cancel function of the ic pin. for the noise cancel function, see section 21.3, noise cancel circuit. bit 4 ncon/off description 0 disables the noise cancel function of the ic pin (initial value) 1 enables the noise cancel function of the ic pin bit 3 ? reserved: this bit cannot be modified and is always read as 1. section 21 prescalar unit rev.2.00 jan. 15, 2007 page 384 of 1174 rej09b0329-0200 bits 2 to 0 ? frequency division clock output select (dcs2 to dcs0): dcs2 to dcs0 select eight types of frequency division clocks that are output from the tmow pin. bit 2 bit 1 bit 0 dcs2 dcs1 dcs0 description 0 outputs pss, /32 (initial value) 0 1 outputs pss, /16 0 outputs pss, /8 0 1 1 outputs pss, /4 1 0 outputs psw, w/32 0 1 outputs psw, w/16 1 0 outputs psw, w/8 1 outputs psw, w/4 21.2.3 port mode register 1 (pmr1) 7 pmr17 0 r/w 6 pmr16 0 r/w 5 pmr15 0 r/w 4 pmr14 0 r/w 3 pmr13 0 r/w 0 pmr10 0 r/w 2 pmr12 0 r/w 1 pmr11 0 r/w bit : initial value : r/w : the port mode register 1 (pmr1) controls switchi ng of each pin function of port 1. the switching is specified in a unit of bit. pmr1 is an 8-bit read/write enable register. when reset, pmr1 is initialized to h'00. for details, refer to port mode register 1 in section 10.3.2 register configuration. bit 7 ? p17/tmow pin switching (pmr17): pmr17 sets whether the p17/tmow pin is used as a p17 i/o pin or a tmow pin for division clock output. bit 7 pmr17 description 0 the p17/tmow pin functions as a p17 i/o pin (initial value) 1 the p17/tmow pin functions as a tmow output function section 21 prescalar unit rev.2.00 jan. 15, 2007 page 385 of 1174 rej09b0329-0200 bit 6 ? p16/ ic pin switching (pmr16): pmr16 sets whether the p16/ ic pin is used as a p16 i/o pin or an ic pin for the input capture input of the prescalar unit. bit 6 pmr16 description 0 the p16/ ic pin functions as a p16 i/o pin (initial value) 1 the p16/ ic pin functions as an ic input function 21.3 noise cancel circuit the ic pin has a built-in a noise cancel circuit. the circuit can be used for noise protection such as remote control receiving. the noise cancel circuit samples the input values of the ic pin twice at an interval of 256 states. if the input values are different, they are assumed to be noise. the ic pin can specify enable/disable of the noise cancel function according to the bit 4 (ncon/off) of the prescalar unit control/status register (pcsr). 21.4 operation 21.4.1 prescalar s (pss) the pss is a 17-bit counter that uses the system clock ( =fosc) as an input clock and generates the frequency division clocks ( /131072 to /2) of the peripheral function. the low-order 17 bits of the 18-bit free running counter (frc) correspond to the pss. the frc is incremented by one clock. the pss output is shared by the timer and serial communication interface (sci), and the frequency division ratio can independently be set by each built-in peripheral function. when reset, the frc is initialized to h'00000, and starts increment after reset has been released. because the system clock oscillator is stopped in standby mode, watch mode, subactive mode, and subsleep mode, the pss operation is also stopped. in this case, the fcr is also initialized to h'00000. the frc cannot be read and written from the cpu. section 21 prescalar unit rev.2.00 jan. 15, 2007 page 386 of 1174 rej09b0329-0200 21.4.2 prescalar w (psw) psw is a counter that uses the subclock as an input clock. the psw also generates the input clock of the timer a. in this case, the tim er a functions as a clock time base. when reset, the psw is initialized to h'00, and starts increment after reset has been released. even if the mode has been shifted to the standby mode*, watch mode*, subactive mode*, and subsleep mode*, the psw continues the operation as long as the clocks are supplied by the x1 and x2 pins. the psw can also be initialized to h'00 by setting the tma3 and tma2 bits of the timer mode register a (tma) to 11. note: * when the timer a is in module stop mode, the operation is stopped. figure 21.2 shows the supply of the clocks to the peripheral function by the pss and psw. /131072 to /2 timer sci osc1 fosc osc2 w/128 w/4 w timer a prescalar s x1 (fx) x2 cpu rom ram tmow pin peripheral register i/o port intermediate speed clock frequency divider prescalar w system clock selection subclock frequency dividers (1/2, 1/4, and 1/8) subclock oscillator system clock oscillator system clock duty correction circuit figure 21.2 clock supply 21.4.3 stable oscillation wait time count for the count of the stable oscillation stable wait time during the return from the low power consumption mode excluding the sleep mode, see section 4, power-down state. section 21 prescalar unit rev.2.00 jan. 15, 2007 page 387 of 1174 rej09b0329-0200 21.4.4 8-bit pwm this 8-bit pwm controls the duty control pwm signal in the conversion cycle 256 states. it counts the cycle and the duty cycle at 2 7 to 2 0 of the frc. it can be used for controlling reel motors and loading motors. for details, see section 18, 8-bit pwm. 21.4.5 8-bit input capture using ic pin this function catches the 8-bit data of 2 15 to 2 8 of the frc according to the edge of the ic pin. it can be used for remote control receiving. for the edge of the ic pin, the rising and falling edges can be selected. the ic pin has a built-in noise cancel circuit. see section 21.3, noise cancel circuit. an interrupt request is generated due to the input capture using the ic pin. note: rewriting the iceg bit, ncon/off bit, or pmr16 bit is incorrectly recognized as edge detection according to the combinations betw een the state and detection edge of the ic pin and the icif bit may be set after up to 384 seconds. 21.4.6 frequency division clock output the frequency division clock can be output from the tmow pin. for the frequency division clock, eight types of clocks ca n be selected according to the dcs2 to dcs0 bits in pcsr. the clock in which the system clock was frequen cy-divided is output in active mode and sleep mode and the clock in which the subclock was frequency-divided is output in active mode*, sleep mode*, and subactive mode. note: * when timer a is in module stop mode, no clock is output. section 21 prescalar unit rev.2.00 jan. 15, 2007 page 388 of 1174 rej09b0329-0200 section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 389 of 1174 rej09b0329-0200 section 22 serial communication interface 1 (sci1) 22.1 overview the serial communication interf ace (sci) can handle both asynchr onous and clocked synchronous serial communication. a function is also provided for serial communication between processors (multiprocessor communication function). 22.1.1 features sci1 features are listed below. ? choice of asynchronous or synchronous serial communication mode ? asynchronous mode ? serial data communication is executed using an asynchronous system in which synchronization is achieved character by character serial data communication can be carried out with standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or asynchronous communication interface adapter (acia) ? a multiprocessor communication function is provided that enables serial data communication with a number of processors ? choice of 12 serial data transfer formats data length: 7 or 8 bits stop bit length: 1 or 2 bits parity: even, odd, or none multiprocessor bit: 1 or 0 ? receive error detection: parity , overrun, and framing errors ? break detection: break can be detected by reading the si1 pin level directly in case of a framing error ? clock synchronous mode ? serial data communication is synchronized with a clock serial data communication can be carried out with other chips that have a synchronous communication function ? one serial data transfer format data length: 8 bits ? receive error detection: overrun errors detected section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 390 of 1174 rej09b0329-0200 ? full-duplex communication capability ? the transmitter and receiver are mutually inde pendent, enabling transmission and reception to be executed simultaneously ? double-buffering is used in both the tran smitter and the receiver, enabling continuous transmission and continuous reception of serial data ? built-in baud rate generator allows any bit rate to be selected ? choice of serial clock source: internal clock from baud rate generator or external clock from sck1 pin ? four interrupt sources ? four interrupt sources (transmit-data-empty, transmit-end, receive-data-full, and receive error) that can issue requests independently section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 391 of 1174 rej09b0329-0200 22.1.2 block diagram figure 22.1 shows a block diagram of the sci. si1 so1 sck1 clock external clock /4 /16 /64 tei txi rxi eri rsr1 rdr1 tsr1 tdr1 smr1 scr1 ssr1 scmr1 brr1 : receive shift register 1 : receive data register 1 : transmit shift register 1 : transmit data register 1 : serial mode register 1 : serial control register 1 : serial status register 1 : serial interface mode register 1 : bit rate register 1 scmr1 ssr1 scr1 smr1 transmission/ reception control baud rate generator brr1 module data bus bus interface internal data bus rdr1 tsr1 rsr1 parity generation parity check legend: tdr1 figure 22.1 block diagram of sci section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 392 of 1174 rej09b0329-0200 22.1.3 pin configuration table 22.1 shows the serial pins used by the sci. table 22.1 sci pins channel pin name symbol i/o function 1 serial clock pin 1 sck1 i/o sci1 clock input/output receive data pin 1 si1 input sci1 receive data input transmit data pin 1 so1 output sci1 transmit data output 22.1.4 register configuration the sci1 has the internal registers shown in ta ble 22.2. these registers are used to specify asynchronous mode or synchronous mode, the data format, and the bit rate, and to control the transmitter/receiver. table 22.2 sci registers channel name abbrev. r/w initial value address * 1 serial mode register 1 smr1 r/w h'00 h'd148 bit rate register 1 brr1 r/w h'ff h'd149 serial control register 1 scr1 r/w h'00 h'd14a transmit data register 1 tdr1 r/w h'ff h'd14b serial status register 1 ssr1 r/(w) * 2 h'84 h'd14c receive data register 1 rdr1 r h'00 h'd14d 1 serial interface mode register 1 scmr1 r/w h'f2 h'd14e common module stop control register mstpcrh r/w h'ff h'ffec mstpcrl r/w h'ff h'ffed notes: 1. lower 16 bits of the address. 2. only 0 can be written, to clear flags. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 393 of 1174 rej09b0329-0200 22.2 register descriptions 22.2.1 receive shift register 1 (rsr1) 7 ? 6 ? 5 ? 4 ? 3 ? 0 ? 2 ? 1 ? bit : r/w : rsr1 is a register used to receive serial data. the sci sets serial data input fr om the si1 pin in rsr1 in the order received, starting with the lsb (bit 0), and converts it to parallel data. when one byte of data has been received, it is transferred to rdr automatically. rsr1 cannot be directly read or written to by the cpu. 22.2.2 receive data register 1 (rdr1) 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit : initial value : r/w : rdr1 is a register that stores received serial data. when the sci has received one byte of serial data, it transfers the received serial data from rsr1 to rdr1 where it is stored, a nd completes the receive operation. after this, rsr1 is receive- enabled. since rsr1 and rdr1 function as a double buffer in this way, continuous receive operations can be performed. rdr1 is a read-only register, and cannot be written to by the cpu. rdr1 is initialized to h'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 394 of 1174 rej09b0329-0200 22.2.3 transmit shift register 1 (tsr1) 7 ? 6 ? 5 ? 4 ? 3 ? 0 ? 2 ? 1 ? bit : r/w : tsr1 is a register used to transmit serial data. to perform serial data transmission, the sci first transfers transmit data from tdr1 to tsr1, then sends the data to the so1 pin starting with the lsb (bit 0). when transmission of one byte is completed, the next transmit data is transferred from tdr1 to tsr1, and transmission started, automatically. however, data transfer from tdr1 to tsr1 is not performed if the tdre bit in ssr1 is set to 1. tsr1 cannot be directly read or written to by the cpu. 22.2.4 transmit data register 1 (tdr1) 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit : initial value : r/w : tdr1 is an 8-bit register that st ores data for serial transmission. when the sci detects that tsr1 is empty, it transfers the transmit data written in tdr1 to tsr1 and starts serial transmission. c ontinuous serial transmission can be carried out by writing the next transmit data to tdr1 during serial transmission of the data in tsr1. tdr1 can be read or written to by the cpu at all times. tdr1 is initialized to h'ff by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 395 of 1174 rej09b0329-0200 22.2.5 serial mode register 1 (smr1) 7 c/a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w bit : initial value : r/w : smr1 is an 8-bit register used to set the sci's serial transfer format and select the baud rate generator clock source. smr1 can be read or written to by the cpu at all times. smr1 is initialized to h'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. bit 7 ? communication mode (c/ a ): selects asynchronous mode or clock synchronous mode as the sci operating mode. bit 7 c/ a description 0 asynchronous mode (initial value) 1 clock synchronous mode bit 6 ? character length (chr): selects 7 or 8 bits as the data length in asynchronous mode. in synchronous mode, a fixed data length of 8 bits is used regardless of the chr setting. bit 6 chr description 0 8-bit data (initial value) 1 7-bit data * note: * when 7-bit data is selected, the msb (bit 7) of tdr1 is not transmitted, and lsb- first/msb-first selection is not available. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 396 of 1174 rej09b0329-0200 bit 5 ? parity enable (pe): in asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. in synchronous mode, or when a multiprocessor format is used, parity bit addition and checking is not performed, regardless of the pe bit setting. bit 5 pe description 0 parity bit addition and checking disabled (initial value) 1 parity bit addition and checking enabled * note: * when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in reception, the parity bit is checked for the parity (even or odd) specified by the o/ e bit. bit 4 ? parity mode (o/ e ): selects either even or odd parity for use in parity addition and checking. the o/ e bit setting is only valid when the pe bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. the o/ e bit setting is invalid in synchronous mode, when parity bit addition and checking is disabled in asynchronous mode, and when a multiprocessor format is used. bit 4 o/ e description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. when even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. when odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1 bi ts in the receive character plus the parity bit is odd. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 397 of 1174 rej09b0329-0200 bit 3 ? stop bit length (stop): selects 1 or 2 bits as the stop bit length in asynchronous mode. the stop bit setting is only valid in asynchronous mode. if synchronous mode is set the stop bit setting is invalid since stop bits are not added. bit 3 stop description 0 1 stop bit * 1 (initial value) 1 2 stop bits * 2 notes: 1. in transmission, a single 1 bit (stop bi t) is added to the end of a transmit character before it is sent. 2. in transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. in reception, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. bit 2 ? multiprocessor mode (mp): selects multiprocessor format. when multiprocessor format is selected, the pe bit and o/ e bit parity settings are invalid. the mp bit setting is only valid in asynchronous mode; it is invalid in synchronous mode. for details of the multiprocessor communication function, see section 22.3.3, multiprocessor communication function. bit 2 mp description 0 multiprocessor function disabled (initial value) 1 multiprocessor format selected section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 398 of 1174 rej09b0329-0200 bits 1 and 0 ? clock select 1 and 0 (cks1, cks0): these bits select the clock source for the baud rate generator. the clock source can be selected from , /4, /16, and /64, according to the setting of bits cks1 and cks0. for the relation between the clock source, the bit rate register setting, and the baud rate, see section 22.2.8, bit rate register 1 (brr1). bit 1 bit 0 cks1 cks0 description 0 clock (initial value) 0 1 /4 clock 1 0 /16 clock 1 /64 clock 22.2.6 serial control register 1 (scr1) 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit : initial value : r/w : scr1 is a register that performs enabling or disabling of sci transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. scr1 can be read or written to by the cpu at all times. scr1 is initialized to h'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. bit 7 ? transmit interrupt enable (tie): enables or disables transmit-data-empty interrupt (txi) request generation when serial transmit data is transferred from tdr1 to tsr1 and the tdre flag in ssr1 is set to 1. bit 7 tie description 0 transmit-data-empty interrupt (txi) request disabled * (initial value) 1 transmit-data-empty interrupt (txi) request enabled note: * txi interrupt request cancellation can be performed by reading 1 from the tdre flag, then clearing it to 0, or clearing the tie bit to 0. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 399 of 1174 rej09b0329-0200 bit 6 ? receive interrupt enable (rie): enables or disables receive -data-full interrupt (rxi) request and receive-error interrupt (eri) request generation when seri al receive data is transferred from rsr1 to rdr1 and the rdrf flag in ssr1 is set to 1. bit 6 rie description 0 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request disabled * (initial value) 1 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request enabled note: * rxi and eri interrupt request cancellation can be performed by reading 1 from the rdrf, fer, per, or orer flag, then clearing the flag to 0, or clearing the rie bit to 0. bit 5 ? transmit enable (te): enables or disables the start of serial transmission by the sci. bit 5 te description 0 transmission disabled * 1 (initial value) 1 transmission enabled * 2 notes: 1. the tdre flag in ssr1 is fixed at 1. 2. in this state, serial transmission is started when transmit data is written to tdr1 and the tdre flag in ssr1 is cleared to 0. smr1 setting must be performed to decide the transmission format before setting the te bit to 1. bit 4 ? receive enable (re): enables or disables the start of serial reception by the sci. bit 4 re description 0 reception disabled * 1 (initial value) 1 reception enabled * 2 notes: 1. clearing the re bit to 0 does not affect the rdrf, fer, per, and orer flags, which retain their states. 2. serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. smr1 setting must be performed to decide the reception format before setting the re bit to 1. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 400 of 1174 rej09b0329-0200 bit 3 ? multiprocessor interrupt enable (mpie): enables or disables multiprocessor interrupts. the mpie bit setting is only valid in asynchronous mode when receiving with the mp bit in smr1 set to 1. the mpie bit setting is invalid in clock synchronous mode or when the mp bit is cleared to 0. bit 3 mpie description 0 multiprocessor interrupts disabled (normal reception performed) (initial value) [clearing conditions] 1. when the mpie bit is cleared to 0 2. when data with mpb = 1 is received 1 multiprocessor interrupts enabled * receive interrupt (rxi) requests, receive-error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr1 are disabled until data with the multiprocessor bit set to 1 is received. note: * when receive data including mpb = 0 is received, receive data transfer from rsr1 to rdr1, receive error detection, and setting of the rdrf, fer, and orer flags in ssr1, is not performed. when receive data with mpb = 1 is received, the mpb bit in ssr1 is set to 1, the mpie bit is cleared to 0 automatically, and generation of rxi and eri interrupts (when the tie and rie bits in scr are set to 1) and fer and orer flag setting is enabled. bit 2 ? transmit end interrupt enable (teie): enables or disables transmit-end interrupt (tei) request generation if there is no valid transmit data in tdr when the msb is transmitted. bit 2 teie description 0 transmit-end interrupt (tei) request disabled * (initial value) 1 transmit-end interrupt (tei) request enabled * note: * tei cancellation can be performed by reading 1 from the tdre flag in ssr1, then clearing it to 0 and clearing the tend flag to 0, or clearing the teie bit to 0. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 401 of 1174 rej09b0329-0200 bits 1 and 0 ? clock enable 1 and 0 (cke1, cke0): these bits are used to select the sci clock source and enable or disable clock output from the sck pin. the combination of the cke1 and cke0 bits determines whether the sck pin functions as an i/o port, the serial clock output pin, or the serial clock input pin. the setting of the cke0 bit, however, is only valid for internal clock operation (cke1 = 0) in asynchronous mode. the cke0 bit setting is invalid in synchronous mode, and in the case of external clock operation (cke1 = 1). note that the sci's operating mode must be decided using smr1 before setting the cke1 and cke0 bits. for details of clock source selection, see table 22.9. bit 1 bit 0 cke1 cke0 description asynchronous mode internal clock/sck1 pin functions as i/o port * 1 0 clock synchronous mode internal clock/sck1 pin functions as serial clock output * 1 asynchronous mode internal clock/sck1 pin functions as clock output * 2 0 1 clock synchronous mode internal clock/sck1 pin functions as serial clock output 1 asynchronous mode external clock/sck1 pin functions as clock input * 3 0 clock synchronous mode external clock/sck1 pin functions as serial clock input asynchronous mode external clock/sck1 pin functions as clock input * 3 clock synchronous mode external clock/sck1 pin functions as serial clock input notes: 1. initial value. 2. outputs a clock of the same frequency as the bit rate. 3. inputs a clock with a frequency 16 times the bit rate. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 402 of 1174 rej09b0329-0200 22.2.7 serial status register 1 (ssr1) 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r note: * only 0 can be written to clear the flag. bit : initial value : r/w : ssr1 is an 8-bit register containing status flags that indicate the operating status of the sci, and multiprocessor bits. ssr1 can be read or written to by the cpu at a ll times. however, 1 cannot be written to flags tdre, rdrf, orer, per, and fer. also note that in order to clear these flags they must be read as 1 beforehand. the tend flag and mpb fl ag are read-only flags and cannot be modified. ssr1 is initialized to h'84 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. bit 7 ? transmit data register empty (tdre): indicates that data has been transferred from tdr1 to tsr1 and the next serial data can be written to tdr1. bit 7 tdre description 0 [clearing condition] when 0 is written in tdre after reading tdre = 1 1 [setting conditions] (initial value) 1. when the te bit in scr1 is 0 2. when data is transferred from tdr1 to tsr1 and data can be written to tdr1 section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 403 of 1174 rej09b0329-0200 bit 6 ? receive data register full (rdrf): indicates that the received data is stored in rdr1. bit 6 rdrf description 0 [clearing condition] (initial value) when 0 is written in rdrf after reading rdrf = 1 1 [setting condition] when serial reception ends normally and receive data is transferred from rsr1 to rdr1 note: rdr1 and the rdrf flag are not affected and retain their previous values when an error is detected during reception or when the re bit in scr1 is cleared to 0. if reception of the next data is completed while the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost. bit 5 ? overrun error (orer): indicates that an overrun error occurred during reception, causing abnormal termination. bit 5 orer description 0 [clearing condition] (initial value) * 1 when 0 is written in orer after reading orer = 1 * 1 1 [setting condition] when the next serial reception is completed while rdrf = 1 * 2 notes: 1. the orer flag is not affected and retains its previous state when the re bit in scr1 is cleared to 0. 2. the receive data prior to the overrun error is retained in rdr1, and the data received subsequently is lost. also, subsequent serial reception cannot be continued while the orer flag is set to 1. in synchronous mode, serial transmission cannot be continued, either. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 404 of 1174 rej09b0329-0200 bit 4 ? framing error (fer): indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. bit 4 fer description 0 [clearing condition] (initial value) when 0 is written in fer after reading fer = 1 * 1 1 [setting condition] when the sci checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0 * 2 notes: 1. the fer flag is not affected and retains its previous state when the re bit in scr1 is cleared to 0. 2. in 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. if a framing error occurs, the receive data is transferred to rdr1 but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the fer flag is set to 1. in synchronous mode, serial transmission cannot be continued, either. bit 3 ? parity error (per): indicates that a parity error oc curred during reception using parity addition in asynchronous mode, causing abnormal termination. bit 4 per description 0 [clearing condition] (initial value) when 0 is written in per after reading per = 1 * 1 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr1 * 2 notes: 1. the per flag is not affected and retains its previous state when the re bit in scr1 is cleared to 0. 2. if a parity error occurs, the receive data is transferred to rdr1 but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the per flag is set to 1. in synchronous mode, serial transmission cannot be continued, either. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 405 of 1174 rej09b0329-0200 bit 2 ? transmit end (tend): indicates that there is no valid data in tdr when the last bit of the transmit character is sent, a nd transmission has been ended. the tend flag is read-only and cannot be modified. bit 2 tend description 0 [clearing condition] when 0 is written in tdre after reading tdre = 1 1 [setting conditions] (initial value) 1. when the te bit in scr1 is 0 2. when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character bit 1 ? multiprocessor bit (mpb): when reception is performed using a multiprocessor format in asynchronous mode, mpb stores the multiprocessor bit in the receive data. mpb is a read-only bit, and cannot be modified. bit 1 mpb description 0 [clearing condition] (initial value) when data with a 0 multiprocessor bit is received * 1 [setting condition] when data with a 1 multiprocessor bit is received note: * retains its previous state when the re bit in scr1 is cleared to 0 with multiprocessor format. bit 0 ? multiprocessor bit transfer (mpbt): when transmission is performed using a multiprocessor format in asynchronous mode, mpbt stores the multiprocessor bit to be added to the transmit data. the mpbt bit setting is invalid when a multiprocessor format is not used, when not transmitting, and in synchronous mode. bit 0 mpbt description 0 data with a 0 multiprocessor bit is transmitted (initial value) 1 data with a 1 multiprocessor bit is transmitted section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 406 of 1174 rej09b0329-0200 22.2.8 bit rate register 1 (brr1) 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit : initial value : r/w : brr1 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 in smr1. brr1 can be read or written to by the cpu at all times. brr1 is initialized to h'ff by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. table 22.3 shows sample brr1 settings in asynchronous mode, and table 22.4 shows sample brr1 settings in synchronous mode. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 407 of 1174 rej09b0329-0200 table 22.3 brr1 settings for various bit rates (asynchronous mode) operating frequency (mhz) 2 2.097152 2.4576 3 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 1 141 0.03 1 148 ? 0.04 1 174 ? 0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 ? 0.71 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.12 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 ? 2.54 0 15 0.00 0 19 ? 2.40 9600 ? ? ? 0 6 ? 2.54 0 7 0.00 0 9 ? 2.40 19200 ? ? ? ? ? ? 0 3 0.00 0 4 ? 2.40 31250 0 1 0.00 ? ? ? 0 ? ? 0 2 0.00 38400 ? ? ? ? ? ? 0 1 0.00 ? ? ? operating frequency (mhz) 3.6864 4 4.9152 5 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 64 0.69 2 70 0.03 2 86 0.31 2 88 ? 0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ? 1.38 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.70 19200 0 5 0.00 ? ? ? 0 7 0.00 0 7 1.70 31250 ? ? ? 0 3 0.00 0 4 ? 1.73 0 4 0.00 38400 0 2 0.00 ? ? ? 0 3 0.00 0 3 1.70 section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 408 of 1174 rej09b0329-0200 operating frequency (mhz) 6 6.144 7.3728 8 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 106 ? 0.44 2 108 0.08 2 130 ? 0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 ? 2.40 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 ? 2.40 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.34 ? ? ? 0 7 0.00 38400 0 4 ? 2.40 0 4 0.00 0 5 0.00 ? ? ? operating frequency (mhz) 9.8304 10 bit rate (bits/s) n n error (%) n n error (%) 110 2 174 ? 0.26 2 177 ? 0.25 150 2 127 0.00 2 129 0.16 300 1 255 0.00 2 64 0.16 600 1 127 0.00 1 129 0.16 1200 0 255 0.00 1 64 0.16 2400 0 127 0.00 0 129 0.16 4800 0 63 0.00 0 64 0.16 9600 0 31 0.00 0 32 ? 1.38 19200 0 15 0.00 0 15 1.70 31250 0 9 ? 1.73 0 9 0.00 38400 0 7 0.00 0 7 1.70 section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 409 of 1174 rej09b0329-0200 table 22.4 brr1 settings for various bit rates (synchronous mode) operating frequency (mhz) 2 4 8 10 bit rate (bits/s) n n n n n n n n 110 3 70 ? ? 250 2 124 2 249 3 124 ? ? 500 1 249 2 124 2 249 ? ? 1 k 1 124 1 249 2 124 ? ? 2.5 k 0 199 1 99 1 199 1 249 5 k 0 99 0 199 1 99 1 124 10 k 0 49 0 99 0 199 0 249 25 k 0 19 0 39 0 79 0 99 50 k 0 9 0 19 0 39 0 49 100 k 0 4 0 9 0 19 0 24 250 k 0 1 0 3 0 7 0 9 500 k 0 0 * 0 1 0 3 0 4 1 m 0 0 * 0 1 2.5 m 0 0 * 5 m legend: blank: cannot be set. ? : can be set, but there will be a degree of error. * : continuous transfer is not possible. note: as far as possible, the setting should be made so that the error is no more than 1%. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 410 of 1174 rej09b0329-0200 the brr1 setting is f ound from the following equations. ? asynchronous mode: n = 10 6 ? 1 64 2 2n ? 1 b ? synchronous mode: n = 10 6 ? 1 8 2 2n ? 1 b where b: bit rate (bits/s) n: brr1 setting for baud rate generator (0 n 255) : operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see the table below for the relation between n and the clock.) smr1 setting n clock cks1 cks0 0 0 0 1 /4 0 1 2 /16 1 0 3 /64 1 1 the bit rate error in asynchronous mode is found from the following equation: error (%) = { 10 6 ? 1 } 10 (n + 1) b 64 2 2n ? 1 table 22.5 shows the maximum bit rate for each frequency in asynchrono us mode. tables 22.6 and 22.7 show the maximum bit rates with external clock input. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 411 of 1174 rej09b0329-0200 table 22.5 maximum bit rate for each frequency (asynchronous mode) (mhz) maximum bit rate (bits/s) n n 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 412 of 1174 rej09b0329-0200 table 22.6 maximum bit rate with external clock input (asynchronous mode) (mhz) external input clock (mhz) maximum bit rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 table 22.7 maximum bit rate with external clock input (synchronous mode) (mhz) external input clock (mhz) maximum bit rate (bits/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 413 of 1174 rej09b0329-0200 22.2.9 serial interface mode register 1 (scmr1) 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 ? 1 ? bit : initial value : r/w : scmr1 is an 8-bit readable/writable register used to select sci functions. scmr1 is initialized to h'f2 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. bits 7 to 4 ? reserved: these bits cannot be modified and are always read as 1. bit 3 ? data transfer direction (sdir): selects the serial/parallel conversion format. bit 3 sdir description 0 tdr1 contents are transmitted lsb-first (initial value) receive data is stored in rdr1 lsb-first 1 tdr1 contents are transmitted msb-first receive data is stored in rdr1 msb-first bit 2 ? data invert (sinv): specifies inversion of the data logic level. the sinv bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the o/ e bit in smr1. bit 2 sinv description 0 tdr1 contents are transmitted without modification (initial value) receive data is stored in rdr1 without modification 1 tdr1 contents are inverted before being transmitted receive data is stored in rdr1 in inverted form bit 1 ? reserved: this bit cannot be modified and is always read as 1. bit 0 ? reserved: 1 should not be written in this bit. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 414 of 1174 rej09b0329-0200 22.2.10 module stop control register (mstpcr) 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w mstpcrh mstpcrl mstp15 mstp14 mstp13 mstp12 mstp11 mstp10 mstp9 mstp8 mstp7 mstp6 mstp5 mstp4 mstp3 mstp2 mstp1 mstp0 bit : initial value : r/w : mstpcr, comprising two 8-bit readable/writable registers, performs module stop mode control. when bit mstp8 is set to 1, sci1 operation stops at the end of the bus cycle and a transition is made to module stop mode. for details, see section 4.5, module stop mode. mstpcr is initialized to h'ffff by a reset. bit 0 ? module stop (mstp8): specifies the sci1 module stop mode. mstpcrh bit 0 mstp8 description 0 sci1 module stop mode is cleared 1 sci1 module stop mode is set (initial value) section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 415 of 1174 rej09b0329-0200 22.3 operation 22.3.1 overview the sci can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. selection of asynchronous or synchronous mode and the transmission format is made using smr1 as shown in table 22.8. the sci clock is determined by a combination of the c/ a bit in smr1 and the cke1 and cke0 bits in scr1, as shown in table 22.9. ? asynchronous mode ? data length: choice of 7 or 8 bits ? choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) ? detection of framing, parity, and overr un errors, and breaks, during reception ? choice of internal or external clock as sci clock source ? when internal clock is selected: the sci operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output ? when external clock is selected: a clock with a frequency of 16 times the bit rate must be input (the built-in baud rate generator is not used) ? clock synchronous mode ? transfer format: fixed 8-bit data ? detection of overrun errors during reception ? choice of internal or external clock as sci clock source ? when internal clock is selected: the sci operates on the baud rate generator clock and a serial clock is output off-chip ? when external clock is selected: the built-in baud rate generator is not used, and the sci operates on the input serial clock section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 416 of 1174 rej09b0329-0200 table 22.8 smr1 settings and serial transfer format selection smr1 settings sci transfer format bit 7 bit 6 bit 2 bit 5 bit 3 c/ a chr mp pe stop mode data length multiproc- essor bit parity bit stop bit length 0 1 bit 0 1 no 2 bits 0 1 bit 0 1 1 8-bit data yes 2 bits 0 1 bit 0 1 no 2 bits 0 1 bit 1 0 1 1 asynchro- nous mode 7-bit data no yes 2 bits ? 0 1 bit 0 ? 1 8-bit data 2 bits ? 0 1 bit 0 1 1 ? 1 asynchro- nous mode (multi- processor format) 7-bit data yes 2 bits 1 ? ? ? ? clock synchronous mode 8-bit data no no table 22.9 smr1 and scr1 settings and sci clock source selection smr1 scr1 setting bit 7 bit 1 bit 0 sci transfer clock c/ a cke1 cke0 mode clock source sck pin function 0 sci does not use sck pin 0 1 internal outputs clock with same frequency as bit rate 0 0 1 1 asynchronous mode external inputs clock with frequency of 16 times the bit rate 0 0 1 internal outputs serial clock 0 1 1 1 clock synchronous mode external inputs serial clock section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 417 of 1174 rej09b0329-0200 22.3.2 operation in asynchronous mode in asynchronous mode, characters are sent or r eceived, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. serial communication is thus carried out with synchronization established on a character-by- character basis. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication. both the transmitter and the receive r also have a double-buffered structure, so that data can be read or written during tran smission or reception, enabling continuous data transfer. figure 22.2 shows the general format for asynchronous serial communication. in asynchronous serial communication, the transmission line is usually held in the mark state (high level). the sci monitors the tran smission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. one serial communication character consists of a start bit (low level), followed by data (in lsb- first order), a parity bit (high or low level), and finally one or two stop bits (high level). in asynchronous mode, the sci performs synchronization at the falling edge of the start bit in reception. the sci samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. lsb start bit msb idle state (mark state) stop bit(s) 0 transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 1 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit, or none one unit of transfer data (character or frame) figure 22.2 data format in asynchronous communication (example with 8-bit data, parity, two stop bits) section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 418 of 1174 rej09b0329-0200 ? data transfer format table 22.10 shows the data transfer formats that can be used in asynchronous mode. any of 12 transfer formats can be selected by settings in smr1. table 22.10 serial transfer formats (asynchronous mode) pe 0 0 1 1 0 0 1 1 ? ? ? ? s 8-bit data stop s 7-bit data stop s 8-bit data stop stop s 8-bit data p stop s 7-bit data stop p s 8-bit data mpb stop s 8-bit data mpb stop stop s 7-bit data stop mpb s 7-bit data stop mpb stop s 7-bit data stop stop chr 0 0 0 0 1 1 1 1 0 0 1 1 mp 0 0 0 0 0 0 0 0 1 1 1 1 stop 0 1 0 1 0 1 0 1 0 1 0 1 smr1 settings 123456789101112 serial transfer format and frame length stop s 8-bit data p stop s 7-bit data stop p stop legend: s: start bit stop: stop bit p: parity bit mpb: multiproccesor bit section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 419 of 1174 rej09b0329-0200 ? clock either an internal clock generated by the built-in baud rate generator or an external clock input at the sck pin can be selected as the sci's serial clock, according to the setting of the c/ a bit in smr1 and the cke1 and cke0 bits in scr1. for details of sci clock source selection, see table 22.9. when an external clock is input at the sck pin, the clock frequency should be 16 times the bit rate used. when the sci is operated on an internal clock, the clock can be output from the sck pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is at the center of each transmit data bit, as shown in figure 22.3. 0 1 frame d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 figure 22.3 relation between output clock and transfer data phase (asynchronous mode) section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 420 of 1174 rej09b0329-0200 ? data transfer operations ? sci initialization (asynchronous mode) before transmitting and receiving data, first clear the te and re bits in scr1 to 0, then initialize the sci as described below. when the operating mode, transfer format, etc ., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1 and tsr1 is initialized. note that clearing the re bit to 0 does not change the contents of the rdrf, per, fer, and orer flags, or the contents of rdr1. when an external clock is used the clock should not be stopped during operation, including initialization, since operation is uncertain. figure 22.4 shows a sample sci initialization flowchart. wait section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 421 of 1174 rej09b0329-0200 ? serial data transmission (asynchronous mode) figure 22.5 shows a sample flowchart for serial transmission. the following procedure should be used for serial data transmission. no < end > [1] yes initialization start transmission read tdre flag in ssr1 [1] write transmit data to tdr1 and clear tdre flag in ssr to 0 no yes no yes read tend flag in ssr1 [3] no yes [4] clear pdr to 0 and set pcr to 1 clear te bit in scr1 to 0 tdre = 1 all data transmitted? tend = 1 break output? sci initialization: the so1 pin is automatically designated as the transmit data output pin. sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr1 and clear the tdre flag to 0. serial transmission continuation procedure: to continue serial transmission, read 1 from the tdre flag to confirm that writing is possible, then write data to tdr1, and then clear the tdre flag to 0. break output at the end of serial transmission: to output a break in serial transmission, set pcr for the port corresponding to the so1 pin to 1, clear pdr to 0, then clear the te bit in scr1 to 0. [1] [2] [3] [4] figure 22.5 sample serial transmission flowchart section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 422 of 1174 rej09b0329-0200 in serial transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr1, and if it is 0, recognizes that data has been written to tdr1, and transfers the data from tdr1 to tsr1. 2. after transferring data from tdr1 to tsr1, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a transmit data empty interrupt (txi) is generated. the serial transmit data is sent from the so1 pin in the following order. a. start bit: one 0-bit is output. b. transmit data: 8-bit or 7-bit data is output in lsb-first order. c. parity bit or multiprocessor bit: one parity bit (even or odd parity), or one multiprocessor bit is output. a format in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. stop bit(s): one or two 1-bits (stop bits) are output. e. mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. the sci checks the tdre flag at the timing for sending the stop bit. if the tdre flag is cleared to 0, the data is transferred from tdr1 to tsr1, the stop bit is sent, and then serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr1 is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. if the teie bit in scr1 is set to 1 at this time, a tei interrupt request is generated. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 423 of 1174 rej09b0329-0200 figure 22.6 shows an example of the operation for transmission in asynchronous mode. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit parity bit stop bit start bit data parity bit stop bit txi interrupt request generated data written to tdr1 and tdre flag cleared to 0 in txi interrupt handling routine tei interrupt request generated idle state (mark state) txi interrupt request generated figure 22.6 example of operation in transmission in asynchronous mode (example with 8-bit data, parity, one stop bit) section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 424 of 1174 rej09b0329-0200 ? serial data reception (asynchronous mode) figures 22.7 and 22.8 show sample flowcharts for serial reception. the following procedure should be used for serial data reception. yes < end > [1] no initialization start reception [2] no yes read rdrf flag in ssr1 [4] [5] clear re bit in scr1 to 0 read orer, per, fer flags in ssr1 error handling (continued on next page) [3] read receive data in rdr1, and clear rdrf flag in ssr1 to 0 no yes per fer orer = 1 rdrf = 1 all data received? sci initialization: the si1 pin is automatically designated as the receive data input pin. receive error handling and break detection: if a receive error occurs, read the orer, per, and fer flags in ssr1 to identify the error. after performing the appropriate error handling, ensure that the orer, per, and fer flags are all cleared to 0. reception cannot be resumed if any of these flags are set to 1. in the case of a framing error, a break can be detected by reading the value of the input port corresponding to the si1 pin. sci status check and receive data read: read ssr1 and check that rdrf = 1, then read the receive data in rdr1 and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. serial reception continuation procedure: to continue serial reception, before the stop bit for the current frame is received, read the rdrf flag, read rdr1, and clear the rdrf flag to 0. [1] [2][3] [4] [5] figure 22.7 sample serial reception data flowchart (1) section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 425 of 1174 rej09b0329-0200 < end > [3] error handling parity error handling yes no clear orer, per, and fer flags in ssr1 to 0 no yes no yes framing error handling no yes overrun error handling orer = 1 fer = 1 break? per = 1 clear re bit in scr1 to 0 figure 22.8 sample serial reception data flowchart (2) section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 426 of 1174 rej09b0329-0200 in serial reception, the sci op erates as described below. 1. the sci monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. 2. the received data is stored in rsr1 in lsb-to-msb order. 3. the parity bit and stop bit are received. after receiving these bits, the sci carries out the following checks. a. parity check: the sci checks whether the number of 1 bits in the receive da ta agrees with the parity (even or odd) set in the o/ e bit in smr1. b. stop bit check: the sci checks whether the stop bit is 1. if there are two stop bits, only the first is checked. c. status check: the sci checks whether the rdrf flag is 0, indicating that the receive data can be transferred from rsr1 to rdr1. if all the above checks are passed , the rdrf flag is set to 1, and the receive data is stored in rdr1. if a receive error* is detected in the error ch eck, the operation is as shown in table 22.11. 4. if the rie bit in scr1 is se t to 1 when the rdrf flag ch anges to 1, a receive-data-full interrupt (rxi) request is generated. also, if the rie bit in scr1 is set to 1 when the orer, per, or fer flag changes to 1, a receive-error interrupt (eri) request is generated. note: * subsequent receive ope rations cannot be performed when a receive error has occurred. also note that the rdrf flag is not set to 1 in reception, and so the error flags must be cleared to 0. table 22.11 receive errors and conditions for occurrence receive error abbrev. occurrence condition data transfer overrun error orer when the next data reception is completed while the rdrf flag in ssr1 is set to 1 receive data is not transferred from rsr1 to rdr1 framing error fer when the stop bit is 0 receive data is transferred from rsr1 to rdr1 parity error per when the received data differs from the parity (even or odd) set in smr1 receive data is transferred from rsr1 to rdr1 section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 427 of 1174 rej09b0329-0200 figure 22.9 shows an example of the operation for reception in asynchronous mode. rdrf fer 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 0 1 1 data start bit parity bit stop bit start bit data parity bit stop bit eri interrupt request generated by framing error idle state (mark state) rdr1 data read and rdrf flag cleared to 0 in rxi interrupt handling routine rxi interrupt request generation figure 22.9 example of sc i operation in reception (example with 8-bit data, parity, one stop bit) 22.3.3 multiprocessor communication function the multiprocessor communication function performs serial communication using a multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. use of this function enables data transfer to be performed among a number of processors sharing transmission lines. when multiprocessor communication is carried out, each receiving station is addressed by a unique id code. the serial communication cycle consists of tw o component cycles: an id transmission cycle which specifies the receiving station, and a data transmission cycle. the multiprocessor bit is used to differentiate between the id transmissi on cycle and the data transmission cycle. the transmitting station first sends the id of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. the receiving station skips the data until data with a 1 multiprocessor bit is sent. when data with a 1 multiprocessor bit is received, the receiving station compares that data with its own id. the station whose id matc hes then receives the data sent next. stations whose id does not match continue to skip the data until data with a 1 multiprocessor bit is again received. in this way, data communication is carried out among a number of processors. figure 22.10 shows an example of inter-processor communication using a multiprocessor format. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 428 of 1174 rej09b0329-0200 1. data transfer format there are four data transfer formats. when a multiprocessor format is specified, the parity bit specification is invalid. for details, see table 22.10. 2. clock see the section on asynchronous mode. transmitting station receiving station a (id = 01) receiving station b (id = 02) receiving station c (id = 03) receiving station d (id = 04) serial communication line serial data id transmission cycle: receiving station specification data transmission cycle: data transmission to receiving station specified by id (mpb = 1) (mpb = 0) h'01 h'aa legend: mpb : multiprocessor bit figure 22.10 example of inter-processor communication using mu ltiprocessor format (transmission of data h'aa to receiving station a) 3. data transfer operations a. multiprocessor serial data transmission figure 22.11 shows a sample flowchart for multiprocessor serial data transmission. the following procedure should be used for multiprocessor serial data transmission. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 429 of 1174 rej09b0329-0200 no < end > [1] yes initialization start transmission read tdre flag in ssr1 [2] write transmit data to tdr1 and set mpbt bit in ssr1 no yes no yes read tend flag in ssr1 [3] no yes [4] clear pdr to 0 and set pcr to 1 clear te bit in scr1 to 0 tdre = 1 transmission end? tend = 1 break output? clear tdre flag to 0 sci initialization: the so1 pin is automatically designated as the transmit data output pin. sci status check and transmit data write: read ssr1 and check that the tdre flag is set to 1, then write transmit data to tdr1. set the mpbt bit in ssr1 to 0 or 1. finally, clear the tdre flag to 0. serial transmission continuation procedure: to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr1, and then clear the tdre flag to 0. break output at the end of serial transmission: to output a break in serial transmission, set the port pcr to 1, clear pdr to 0, then clear the te bit in scr1 to 0. [1] [2] [3] [4] figure 22.11 sample multiprocessor serial transmission flowchart section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 430 of 1174 rej09b0329-0200 in serial transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr1, and if it is 0, recognizes that data has been written to tdr1, and transfers the data from tdr1 to tsr1. 2. after transferring data from tdr1 to tsr1, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a transmit-data-empty interrupt (txi) is generated. the serial transmit data is sent from the so2 pin in the following order. a. start bit: one 0-bit is output. b. transmit data: 8-bit or 7-bit data is output in lsb-first order. c. multiprocessor bit one multiprocessor bit (mpbt value) is output. d. stop bit(s): one or two 1-bits (stop bits) are output. e. mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. the sci checks the tdre flag at the timing for sending the stop bit. if the tdre flag is cleared to 0, data is transferred from tdr1 to tsr1, the stop bit is sent, and then serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr1 is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. if the teie bit in scr1 is set to 1 at this time, a transmit-end interrupt (tei) request is generated. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 431 of 1174 rej09b0329-0200 figure 22.12 shows an example of sci operation for transmission using a multiprocessor format. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 data data txi interrupt request general data written to tdr1 and tdre flag cleared to 0 in txi interrupt handling routine tei interrupt request generated idle state (mark state) txi interrupt request generated start bit multi- processor bit stop bit start bit stop bit 1 multi- processor bit figure 22.12 example of sci operation in transmission (example with 8-bit data, multip rocessor bit, one stop bit) b. multiprocessor serial data reception figures 22.13 and 22.14 show sample flowcharts for multiprocessor serial reception. the following procedure should be used for multiprocessor serial data reception. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 432 of 1174 rej09b0329-0200 yes < end > [1] no initialization start reception no yes [4] clear re bit in scr1 to 0 error handling (continued on next page) [5] no yes fer orer = 1 rdrf = 1 all data received? set mpie bit in scr1 to 1 [2] read orer and fer flags in ssr1 read rdrf flag in ssr1 [3] read receive data in rdr1 no yes this station's id? read orer and fer flags in ssr1 yes no read rdrf flag in ssr1 no yes fer orer = 1 read receive data in rdr1 rdrf = 1 sci initialization: the si1 pin is automatically designated as the receive data input pin. id reception cycle: set the mpie bit in scr1 to 1. sci status check, id reception and comparison: read ssr1 and check that the rdrf flag is set to 1, then read the receive data in rdr1 and compare it with this station's id. if the data is not this station's id, set the mpie bit to 1 again, and clear the rdrf flag to 0. if the data is this station's id, clear the rdrf flag to 0. sci status check and data reception: read ssr1 and check that the rdrf flag is set to 1, then read the data in rdr1. receive error handling and break detectioon: if a receive error occurs, read the orer and fer flags in ssr1 to identify the error. after performing the appropriate error handling, ensure that the orer and fer flags are both cleared to 0. reception cannot be resumed if either of these flags is set to 1. in the case of a framing error, a break can be detected by reading the si1 in value. [1] [2] [3] [4] [5] figure 22.13 sample multiprocesso r serial reception flowchart (1) section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 433 of 1174 rej09b0329-0200 < end > error handling yes no clear orer, per, and fer flags in ssr1 to 0 no yes no yes framing error handling overrun error handling orer = 1 fer = 1 break? clear re bit in scr1 to 0 [5] figure 22.14 sample multiprocesso r serial reception flowchart (2) section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 434 of 1174 rej09b0329-0200 figure 22.15 shows an example of sci operation for multiprocessor format reception. mpie rdr1 value 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 1 data (id1) start bit mpb stop bit start bit data (data 1) mpb stop bit rxi interrupt request (multi- processor interrupt) generated idle state (mark state) rdrf rdr1 data read and rdrf flag cleared to 0 in rxi interrupt handling routine if not this station's id, mpie bit is set to 1 again rxi interrupt request is not generated, and rdr1 retains its state id1 (a) data does not match station's id mpie rdr1 value 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 1 data (id2) start bit mpb stop bit start bit data (data 2) mpb stop bit rxi interrupt request (multi- processor interrupt) generated idle state (mark state) rdrf rdr1 data read and rdrf flag cleared to 0 in rxi interrupt handling routine matches this station's id, so reception continues, and data is received in rxi interrupt handling routine mpie bit set to 1 again id2 (b) data matches station's id data2 id1 mpie = 0 mpie = 0 figure 22.15 example of sci operation in reception (example with 8-bit data, multip rocessor bit, one stop bit) section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 435 of 1174 rej09b0329-0200 22.3.4 operation in synchronous mode in synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. figure 22.16 shows the general format for synchronous serial communication. don't care don't care one unit of transfer data (character or frame) bit 0 serial data synchronous clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * * note: * high except in continuous transfer figure 22.16 data format in synchronous communication in synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. data is guaranteed valid at the rising edge of the serial clock. in synchronous serial communication, one character consists of data output starting with the lsb and ending with the msb. after the msb is output, the transmission line holds the msb state. in synchronous mode, the sci receives data in s ynchronization with the risi ng edge of the serial clock. ? data transfer format a fixed 8-bit data format is used. no parity or multiprocessor bits are added. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 436 of 1174 rej09b0329-0200 ? clock either an internal clock generated by the built-in baud rate generator or an external serial clock input at the sck pin can be select ed, according to the setting of the c/ a bit in smr1 and the cke1 and cke0 bits in scr1. for details on sci clock source selection, see table 22.9. when the sci is operated on an internal clock, the serial clock is output from the sck pin. eight serial clock pulses are out put in the transfer of one char acter, and when no transfer is performed the clock is fixed high. when only receive operations are performed, however, the serial clock is output until an overrun error occurs or the re bit is cleared to 0. to perform receive operations in units of one character, se lect an external cloc k as the clock source. ? data transfer operations ? sci initialization (synchronous mode) before transmitting and receiving data, first clear the te and re bits in scr1 to 0, then initialize the sci as described below. when the operating mode, transfer format, etc ., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1 and tsr1 is initialized. note that clearing the re bit to 0 does not change the settings of the rdrf, per, fer, and orer flags, or the contents of rdr1. figure 22.17 shows a sample sci initialization flowchart. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 437 of 1174 rej09b0329-0200 wait section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 438 of 1174 rej09b0329-0200 ? serial data transmission (synchronous mode) figure 22.18 shows a sample flowchart for serial transmission. the following procedure should be used for serial data transmission. no < end > [1] yes initialization start transmission read tdre flag in ssr1 [2] write transmit data to tdr1 and clear tdre flag in ssr1 to 0 no yes no yes read tend flag in ssr1 [3] clear te bit in scr1 to 0 tdre = 1 all data transmitted? tend = 1 sci initialization: the so1 pin is automatically designated as the transmit data output pin. sci status check and transmit data write: read ssr1 and check that the tdre flag is set to 1, then write transmit data to tdr1 and clear the tdre flag to 0. serial transmission continuation procedure: to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr1, and then clear the tdre flag to 0. [1] [2] [3] figure 22.18 sample serial transmission flowchart section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 439 of 1174 rej09b0329-0200 in serial transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr1, and if it is 0, recognizes that data has been written to tdr1, and transfers the data from tdr1 to tsr1. 2. after transferring data from tdr1 to tsr1, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a transmit-data-empty interrupt (txi) is generated. when clock output mode has been set, the sci outputs 8 serial clock pulses. when use of an external clock has been specified, data is output synchronized with the input clock. the serial transmit data is sent from the so1 pin starting with the lsb (bit 0) and ending with the msb (bit 7). 3. the sci checks the tdre flag at the timing for sending the msb (bit 7). if the tdre flag is cleared to 0, data is transferred from tdr1 to tsr1, and serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr1 is set to 1, the msb (bit 7) is sent, and the so1 pin maintains its state. if the teie bit in scr1 is set to 1 at this time, a transmit-end interrupt (tei) request is generated. 4. after completion of serial transmission, the sck pin is held in a constant state. figure 22.19 shows an example of sci operation in transmission. transfer direction bit 0 serial data synchronous clock 1 frame tdre tend data written to tdr1 and tdre flag cleared to 0 in txi interrupt handling routine txi interrupt request generated bit 1 bit 7 bit 0 bit 1 bit 6 bit 7 txi interrupt request generated tei interrupt request generated figure 22.19 example of sci operation in transmission section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 440 of 1174 rej09b0329-0200 ? serial data reception (synchronous mode) figure 22.20 shows a sample flow chart for serial reception. the following procedure should be used for serial data reception. when changing the operating mode from asynchronous to synchronous, be sure to check that the orer, per, and fer flags are all cleared to 0. the rdrf flag will not be set if the fer or per flag is set to 1, and neither transmit nor receive operations will be possible. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 441 of 1174 rej09b0329-0200 yes < end > [1] no initialization start reception [2] no yes read rdrf flag in ssr1 [4] [5] clear re bit in scr1 to 0 error handling (continued below) [3] read receive data in rdr1, and clear rdrf flag in ssr1 to 0 no yes orer = 1 rdrf = 1 all data received? read orer flag in ssr1 < end > error handling clear orer flag in ssr1 to 0 overrun error handling [3] sci initialization: the si1 pin is automatically designated as the receive data input pin. receive error handling: if a receive error occurs, read the orer flag in ssr1, and after performing the appropriate error handling, clear the orer flag to 0. transfer cannot be resumed if the orer flag is set to 1. sci status check and receive data read: read ssr1 and check that the rdrf flag is set to 1, then read the receive data in rdr1 and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by and rxi interrupt. serial reception continuation procedure: to continue serial reception, before the msb (bit 7) of the current frame is received, finish reading the rdrf flag, reading rdr1, and clearing the rdrf flag to 0. [1] [2][3] [4] [5] figure 22.20 sample s erial reception flowchart section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 442 of 1174 rej09b0329-0200 in serial reception, the sci op erates as described below. 1. the sci performs internal initialization in synchronization with serial clock input or output. 2. the received data is stored in rsr1 in lsb-to-msb order. after reception, the sci checks whether the rdrf flag is 0 and the receive data can be transferred from rsr1 to rdr1. if this check is passed, the rdrf flag is set to 1, and the receive data is stored in rdr1. if a receive error is detected in the error check , the operation is as shown in table 22.11. neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. 3. if the rie bit in scr1 is se t to 1 when the rdrf flag ch anges to 1, a receive-data-full interrupt (rxi) request is generated. also, if the rie bit in scr1 is set to 1 when the orer flag changes to 1, a receive-error interrupt (eri) request is generated. figure 22.21 shows an example of sci operation in reception. bit 7 serial data synchronous clock 1 frame rdrf orer eri interrupt request generated by overrun error rxi interrupt request generated rdr1 data read and rdrf flag cleared to 0 in rxi interrupt handling routine rxi interrupt request generated bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 figure 22.21 example of sci operation in reception section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 443 of 1174 rej09b0329-0200 ? simultaneous serial data transmissi on and reception (synchronous mode) figure 22.22 shows a sample flowchart for simultaneous serial transmit and receive operations. the following procedure should be used for simultaneous serial data transmit and receive operations. yes < end > [1] no initialization start transfer [5] error handling [3] read receive data in rdr1, and clear rdrf flag in ssr1 to 0 no yes orer = 1 all data received? [2] read tdre flag in ssr1 no yes tdre = 1 write transmit data to tdr1 and clear tdre flag in ssr1 to 0 no yes rdrf = 1 read orer flag in ssr1 [4] read rdrf flag in ssr1 clear te and re bits in scr1 to 0 note: when switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the te bit and re bit to 0, then set both these bits to 1 simultaneously. sci initialization: the so1 pin is designated as the transmit data output pin, and the si1 pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. sci status check and transmit data write: read ssr1 and check that the tdre flag is set to 1, then write transmit data to tdr1 and clear the tdre flag to 0. transition of the tdre flag from 0 to 1 can also be identified by a txi interrupt. receive error handling: if a receive error occurs, read the orer flag in ssr1, and after performing the appropriate error handling, clear the orer flag to 0. transmission/reception cannot be resumed if the orer flag is set to 1. sci status check and receive data read: read ssr1 and check that the rdrf flag is set to 1, then read the receive data in rdr1 and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. serial transmission/reception continuation procedure: to continue serial transmission/reception, before the msb (bit 7) of the current frame is received, finish reading the rdrf flag, reading rdr1, and clearing the rdrf flag to 0. also before the msb (bit 7) of the current frame is transmitted, read 1 from the tdre flag to confirm that writing is possible, then write data to tdr1 and clear the tdre flag to 0. [1] [2] [3] [4] [5] figure 22.22 sample flowchar t of simultaneous serial tr ansmit and receive operations section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 444 of 1174 rej09b0329-0200 22.4 sci interrupts the sci has four interrupt sources: the transmit-end interrupt (tei) request, receive-error interrupt (eri) request, receive-data-full interrupt (rxi) request, and transmit-data-empty interrupt (txi) request. table 22.12 shows the interrupt sources and their relative priorities. individual interrupt sources can be enabled or disabled with the tie, rie, and teie bits in scr1. each kind of interrupt request is sent to the interrupt controller independently. when the tdre flag in ssr1 is set to 1, a txi interrupt request is generated. when the tend flag in ssr1 is set to 1, a tei interrupt request is generated. when the rdrf flag in ssr1 is set to 1, an rx i interrupt request is generated. when the orer, per, or fer flag in ssr1 is set to 1, an eri interrupt request is generated. table 22.12 sci interrupt sources channel interrupt source description priority eri interrupt by receive error (orer, fer, or per) rxi interrupt by receive data register full (rdrf) txi interrupt by transmit data register empty (tdre) 1 tei interrupt by transmit end (tend) high low the tei interrupt is requested when the tend flag is set to 1 while the teie bit is set to 1. the tend flag is cleared at the same time as the tdre flag. consequently, if a tei interrupt and a txi interrupt are requested simultaneously, the txi interrupt will have priority for acceptance, and the tdre flag and tend flag may be cleared. note that the tei interrupt will not be accepted in this case. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 445 of 1174 rej09b0329-0200 22.5 usage notes the following points should be noted when using the sci. ? relation between writes to tdr1 and the tdre flag the tdre flag in ssr1 is a status flag that i ndicates that transmit data has been transferred from tdr1 to tsr1. when the sci transfers data from tdr1 to tsr1, the tdre flag is set to 1. data can be written to tdr1 regardless of the state of the tdre flag. however, if new data is written to tdr1 when the tdre flag is cleared to 0, the data stored in tdr1 will be lost since it has not yet been transferred to tsr1. it is therefore essential to check that the tdre flag is set to 1 before writing transmit data to tdr1. ? operation when multiple receive errors occur simultaneously if a number of receive errors occur at the same tim e, the state of the status flags in ssr1 is as shown in table 22.13. if there is an overrun error, data is not transferred from rsr1 to rdr1, and the receive data is lost. table 22.13 state of ssr1 status flags and transfer of receive data ssr1 status flags receive data transfer rdrf orer fer per rsr1 to rdr1 receive error status 1 1 0 0 x overrun error 0 0 1 0 framing error 0 0 0 1 parity error 1 1 1 0 x overrun error + framing error 1 1 0 1 x overrun error + parity error 0 0 1 1 framing error + parity error 1 1 1 1 x overrun error + framing error + parity error notes: : receive data is transferred from rsr1 to rdr1. x: receive data is not transferred from rsr1 to rdr1. ? break detection and processing when framing error (fer) detection is performed, a break can be detected by reading the si1 pin value directly. in a break, the input from the si1 pin becomes all 0s, and so the fer flag is set, and the parity error flag (per) may also be set. note that, since the sci contin ues the receive operation after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 446 of 1174 rej09b0329-0200 ? sending a break the so1 pin has a dual function as an i/o port whose direction (input or output) is determined by pdr and pcr. this can be used to send a break. between serial transmission initialization and setting of the te bit to 1, the mark state is replaced by the value of pdr (the pin does not function as the so1 pin until the te bit is set to 1). consequently, pcr and pdr for the port corresponding to the so1 pin are first set to 1. to send a break during serial transmission, first clear pdr to 0, then clear the te bit to 0. when the te bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the so1 pin becomes an i/o port, and 0 is output from the so1 pin. ? receive error flags and transmit operati ons (clocked synchronous mode only) transmission cannot be started when a receive error flag (orer, per, or fer) is set to 1, even if the tdre flag is cleared to 0. be sure to clear the receive error flags to 0 before starting transmission. note also that receive error flag s cannot be cleared to 0 even if the re bit is cleared to 0. ? receive data sampling timing and recep tion margin in asynchronous mode in asynchronous mode, the sci operates on a basic clock with a frequency of 16 times the transfer rate. in reception, the sci samples the falling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 8th pulse of the basic clock. this is illustrated in figure 22.23. internal basic clock 16 clocks 8 clocks receive data synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 0 7 figure 22.23 receive data samplin g timing in asynchronous mode section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 447 of 1174 rej09b0329-0200 thus the reception margin in asynchronous mode is given by formula (1) below. m = | (0.5 ? 1 2n ) ? (l ? 0.5) f ? | d ? 0.5 | n (1 + f) | 100% ... formula (1) where m : reception margin (%) n : ratio of bit rate to clock (n = 16) d : clock duty (d = 0 to 1.0) l : frame length (l = 9 to 12) f : absolute value of clock rate deviation assuming values of f = 0 and d = 0.5 in formula (1), a reception margin of 46.875% is given by formula (2) below. when d = 0.5 and f = 0, m = (0.5 ? 1 2 16 ) 100% = 46.875% ... formula (2) however, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. ? operation in case of mode transition ? transmission operation should be stopped (by clearing te, tie, and teie to 0) before making a module stop mode, standby mode, watch mode, subactive mode, or subsleep mode transition. tsr1, tdr1, and ssr1 are reset. the output pin states in module stop mode, standby mode, watch mode, subactive mode, or subsleep mode depend on the port settings, and becomes high-level output after the relevant mode is cleared. if a transition is made during transmission, the data being transmitted w ill be undefined. when transmitting without changing the transmit mode after the relevant mode is cleared, transmission can be started by setting te to 1 again, and performing the following sequence: ssr1 read tdr1 write tdre clearance. to transmit with a di fferent transmit mode after clearing the relevant mode, the procedure must be started again from initialization. figure 22.24 shows a sample flowchart for mode transition during transmission. port pin states are shown in figures 22.25 and 22.26. section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 448 of 1174 rej09b0329-0200 ? reception receive operation should be stopped (by cleari ng re to 0) before making a module stop mode, standby mode, watch mode, subactive mode, or subsleep mode transition. rsr1, rdr1, and ssr1 are reset. if a transition is made without stopping operation, the data being received will be invalid. to continue receiving without changing the reception mode after the relevant mode is cleared, set re to 1 before starting reception. to receive with a different receive mode, the procedure must be started again from initialization. figure 22.27 shows a sample flowchart for mode transition during reception. read tend flag in ssr1 te = 0 transition to standby mode, etc. exit from standby mode, etc. change operating mode? no all data transmitted? tend = 1 yes yes yes section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 449 of 1174 rej09b0329-0200 sck1 output pin te bit so1 output pin port input/output high output port input/output high output start stop start of transmission end of transmission port input/output sci txd output port sci txd output port transition to standby exit from standby figure 22.25 asynchronous transmission using internal clock port input/output last txd bit held high output * port input/output marking output port input/output sci txd output port port note: * initialized by software standby. sck1 output pin te bit so1 output pin sci txd output start of transmission end of transmission transition to standby exit from standby figure 22.26 synchronous transmission using internal clock section 22 serial communication interface 1 (sci1) rev.2.00 jan. 15, 2007 page 450 of 1174 rej09b0329-0200 re = 0 transition to standby mode, etc. read receive data in rdr1 read rdrf flag in ssr1 exit from standby mode, etc. change operating mode? no rdrf = 1 yes yes section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 451 of 1174 rej09b0329-0200 section 23 i 2 c bus interface (iic) 23.1 overview this lsi incorporates a 2-channel i 2 c bus interface (h8s/2197s and h8s/2196s: 1 channel). the i 2 c bus interface conforms to and provides a subset of the philips i 2 c bus (inter-ic bus) interface functions. the register c onfiguration that controls the i 2 c bus differs partly from the philips configuration, however. each i 2 c bus interface channel uses only one data line (sda) and one clock line (scl) to transfer data, saving board and connector space. 23.1.1 features ? selection of addressing format or non-addressing format ? i 2 c bus format: addressing format with acknowledge bit, for master/slave operation ? serial format: non-addressing format without acknowledge bit, for master operation only ? conforms to philips i 2 c bus interface (i 2 c bus format) ? two ways of setting slave address (i 2 c bus format) ? start and stop conditions generated automatically in master mode (i 2 c bus format) ? selection of acknowledge out put levels when receiving (i 2 c bus format) ? automatic loading of acknowle dge bit when transmitting (i 2 c bus format) ? wait function in master mode (i 2 c bus format) ? a wait can be inserted by driving the sc l pin low after data transfer, excluding acknowledgement. the wait can be cleared by clearing the interrupt flag. ? wait function in slave mode (i 2 c bus format) ? a wait request can be generated by driving the scl pin low after data transfer, excluding acknowledgement. the wait request is cleared when the next transfer becomes possible. ? three interrupt sources ? data transfer end (including transmission mode transition with i 2 c bus format and address reception after loss of master arbitration) ? address match: when any slave address matche s or the general call address is received in slave receive mode (i 2 c bus format) ? stop condition detection ? selection of 16 internal clocks (in master mode) section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 452 of 1174 rej09b0329-0200 ? direct bus drive (with scl and sda pins) ? four pins p26/scl0, p25/sda0, p24/scl1 and p23/sda1 (normally cmos pins) function as nmos-only outputs when the bus drive function is selected. 23.1.2 block diagram figure 23.1 shows a block diagram of the i 2 c bus interface. figure 23.2 shows an example of i/o pin connections to external circuits. i/o pins are driven only by nmos and apparently function as nmos open-drain outputs. however, applicable voltages to input pins depend on the power (vcc) voltage of this lsi. scl ps noise canceller bus state decision circuit output data control circuit iccr clock control icmr icsr icdrs address comparator arbitration decision circuit sar, sarx sda noise canceler interrupt generator interrupt request internal data bus legend: iccr icmr icsr icdr sar sarx ps : i 2 c control register : i 2 c mode register : i 2 c status register : i 2 c data register : slave address register : slave address register x : prescaler icdrr icdrt figure 23.1 block diagram of i 2 c bus interface section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 453 of 1174 rej09b0329-0200 v cc scl in scl out scl sda in sda out (master) this lsi sda scl sda scl in scl out scl sda in sda out (slave 1) sda scl in scl out scl sda in sda out (slave 2) sda figure 23.2 i 2 c bus interface connections (example: this chip as master) 23.1.3 pin configuration table 23.1 summarizes the input/output pins used by the i 2 c bus interface. table 23.1 i 2 c bus interface pins channel name abbrev. * i/o function serial clock pin scl0 input/output iic0 serial clock input/output serial data pin sda0 input/output iic0 serial data input/output 0 formatless serial clock pin synci input iic0 formatless serial clock input 1 serial clock pin scl1 input/output iic1 serial clock input/output serial data pin sda1 input/output iic1 serial data input/output notes: * in this section, channel numbers in the abbreviated register names are omitted; scl0 and scl1 are collectively referred to as scl, and sda0 and sda1 as sda. channel 0 is not provided (incorporated in) for the h8s/2197s and h8s/2196s. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 454 of 1174 rej09b0329-0200 23.1.4 register configuration table 23.2 summarizes the registers of the i 2 c bus interface. table 23.2 register configuration channel name abbrev. r/w initial value address * 1 0 * 3 i 2 c bus control register iccr0 r/w h'01 h'd0e8 i 2 c bus status register icsr0 r/w h'00 h'd0e9 i 2 c bus data register icdr0 r/w ? h'd0ee * 2 i 2 c bus mode register icmr0 r/w h'00 h'd0ef * 2 slave address register sar0 r/w h'00 h'd0ef * 2 second slave address register sarx0 r/w h'01 h'd0ee * 2 1 i 2 c bus control register iccr1 r/w h'01 h'd158 i 2 c bus status register icsr1 r/w h'00 h'd159 i 2 c bus data register icdr1 r/w ? h'd15e * 2 i 2 c bus mode register icmr1 r/w h'00 h'd15f * 2 slave address register sar1 r/w h'00 h'd15f * 2 second slave address register sarx1 r/w h'01 h'd15e * 2 0 and 1 ddc switch register ddcswr r/w h'0f h'd0e5 module stop control register mstpcrh mstpcrl r/w h'ff h'ff h'ffec h'ffed notes: 1. lower 16 bits of the address. 2. the registers that can be read from or written to depend on the ice bit in the i 2 c bus control register. the slave address registers can be accessed when ice = 0, and the i 2 c bus mode registers can be accessed when ice = 1. 3. channel 0 is not provided (incorporated in) for the h8s/2197s and h8s/2196s. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 455 of 1174 rej09b0329-0200 23.2 register descriptions 23.2.1 i 2 c bus data register (icdr) 7 icdr7 ? r/w 6 icdr6 ? r/w 5 icdr5 ? r/w 4 icdr4 ? r/w 3 icdr3 ? r/w 0 icdr0 ? r/w 2 icdr2 ? r/w 1 icdr1 ? r/w bit : initial value : r/w : icdrr 7 icdrr7 ? r 6 icdrr6 ? r 5 icdrr5 ? r 4 icdrr4 ? r 3 icdrr3 ? r 0 icdrr0 ? r 2 icdrr2 ? r 1 icdrr1 ? r bit : initial value : r/w : icdrs 7 icdrs7 ? ? 6 icdrs6 ? ? 5 icdrs5 ? ? 4 icdrs4 ? ? 3 icdrs3 ? ? 0 icdrs0 ? ? 2 icdrs2 ? ? 1 icdrs1 ? ? bit : initial value : r/w : icdrt 7 icdrt7 ? w 6 icdrt6 ? w 5 icdrt5 ? w 4 icdrt4 ? w 3 icdrt3 ? w 0 icdrt0 ? w 2 icdrt2 ? w 1 icdrt1 ? w bit : initial value : r/w : tdre, rdrf (internal flag) ? rdrf 0 ? ? tdre 0 ? bit : initial value : r/w : icdr is an 8-bit readable/writable register th at is used as a transmit data register when transmitting and a receive data register when recei ving. icdr is divided internally into a shift register (icdrs), receive buffer (icdrr), and tran smit buffer (icdrt). icdrs cannot be read or written by the cpu, icdrr is read-only, and icdrt is write-only. data transfers among the section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 456 of 1174 rej09b0329-0200 three registers are performed automatically in co ordination with changes in the bus state, and affect the status of internal flags such as tdre and rdrf. after transmission/reception of one frame of data using icdrs, if the i 2 c bus is in transmit mode and the next data is in icdrt (the tdre flag is 0), data is transferred automatically from icdrt to icdrs. after transmission/reception of one frame of data using icdrs, if the i 2 c bus is in receive mode and no previous data remains in icd rr (the rdrf flag is 0), data is transferred automatically from icdrs to icdrr. if the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. transmit data should be written justified toward the msb side when mls = 0, and toward the lsb side when ml s = 1. receive data bits read from the lsb side should be treated as valid when mls = 0, and bits read from the msb side when mls = 1. icdr is assigned to the same address as sarx, and can be written and read only when the ice bit is set to 1 in iccr. the value of icdr is undefined after a reset. the tdre and rdrf flags are set and cleared under the conditions shown below. setting the tdre and rdrf flags affects the status of the interrupt flags. tdre description 0 the next transmit data is in icdr (icdrt), or transmission cannot be started [clearing conditions] (initial value) 1. when transmit data is written in icdr (icdrt) in transmit mode (trs = 1) 2. when a stop condition is detected in the bus line state after a stop condition is issued with the i 2 c bus format or serial format selected 3. when a stop condition is detected with the i 2 c bus format selected 4. in receive mode (trs = 0) (a 0 write to trs during transfer is valid after reception of a frame containing an acknowledge bit) 1 the next transmit data can be written in icdr (icdrt) [setting conditions] 1. in transmit mode (trs = 1), when a start condition is detected in the bus line state after a start condition is issued in master mode with the i 2 c bus format or serial format selected 2. in transmit mode (trs = 1) when formatless transfer is selected 3. when data is transferred from icdrt to icdrs (data transfer from icdrt to icdrs when trs = 1 and tdre = 0, and icdrs is empty) 4. when a switch is made from receive mode (trs = 0) to transmit mode (trs = 1) after detection of a start condition section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 457 of 1174 rej09b0329-0200 rdrf description 0 the data in icdr (icdrr) is invalid (initial value) [clearing condition] when icdr (icdrr) receive data is read in receive mode 1 the icdr (icdrr) receiv e data can be read [setting condition] when data is transferred from icdrs to icdrr (data transfer from icdrs to icdrr in case of normal termination with trs = 0 and rdrf = 0) 23.2.2 slave address register (sar) 7 sva6 0 r/w 6 sva5 0 r/w 5 sva4 0 r/w 4 sva3 0 r/w 3 sva2 0 r/w 0 fs 0 r/w 2 sva1 0 r/w 1 sva0 0 r/w bit : initial value : r/w : sar is an 8-bit readable/writable register th at stores the slave address and selects the communication format. when the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of sar match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave de vice specified by the master device. sar is assigned to the same address as icmr, and can be written and read onl y when the ice bit is cleared to 0 in iccr. sar is initialized to h'00 by a reset. bits 7 to 1 ? slave address (sva6 to sva0): set a unique address in bits sva6 to sva0, differing from the addresses of other slave devices connected to the i 2 c bus. bit 0 ? format select (fs): used together with the fsx bit in sarx and the sw bit in ddcswr to select the communication format. ? i 2 c bus format: addressing format with acknowledge bit ? synchronous serial format: non-addressing format without acknowledge bit, for master mode only ? formatless transfer (only for channel 0): non-addressing with or without an acknowledge bit and without detec tion of start or stop condition, for slave mode only. the fs bit also specifies whether or not sar slave address recognition is performed in slave mode. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 458 of 1174 rej09b0329-0200 ddcswr bit 6 sar bit 0 sarx bit 0 sw fs fsx operating mode 0 i 2 c bus format ? sar and sarx slave addresses recognized 0 1 i 2 c bus format (initial value) ? sar slave address recognized ? sarx slave address ignored 0 i 2 c bus format ? sar slave address ignored ? sarx slave address recognized 0 1 1 synchronous serial format ? sar and sarx slave addresses ignored 0 0 1 formatless transfer (start and stop conditions are not detected) ? with acknowledge bit 0 1 1 1 formatless transfer * (start and stop conditions are not detected) ? without acknowledge bit note: * do not use this setting when automatically switching the mode from formatless transfer to i 2 c bus format by setting ddcswr. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 459 of 1174 rej09b0329-0200 23.2.3 second slave address register (sarx) 7 svax6 0 r/w 6 svax5 0 r/w 5 svax4 0 r/w 4 svax3 0 r/w 3 svax2 0 r/w 0 fsx 1 r/w 2 svax1 0 r/w 1 svax0 0 r/w bit : initial value : r/w : sarx is an 8-bit readable/writable register that stores the second slave address and selects the communication format. when the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of sarx match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave de vice specified by the master device. sarx is assigned to the same address as icdr, and can be written and read only when the ice bit is cleared to 0 in iccr. sarx is initialized to h'01 by a reset and in hardware standby mode. bits 7 to 1 ? second slave address (svax6 to svax0): set a unique address in bits svax6 to svax0, differing from the addresses of ot her slave devices connected to the i 2 c bus. bit 0 ? format select x (fsx): used together with the fx bit in sar and the sw bit in ddcswr to select the communication format. ? i 2 c bus format: addressing format with acknowledge bit ? synchronous serial format: non-addressing format without acknowledge bit, for master mode only ? formatless transfer: non-addressing with or without an acknowledge bit and without detection of start or stop condition, for slave mode only. the fsx bit also specifies whether or not sarx slave address recognition is performed in slave mode. for details, see the description of the fs bit in section 23.2.2, slave address register (sar). section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 460 of 1174 rej09b0329-0200 23.2.4 i 2 c bus mode register (icmr) 7 mls 0 r/w 6 wait 0 r/w 5 cks2 0 r/w 4 cks1 0 r/w 3 cks0 0 r/w 0 bc0 0 r/w 2 bc2 0 r/w 1 bc1 0 r/w bit : initial value : r/w : icmr is an 8-bit readable/writable register that selects whether the msb or lsb is transferred first, performs master mode wait control, and sel ects the master mode transfer clock frequency and the transfer bit count. icmr is assigned to the same address as sar. icmr can be written and read only when the ice bit is set to 1 in iccr. icmr is initialized to h'00 by a reset. bit 7 ? msb-first/lsb-first select (mls): selects whether data is transferred msb-first or lsb-first. if the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. transmit data should be written justified toward the msb side when mls = 0, and toward the lsb side when ml s = 1. receive data bits read from the lsb side should be treated as valid when mls = 0, and bits read from the msb side when mls = 1. do not set this bit to 1 when the i 2 c bus format is used. bit 7 mls description 0 msb-first (initial value) 1 lsb-first section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 461 of 1174 rej09b0329-0200 bit 6 ? wait insertion bit (wait): selects whether to insert a wait between the transfer of data and the acknowledge bit, in master mode with the i 2 c bus format. when wait is set to 1, after the fall of the clock for the final data bit, the iric flag is set to 1 in iccr, and a wait state begins (with scl at the low level). when the iric flag is cleared to 0 in iccr, the wait ends and the acknowledge bit is transferred. if wait is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. the iric flag in iccr is set to 1 on completion of the acknowledge bit transfer, regardless of the wait setting. the setting of this bit is invalid in slave mode. bit 6 wait description 0 data and acknowledge bits transferred consecutively (initial value) 1 wait inserted between data and acknowledge bits section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 462 of 1174 rej09b0329-0200 bits 5 to 3 ? transfer clock select (cks2 to cks0): these bits, together with the iicx1 bit (for channel 1) or iicx0 bit (for channel 0) in st cr, select the serial clock frequency in master mode. they should be set according to the required transfer rate. stcr bits 5, 6 bit 5 bit 4 bit 3 transfer rate iicx cks2 cks1 cks0 clock = 8 mhz = 10 mhz 0 /28 286 khz 357 khz 0 1 /40 200 khz 250 khz 0 /48 167 khz 208 khz 0 1 1 /64 125 khz 156 khz 0 /80 100 khz 125 khz 0 1 /100 80.0 khz 100 khz 0 /112 71.4 khz 89.3 khz 0 1 1 1 /128 62.5 khz 78.1 khz 0 /56 143 khz 179 khz 0 1 /80 100 khz 125 khz 0 /96 83.3 khz 104 khz 0 1 1 /128 62.5 khz 78.1 khz 0 /160 50.0 khz 62.5 khz 0 1 /200 40.0 khz 50.0 khz 0 /224 35.7 khz 44.6 khz 1 1 1 1 /256 31.3 khz 39.1 khz section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 463 of 1174 rej09b0329-0200 bits 2 to 0 ? bit counter (bc2 to bc0): bits bc2 to bc0 specify the number of bits to be transferred next. with the i 2 c bus format (when the fs bit in sar or the fsx bit in sarx is 0), the data is transferred with one addition acknowledge bit. bit bc2 to bc0 settings should be made during an interval between transfer frames. if bits bc2 to bc0 are set to a value other than 000, the setting should be made while the scl line is low. the bit counter is initiali zed to 000 by a reset and when a st art condition is de tected. the value returns to 000 at the end of a data transfer, including the acknowledge bit. bit 2 bit 1 bit 0 bits/frame bc2 bc1 bc0 synchronous serial format i 2 c bus format 0 8 9 (initial value) 0 1 1 2 0 2 3 0 1 1 3 4 1 0 4 5 0 1 5 6 1 0 6 7 1 7 8 section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 464 of 1174 rej09b0329-0200 23.2.5 i 2 c bus control register (iccr) 7 ice 0 r/w 6 ieic 0 r/w 5 mst 0 r/w 4 trs 0 r/w 3 acke 0 r/w 0 scp 1 w 2 bbsy 0 r/w 1 iric 0 r/(w) * note: * only 0 can be written to clear the flag. bit : initial value : r/w : iccr is an 8-bit readable/writable regi ster that enables or disables the i 2 c bus interface, enables or disables interrupts, selects master or slave mode and transmission or reception, enables or disables acknowledgement, confirms the i 2 c bus interface bus status, issues start/stop conditions, and performs interrupt flag confirmation. iccr is initialized to h'01 by a reset. bit 7 ? i 2 c bus interface enable (ice): selects whether or not the i 2 c bus interface is to be used. when ice is set to 1, port pins function as scl and sda input/output pins and transfer operations are enabled. when ice is cleared to 0, the iic stops and its internal status is initialized. the sar and sarx registers can be accessed when ice is 0. the icmr and icdr registers can be accessed when ice is 1. bit 7 ice description 0 i 2 c bus interface module disabled, with scl and sda signal pins set to port function the internal status of the iic is initialized sar and sarx can be accessed (initial value) 1 i 2 c bus interface module enabled for transfer operations (pins scl and sda are driving the bus) icmr and icdr can be accessed bit 6 ? i 2 c bus interface interrupt enable (ieic): enables or disables interrupts from the i 2 c bus interface to the cpu. bit 6 ieic description 0 interrupts disabled (initial value) 1 interrupts enabled section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 465 of 1174 rej09b0329-0200 bits 5 and 4 ? master/slave select (mst) and tr ansmit/receive select (trs): mst selects whether the i 2 c bus interface operates in master mode or slave mode. trs selects whether the i 2 c bus interface operates in transmit mode or receive mode. in master mode with the i 2 c bus format, when arbitration is lost, mst and trs are both reset by hardware, causing a transition to slave receive mo de. in slave receive mode with the addressing format (fs = 0 or fsx = 0), hard ware automatically selects transm it or receive mode according to the r/w bit in the first frame after a start condition. modification of the trs bit during transfer is deferred until transfer of the frame containing the acknowledge bit is completed, and the changeover is made after completion of the transfer. mst and trs select the operating mode as follows. bit 5 bit 4 mst trs description 0 slave receive mode (initial value) 0 1 slave transmit mode 1 0 master receive mode 1 master transmit mode bit 5 mst description 0 slave mode (initial value) [clearing conditions] 1. when 0 is written by software 2. when bus arbitration is lost after transmission is started in i 2 c bus format master mode 1 master mode [setting conditions] 1. when 1 is written by software (in cases other than clearing condition 2) 2. when 1 is written in mst after reading mst = 0 (in case of clearing condition 2) section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 466 of 1174 rej09b0329-0200 bit 4 trs description 0 receive mode (initial value) [clearing conditions] 1. when 0 is written by software (in cases other than setting condition 3) 2. when 0 is written in trs after reading trs = 1 (in case of setting condition 3) 3. when bus arbitration is lost after transmission is started in i 2 c bus format master mode 4. when the sw bit in ddcswr changes from 1 to 0 1 transmit mode [setting conditions] 1. when 1 is written by software (in cases other than clearing conditions 3) 2. when 1 is written in trs after reading trs = 0 (in case of clearing conditions 3) 3. when a 1 is received as the r/w bit of the first frame in i 2 c bus format slave mode bit 3 ? acknowledge bit judgement selection (acke): specifies whether the value of the acknowledge bit returned from the receiving device when using the i 2 c bus format is to be ignored and continuous transfer is performed, or transf er is to be aborted and error handling, etc., performed if the acknowledge b it is 1. when the acke bit is 0, the value of the received acknowledge bit is not indicated by the ackb bit, which is always 0. when the acke bit is 0, the tdre, iric, and irtr flags are set on completion of data transmission, regardless of the value of the acknowledge bit. when the acke bit is 1, the tdre, iric, and irtr flags are set on completion of data transmission when the acknowledge bit is 0, and the iric flag alone is set on completion of da ta transmission when the acknowledge bit is 1. depending on the receiving device, the acknowledge bit ma y be significant, in indicating completion of processing of the received data, for instance, or may be fixed at 1 and have no significance. bit 3 acke description 0 the value of the acknowledge bit is ignored, and continuous transfer is performed (initial value) 1 if the acknowledge bit is 1, continuous transfer is interrupted section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 467 of 1174 rej09b0329-0200 bit 2 ? bus busy (bbsy): the bbsy flag can be read to check whether the i 2 c bus (scl, sda) is busy or free. in master mode, this bit is also used to issue start and stop conditions. a high-to-low transition of sda while scl is high is recognized as a start condition, setting bbsy to 1. a low-to-high trans ition of sda while scl is high is recognized as a stop condition, clearing bbsy to 0. to issue a start condition, use a mov instruction to write 1 in bbsy and 0 in scp. a retransmit start condition is issued in the same way. to issue a stop condition, use a mov instruction to write 0 in bbsy and 0 in scp. it is not possible to write to bbsy in slave mode; the i 2 c bus interface must be set to master transmit mode before issuing a start condition. mst and trs should both be set to 1 before writing 1 in bbsy and 0 in scp. bit 2 bbsy description 0 bus is free (initial value) [clearing condition] when a stop condition is detected 1 bus is busy [setting condition] when a start condition is detected bit 1 ? i 2 c bus interface interrupt request flag (iric): indicates that the i 2 c bus interface has issued an interrupt request to the cpu. iric is set to 1 at the end of a data transfer, when a slave address or general call address is detected in slav e receive mode, when bus arbitration is lost in master transmit mode, and when a stop condition is detected. iric is set at different times depending on the fs bit in sar and the wait bit in icmr. see section 23.3.6, iric setting timing and scl control. the conditions under which iric is set also differ depending on the setting of the acke bit in iccr. iric is cleared by reading iric after it has been set to 1, then writing 0 in iric. when the dtc is used, iric is cleared automatically and transfer can be performed continuously without cpu intervention. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 468 of 1174 rej09b0329-0200 bit 1 iric description 0 waiting for transfer, or transfer in progress (initial value) [clearing condition] when 0 is written in iric after reading iric = 1 (1) interrupt requested [setting conditions] ? i 2 c bus format master mode 1. when a start condition is detected in the bus line state after a start condition is issued (when the tdre flag is set to 1 because of first frame transmission) 2. when a wait is inserted between the data and acknowledge bit when wait = 1 3. at the end of data transfer (at the rise of the 9th transmit/receive clock pulse, or at the fall of the 8th transmit/receive clock pulse when using wait insertion) 4. when a slave address is received after bus arbitration is lost (when the al flag is set to 1) 5. when 1 is received as the acknowledge bit when the acke bit is 1 (when the ackb bit is set to 1) ? i 2 c bus format slave mode 1. when the slave address (sva, svax) matches (when the aas and aasx flags are set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the tdre or rdrf flag is set to 1) 2. when the general call address is detected (when fs = 0 and the adz flag is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the tdre or rdrf flag is set to 1) 3. when 1 is received as the acknowledge bit when the acke bit is 1 (when the ackb bit is set to 1) 4. when a stop condition is detected (when the stop or estp flag is set to 1) ? synchronous serial format 1. at the end of data transfer (when the tdre or rdrf flag is set to 1) 2. when a start condition is detected with serial format selected ? when a condition, other than the above, that sets the tdre or rdrf flag to 1 is detected section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 469 of 1174 rej09b0329-0200 when, with the i 2 c bus format selected, iric is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set iric to 1. although each source has a corresponding flag, caution is need ed at the end of a transfer. when the tdre or rdrf internal flag is set, th e readable irtr flag may or may not be set. the irtr flag (the dtc start request flag) is not set at the end of a data transfer up to detection of a retransmission start condition or stop condition afte r a slave address (sva) or general call address match in i 2 c bus format slave mode. even when the iric flag and irtr flag are set, the tdre or rdrf internal flag may not be set. the iric and irtr flags are not cleared at th e end of the specified number of transfers in continuous transfer using the dtc. the tdre or rdrf flag is cleared, however, since the specified number of icdr reads or writes have been completed. table 23.3 shows the relationship between the flags and the transfer states. note: * this lsi does not incorporate dtc. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 470 of 1174 rej09b0329-0200 table 23.3 flags and transfer states mst trs bbsy estp stop irtr aasx al aas adz ackb state 1/0 1/0 0 0 0 0 0 0 0 0 0 idle state (flag clearing required) 1 1 0 0 0 0 0 0 0 0 0 start condition issuance 1 1 1 0 0 1 0 0 0 0 0 start condition established 1 1/0 1 0 0 0 0 0 0 0 0/1 master mode wait 1 1/0 1 0 0 1 0 0 0 0 0/1 master mode transmit/receive end 0 0 1 0 0 0 1/0 1 1/0 1/0 0 arbitration lost 0 0 1 0 0 0 0 0 1 0 0 sar match by first frame in slave mode 0 0 1 0 0 0 0 0 1 1 0 general call address match 0 0 1 0 0 0 1 0 0 0 0 sarx match 0 1/0 1 0 0 0 0 0 0 0 0/1 slave mode transmit/receive end (except after sarx match) 0 0 1/0 1 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 slave mode transmit/receive end (after sarx match) 0 1/0 0 1/0 1/0 0 0 0 0 0 0/1 stop condition detected bit 0 ? start condition/stop condition prohibit (scp): controls the issuing of start and stop conditions in master mode. to issue a start condition, write 1 in bbsy and 0 in scp. a retransmit start condition is issued in the same way. to issue a stop condition, write 0 in bbsy and 0 in scp. this bit is always read as 1. if 1 is written, the data is not stored. bit 0 scp description 0 writing 0 issues a start or stop condition, in combination with the bbsy flag 1 reading always returns a value of 1 (initial value) writing is ignored section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 471 of 1174 rej09b0329-0200 23.2.6 i 2 c bus status register (icsr) 7 estp 0 r/(w) * 6 stop 0 r/(w) * 5 irtr 0 r/(w) * 4 aasx 0 r/(w) * 3 al 0 r/(w) * 0 ackb 0 r/w 2 aas 0 r/(w) * 1 adz 0 r/(w) * note: * only 0 can be written to clear the flag. bit : initial value : r/w : icsr is an 8-bit readable/writable register that performs flag confirmation and acknowledge confirmation and control. icsr is initialized to h'00 by a reset. bit 7 ? error stop condition detection flag (estp): indicates that a stop condition has been detected during frame transfer in i 2 c bus format slave mode. bit 7 estp description 0 no error stop condition (initial value) [clearing conditions] 1. when 0 is written in estp after reading estp = 1 2. when the iric flag is cleared to 0 1 ? in i 2 c bus format slave mode: error stop condition detected [setting condition] when a stop condition is detected during frame transfer ? in other modes: no meaning section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 472 of 1174 rej09b0329-0200 bit 6 ? normal stop condition detection flag (stop): indicates that a stop condition has been detected after completion of frame transfer in i 2 c bus format slave mode. bit 6 stop description 0 no normal stop condition (initial value) [clearing conditions] 1. when 0 is written in stop after reading stop = 1 2. when the iric flag is cleared to 0 1 ? in i 2 c bus format slave mode: error stop condition detected [setting condition] when a stop condition is detected after completion of frame transfer ? in other modes:no meaning bit 5 ? i 2 c bus interface continuous transmission/reception interrupt request flag (irtr): indicates that the i 2 c bus interface has issued an interr upt request to the cpu, and the source is completion of reception/transmission of one frame in continuous transmission/reception for which dtc activation is possible. when the irtr flag is set to 1, the iric flag is also set to 1 at the same time. irtr flag setting is performed when the tdre or rdrf flag is set to 1. irtr is cleared by reading irtr after it has been set to 1, then writing 0 in irtr. irtr is also cleared automatically when the iric flag is cleared to 0. note: * this lsi does not incorporate dtc. bit 5 irtr description 0 waiting for transfer, or transfer in progress (initial value) [clearing conditions] 1. when 0 is written in irtr after reading irtr = 1 2. when the iric flag is cleared to 0 1 continuous transfer state [setting conditions] ? in i 2 c bus interface slave mode: when the tdre or rdrf flag is set to 1 when aasx = 1 ? in other modes: when the tdre or rdrf flag is set to 1 section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 473 of 1174 rej09b0329-0200 bit 4 ? second slave address recognition flag (aasx): in i 2 c bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits svax6 to svax0 in sarx. aasx is cleared by reading aasx af ter it has been set to 1, then writing 0 in aasx. aasx is also cleared automatically when a start condition is detected. bit 4 aasx description 0 second slave address not recognized (initial value) [clearing conditions] 1. when 0 is written in aasx after reading aasx = 1 2. when a start condition is detected 3. in master mode 1 second slave address recognized [setting condition] when the second slave address is detected in slave receive mode while fsx=0 bit 3 ? arbitration lost (al): this flag indicates that arbitra tion was lost in master mode. the i 2 c bus interface monitors the bus. when two or more master devices attempt to seize the bus at nearly the same time, if the i 2 c bus interface detects data differing from the data it sent, it sets al to 1 to indicate that the bus has been taken by another master. al is cleared by reading al after it has been set to 1, then writing 0 in al. in addition, al is reset automatically by write access to icdr in transmit mode, or read access to icdr in receive mode. bit 3 al description 0 bus arbitration won (initial value) [clearing conditions] 1. when icdr data is written (transmit mode) or read (receive mode) 2. when 0 is written in al after reading al = 1 1 arbitration lost [setting conditions] 1. if the internal sda and sda pin disagree at the rise of scl in master transmit mode 2. if the internal scl line is high at the fall of scl in master transmit mode section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 474 of 1174 rej09b0329-0200 bit 2 ? slave address recognition flag (aas): in i 2 c bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits sva6 to sva0 in sar, or if the general call address (h'00) is detected. aas is cleared by reading aas after it has been set to 1, then writing 0 in aas. in addition, aas is reset automatically by write acce ss to icdr in transmit mode, or read access to icdr in receive mode. bit 2 aas description 0 slave address or general call address not recognized (initial value) [clearing conditions] 1. when icdr data is written (transmit mode) or read (receive mode) 2. when 0 is written in aas after reading aas = 1 3. in master mode 1 slave address or general call address recognized [setting condition] when the slave address or general call addr ess is detected when fs = 0 in slave receive mode bit 1 ? general call address recognition flag (adz): in i 2 c bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (h'00). adz is cleared by reading adz after it has been set to 1, then writing 0 in adz. in addition, adz is reset automatically by write acce ss to icdr in transmit mode, or read access to icdr in receive mode. bit 1 adz description 0 general call address not recognized (initial value) [clearing conditions] 1. when icdr data is written (transmit mode) or read (receive mode) 2. when 0 is written in adz after reading adz = 1 3. in master mode 1 general call address recognized [setting condition] if the general call address is detected when fsx = 0 or fs = 0 is selected in the slave receive mode. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 475 of 1174 rej09b0329-0200 bit 0 ? acknowledge bit (ackb): stores acknowledge data. in transmit mode, after the receiving device receives data, it retu rns acknowledge data, and this da ta is loaded into ackb. in receive mode, after data has been received, the ack nowledge data set in this bit is sent to the transmitting device. when this bit is read, in transmission (when trs = 1), the value loaded from the bus line (returned by the receiving device) is read. in reception (when trs = 0), the value set by internal software is read. bit 0 ackb description 0 receive mode: 0 is output at acknowledge output timing (initial value) transmit mode: indicates that the receiving device has acknowledged the data (signal is 0) 1 receive mode: 1 is output at acknowledge output timing transmit mode: indicates that the receiving device has not acknowledged the data (signal is 1) 23.2.7 serial/timer control register (stcr) 7 ? 0 ? 6 iicx1 0 r/w 5 iicx0 0 r/w 4 ? 0 ? 3 flshe 0 r/w 0 ? 0 ? 2 osrome 0 r/w 1 ? 0 ? bit : initial value : r/w : stcr is an 8-bit readable/writable register that controls the iic operating mode. stcr is initialized to h'00 by a reset. bit 7 ? reserved: this bit cannot be modified and is always read as 0. bits 6 and 5 ? i 2 c transfer select 1, 0 (iicx1, iicx0): these bits, together with bits cks2 to cks0 in icmr of iic, select the transfer rate in master mode. for details, see section 23.2.4, i 2 c bus mode register (icmr). bit 3 ? flash memory control resister enable (flshe): this bit selects the control resister of the flash memory. for details, refer to section 7.3.5, serial/timer control resister (stcr). bit 2 ? osd rom enable (osrome): this bit controls the osd rom. for details, refer to section 7, rom. bits 4, 1, and 0 ? reserved: these bits cannot be modified and are always read as 0. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 476 of 1174 rej09b0329-0200 23.2.8 ddc switch register (ddcswr) 7 swe * 3 0 r/w 6 sw * 3 0 r/w 5 ie * 3 0 r/w 4 if * 3 0 r/(w) * 1 3 clr3 1 w * 2 0 clr0 1 w * 2 2 clr2 1 w * 2 1 clr1 1 w * 2 notes: 1. 2. 3. only 0 can be written to clear the flag. always read as 1. these bits are not provided (incorporated in) for the h8s/2197s and h8s/2196s. bit : initial value : r/w : ddcswr is an 8-bit read/write register that controls automatic format switching for iic channel 0 and iic internal latch clearing. ddcswr is initia lized to h'0f by a reset or in hardware standby mode. bit 7 ? ddc mode switch enable (swe): enables or disables automatic switching from formatless transfer to i 2 c bus format transfer for iic channel 0. bit 7 swe description 0 disables automatic switching from formatless transfer to i 2 c bus format transfer for iic channel 0. (initial value) 1 enables automatic switching from formatless transfer to i 2 c bus format transfer for iic channel 0. bit 6 ? ddc mode switch (sw): selects formatless transfer or i 2 c bus format transfer for iic channel 0. bit 6 sw description 0 i 2 c bus format is selected for iic channel 0. (initial value) [clearing conditions] 1. when 0 is written by software 2. when an scl falling edge is detected when swe = 1 1 formatless transfer is selected for iic channel 0. [setting condition] when 1 is written after sw = 0 is read section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 477 of 1174 rej09b0329-0200 bit 5 ? ddc mode switch interrupt enable bit (ie): enables or disables an interrupt request to the cpu when the format for iic channel 0 is automatically switched. bit 5 ie description 0 disables an interrupt at automatic format switching (initial value) 1 enables an interrupt at automatic format switching bit 4 ? ddc mode switch interrupt flag (if): indicates the interrupt request to the cpu when the format for iic channel 0 is automatically switched. bit 4 if description 0 interrupt has not been requested (initial value) [clearing condition] when 0 is written after if = 1 is read 1 interrupt has been requested [setting condition] when an scl falling edge is detected when swe = 1 bits 3 to 0 ? iic clear 3 to 0 (clr3 to clr0): control the iic0 and iic1 initialization. these are write-only bits and are always read as 1. writing to these bits generates a clearing signal for the internal latch circuit which initializes the iic status. the data written to these bits are not held. when initializing the iic, be sure to use the mov instruction to write to all the clr3 to clr0 bits at the same time; do not use bit manipulation instructions such as bclr. when reinitializing the module status, the clr3 to clr0 bits must be rewritten. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 478 of 1174 rej09b0329-0200 bit 3 bit 2 bit 1 bit 0 clr3 clr2 clr1 clr0 description 0 ? ? the setting is invalid 0 the setting is invalid 0 1 iic0 internal latch cleared 0 iic1 internal latch cleared 0 1 1 1 iic0 and iic1 internal latches cleared 1 ? ? ? this setting is invalid 23.2.9 module stop control register (mstpcr) 7 1 mstp15 r/w mstpcrh 6 1 mstp14 r/w 5 1 mstp13 r/w 4 1 mstp12 r/w 3 1 mstp11 r/w 2 1 mstp10 r/w 1 1 mstp9 r/w 0 1 mstp8 r/w 7 1 mstp7 r/w 6 1 mstp6 r/w 5 1 mstp5 r/w 4 1 mstp4 r/w 3 1 mstp3 r/w 2 1 mstp2 r/w 1 1 mstp1 r/w 0 1 mstp0 r/w mstpcrl bit : initial value : r/w : mstpcr comprises two 8-bit readable/writable registers, and is used to perform module stop mode control. when the corresponding bit in mstpcr is set to 1, operation of the corresponding iic channel is halted at the end of the bus cycle, and a transition is made to module stop mode. for details, see section 4.5, module stop mode. mstpcr is initialized to h'ffff by a reset. it is not initialized in standby mode. mstpcrl bit 7 ? module stop (mstp7): specifies the module stop mode for iic channel 0. mstpcrl bit 7 mstp7 description 0 module stop mode for iic channel 0 is cleared 1 module stop mode for iic channel 0 is set (initial value) section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 479 of 1174 rej09b0329-0200 mstpcrl bit 6 ? module stop (mstp6): specifies the module stop mode for iic channel 1. mstpcrl bit 6 mstp6 description 0 module stop mode for iic channel 1 is cleared 1 module stop mode for iic channel 1 is set (initial value) 23.3 operation 23.3.1 i 2 c bus data format the i 2 c bus interface has serial and i 2 c bus formats. the i 2 c bus formats are addressing formats with an acknowledge bit. these are shown in figures 23.3(1) and (2). the first frame following a start condition always consists of 8 bits. formatless transfer can be selected only for iic channel 0. the formatless transfer data is shown in figure 23.3 (3). the serial format is a non-addressing format with no acknowledge bit. this is shown in figure 23.4. figure 23.5 shows the i 2 c bus timing. the symbols used in figures 23.3 to 23.5 are explained in table 23.4. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 480 of 1174 rej09b0329-0200 sa sla 7n r/w data a 1 1m 11 1 a/a 1 p 1 transfer bit count (n = 1 to 8) transfer frame count (m = 1 or above) s sla 7n1 7 r/w a data 11 1m1 1 a/a 1 s 1 sla r/w 1 1m2 a 1 data n2 a/a 1 p 1 upper: transfer bit count (n1 and n2 = 1 to 8) lower: transfer frame count (m1 and m2 = 1 or above) (1) fs = 0 or fsx = 0 a n data data a 1m 1 81 a/a 1 transfer bit count (n = 1 to 8) transfer frame count (m = 1 or above) (3) formatless (iic channel 0 only, fs = 0 or fsx = 0) (2) start condition transmission, fs = 0 or fsx = 0 figure 23.3 i 2 c bus data formats (i 2 c bus formats) s data 8n data 1 1m p 1 transfer bit count (n = 1 to 8) transfer frame count (m = 1 or above) fs = 1 and fsx = 1 figure 23.4 i 2 c bus data format (serial format) sda scl s sla r/ w a 9 8 1-7 9 8 1-7 9 8 1-7 data a data a/ a p figure 23.5 i 2 c bus timing section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 481 of 1174 rej09b0329-0200 table 23.4 i 2 c bus data format symbols symbol description s start condition. the master device drives sda from high to low while scl is hig sla slave address, by which the master device selects a slave device r/ w indicates the direction of data transfer: from the slave device to the master device when r/ w is 1, or from the master device to the slave device when r/ w is 0 a acknowledge. the receiving device (the slave in master transmit mode, or the master in master receive mode) drives sda low to acknowledge a transfer data transferred data. the bit length is set by bits bc2 to bc0 in icmr. the msb-first or lsb-first format is selected by bit mls in icmr p stop condition. the master device drives sda from low to high while scl is high 23.3.2 master transmit operation in i 2 c bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowl edge signal. the transmission procedure and operations synchronize with the icdr writing are described below. [1] set bit ice in iccr to 1. set bits mls, wait, and cks2 to cks0 in icmr, and bit iicx in stcr, according to the operating mode. [2] read the bbsy flag in iccr to confirm that the bus is free. [3] set bits mst and trs to 1 in iccr to select master transmit mode. [4] write 1 to bbsy and 0 to scp. this changes sda from high to low when scl is high, and generates the start condition. [5] then iric and irtr flags are set to 1. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. [6] write the data (slave address + r/ w ) to icdr. after the start condition instruction has been issued and the start condition has been generated, write data to icdr. if this procedure is not followed, data may not be output correctly. with the i 2 c bus format (when the fs bit in sar or the fsx bit in sarx is 0), the first frame data following the start condition indicates the 7- bit slave address and transmit/recei ve direction. as indicating the end of the transfer, and so the iric flag is cleared to 0. after writing ic dr, clear iric immediatel y not to execute other interrupt handling routine. if one frame of data has been transmitted before the iric clearing, it can not be determine the end of transmission. the master device sequentially sends the transmission clock and the data written to icdr using the timing shown in figure 23.6. the selected slave device (i.e. the slave device with the matching slave address) drives sda low at the 9th transmit clock pulse and returns an acknowledge signal. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 482 of 1174 rej09b0329-0200 [7] when one frame of data has been transmitted, the iric flag is set to 1 at the rise of the 9th transmit clock pulse. after one frame has been transmitted scl is automatically fixed low in synchronization with the internal clock until the next transmit data is written. [8] read the ackb bit in icsr to confirm that ackb is cleared to 0. when the slave device has not acknowledged (ackb bit is 1), operate the step [12] to end transmission, and retry the transmit operation. [9] write the transmit data to icdr. as indicating the end of the transfer, and so the iric flag is cleared to 0. after writing icdr, clear iric immediately not to execute other interrupt handling routine. the master device sequentially sends the transmission clock and the data written to icdr. transmission of the next frame is performed in synchronization with the internal clock. [10] when one frame of data has been transmitted, the iric flag is set to 1 at the rise of the 9th transmit clock pulse. after one frame has been transmitted scl is automatically fixed low in synchronization with the internal clock until the next transmit data is written. [11] read the ackb bit in icsr and confirm ackb is cleared to 0. when there is data to be transmitted, go to the step [9] to continue next transmission. when the slave device has not acknowledged (ackb bit is set to 1), operate the step [12] to end transmission. [12] clear the iric flag to 0. and write 0 to bbsy and scp in iccr. this changes sda from low to high when scl is high, and generates the stop condition. sda (master output) sda (slave output) 2 1 r/ w 4 36 58 7 12 9 a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 iric irtr icdr scl (master output) start condition geberation slave address data 1 [9] icdr write [9] iric clear [6] icdr write [6] iric clear address + r/ w [7] [5] note: data write timing in icdr icdr writing prohibited [4] write bbsy = 1 and scp = 0 (start condition issuance) icdr writing enable data 1 user processing these processes are executed continuously. these processes are executed continuously. figure 23.6 example of master transmit mode operation timing (mls = wait = 0) section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 483 of 1174 rej09b0329-0200 23.3.3 master receive operation in master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. the slave device transmits data. i 2 c bus interface module consists of the data buffers of icdrr and icdrs, so data can be r eceived continuously in master receive mode. for this construction, when stop condition issuing timing delayed, it may occurs the internal contention between stop condition i ssuance and scl clock output for next data receiving, and then the extra scl clock would be outputted automatically or the sda line would be held to low. and for i 2 c bus interface system, the acknowledge bit must be set to 1 at the last data receiving, so the change timing of ackb bit in icsr should be controlled by software. to take measures against these problems, the wait function should be used in master receive mode. the reception procedure and operations with the wait function in ma ster receive mode are described below. [1] clear the trs bit in iccr to 0 to switch from transmit mode to receive mode, and set the wait bit in icmr to 1. also clear the ackb bit in icsr to 0 (acknowledge data setting). [2] when icdr is read (dummy da ta read), reception is started, and the receive clock is output, and data received, in synchronization with the in ternal clock. in order to detect wait operation, set the iric flag in iccr must be cleared to 0. after reading icdr, clear iric immediately not to execute other interrupt ha ndling routine. if one frame of data has been received before the iric clearing, it can not be determine the end of reception. [3] the iric flag is set to 1 at the fall of the 8th receive clock pu lse. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. scl is automatically fixed low in synchronization with the internal clock until the iric flag clearing. if the first frame is the last receive data, execute step [10] to halt reception. [4] clear the iric flag to releas e from the wait state. the master device outputs the 9th clock and drives sda at the 9th recei ve clock pulse to return an acknowledge signal. [5] when one frame of data has been received, the iric flag in iccr and the irtr flag in icsr are set to 1 at the rise of the 9th receive cl ock pulse. the master device outputs scl clock to receive next data. [6] read icdr. [7] clear the iric flag to detect next wait operation. from clearing of the iric flag to negation of a wait as described in step [4] (and [9]) to clearing of the iric flag as described in steps [5], [6], and [7], must be performed within the time taken to transfer one byte. [8] the iric flags set to 1 at th e fall of the 8th receive clock pulse . scl is automatically fixed low in synchronization with the internal clock until the iric flag clearing. if this frame is the last receive data, execute step [10] to halt reception. [9] clear the iric flag in iccr to cancel wait ope ration. the master device outputs the 9th clock and drives sda at the 9th receive clock pulse to return an acknowledge signal. data can be received continuously by repe ating step [5] to [9]. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 484 of 1174 rej09b0329-0200 [10] set the ackb bit in icsr to 1 so as to return ?no acknowledge? data. also set the trs bit to 1 to switch from receive mode to transmit mode. [11] clear iric flag to 0 to release from the wait state. [12] when one frame of data has been received, th e iric flag is set to 1 at the rise of the 9th receive clock pulse. [13] clear the wait bit to 0 to switch from wait mode to no wait mode. read icdr and the iric flag to 0. clearing of the iric flag should be after the wait = 0. [14] clear the bbsy bit and scp bit to 0. this changes sda from low to high when scl is high, and generates the stop condition. 9 a bit7 master receive mode master transmit mode scl (master output) sda (slave output) sda (master output) iric irtr icdr user processing [1] trs cleared to 0 wait set to 1 ackb cleared to 0 [2] icdr read (dummy read) [2] iric clearance [4] irc clearance [6] icdr read (data 1) [7] iric clearance bit6 bit5 bit4 bit3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 12 34 56 78 [3] [5] a 912 3 45 data 1 data 2 data 1 these processes are executed continuously. these processes are executed continuously. figure 23.7 example of master r eceive mode operation timing (mls = ackb = 0, wait = 1) section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 485 of 1174 rej09b0329-0200 8 bit0 data 2 scl (master output) sda (slave output) sda (master output) iric irtr icdr user processing [9] iric clearance [6] icdr read (data 2) [7] iric clearance [9] iric clearance [6] icdr read (data 3) [7] iric clearance bit7 [8] [5] a bit6 bit5 bit4 bit7 bit6 bit3 bit2 bit1 bit0 91 23 45 67 [8] [5] a 8912 data 3 data 4 data 3 data 2 data 1 these processes are executed continuously. these processes are executed continuously. figure 23.8 example of master r eceive mode operation timing (mls = ackb = 0, wait = 1) continued 23.3.4 slave recei ve operation in slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. the r eceive procedure and operations in slave receive mode are described below. 1. set bit ice in iccr to 1. set bits mls in icmr and bits mst and tr s in iccr according to the operating mode. 2. a start condition output by the master device sets the bbsy flag to 1 in iccr. 3. after the slave device detects the start condition, if the first frame matches its slave address, it functions as the slave device designated as the master device. if the 8th bit data (r/ w ) is 0, trs bit in iccr remains 0 and executes slave receive operation. 4. at the ninth clock pul se of the receive frame, the slave device drives sda low to acknowledge the transfer. at the same time, the iric flag is set to 1 in iccr. if ieic is 1 in iccr, a cpu interrupt is requested. if the rdrf internal flag is 0, it is set to 1 and continuous reception is performed. if the rdrf internal flag is 1, the slave device holds scl low from the fall of the receive clock until it has read the data in icdr. 5. read icdr and clear iric to 0 in iccr. at this time, the rdrf fl ag is cleared to 0. steps 4 and 5 can be repeated to receive data continuously. when a stop condition is detected (a low-to-high transition of sda while scl is hi gh), the bbsy flag is cleared to 0 in iccr. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 486 of 1174 rej09b0329-0200 sda (master output) sda (slave output) 2 1 2 1 4 36 58 79 bit 7 bit 6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iric icdrs icdrr rdrf scl (master output) start condition issurance scl (slave output) interrupt request generated address + r/w address + r/w [5] read icdr [5] clear iric user processing slave address data 1 [4] a r/w figure 23.9 example of timing in slave receive mode (mls = ackb = 0) section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 487 of 1174 rej09b0329-0200 sda (master output) sda (slave output) 2 14 36 58 79 8 79 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 1 bit 0 iric icdrs icdrr rdrf scl (master output) scl (slave output) interrupt request generated interrupt request generated data 2 data 2 data 1 data 1 [5] read icdr [5] clear iric user processing data 2 data 1 [4] [4] a a figure 23.10 example of timing in slave receive mode (mls = ackb = 0) section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 488 of 1174 rej09b0329-0200 23.3.5 slave transmit operation in slave transmit mode, the slave device outputs the transmit data, and the master device outputs the transmit clock and returns an acknowledge signal. the transmit procedure and operations in slave transmit mode are described below. 1. set bit ice in iccr to 1. set bits mls in icmr and bits mst and trs in iccr according to the operating mode. 2. after the slave device detects a start condition, if the first frame matches its slave address, at the ninth clock pulse the slave device drives sda low to acknowledge the transfer. at the same time, the iric flag is set to 1 in iccr, and if the ieic bit in iccr is set to 1 at this time, an interrupt request is sent to the cpu. if the eighth data bit (r/ w ) is 1, the trs bit is set to 1 in iccr, automatically causing a transition to slave transmit mode. the slave device holds scl low from the fall of the transmit clock until data is written in icdr. 3. clear the iric flag to 0, then write data in icdr. the written data is transferred to icdrs, and the tdre internal flag and the iric and irtr flags are set to 1 again. clear iric to 0, then write the next data in icdr. the slave device outputs the written data serially in step with the clock output by the master device, with the timing shown in figure 23.11. 4. when one frame of data has been transmitted, at the rise of the ninth transmit clock pulse iric is set to 1 in iccr. if the tdre internal flag is 1, the slave device holds scl low from the fall of the transmit clock until data is written in icdr. the master device drives sda low at the ninth clock pulse to acknowledge the data. the acknowledge signal is stored in the ackb bit in icsr, and can be used to check whether th e transfer was carried out normally. if tdre internal flag is set to 0, the data written in icdr is transferred to icdrs, then transmission starts and tdre internal flag and iric and irtr flags are all set to 1 again. 5. to continue transmitting, clear iric to 0, then write the next transmit data in icdr. at this time, the tdre internal flag is cleared to 0. steps 4 and 5 can be repeated to transmit continuously. to end the transmission, write h'ff in icdr so that the sda may be freed on the slave side. when a stop condition is detected (a low-to- high transition of sda while scl is high), th e bbsy flag will be cleared to 0 in iccr. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 489 of 1174 rej09b0329-0200 sda (slave output) sda (master output) scl (slave output) 2 1 2 1 4 36 58 79 9 8 bit 7 bit 6 bit 5 bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 bit 0 iric icdrs icdrt tdre scl (master output) interrupt request generated interrupt request generated interrupt request generated slave receive mode slave transmit mode data 1 data 2 [3] clear iric [5] clear iric [3] write icdr [3] write icdr [5] write icdr user processing data 1 data 1 data 2 data 2 a r/w a [3] [2] figure 23.11 example of timing in slave transmit mode (mls = 0) 23.3.6 iric setting timing and scl control the interrupt request flag (iric) is set at different times depending on the wait bit in icmr, the fs bit in sar, and the fsx bit in sarx. if the tdre or rdrf internal flag is set to 1, scl is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. figure 23.12 shows the iric set timing and scl control. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 490 of 1174 rej09b0329-0200 scl sda iric user processing clear iric write to icdr (transmit) or read icdr (receive) 1 a 8 7 1 9 8 7 scl sda iric user processing clear iric write to icdr (transmit) or read icdr (receive) 1 a 8 1 9 8 clear iric scl sda iric user processing clear iric write to icdr (transmit) or read icdr (receive) 1 8 7 1 8 7 (a) when wait = 0, and fs = 0 or fsx = 0 (i 2 c bus format, no wait) (b) when wait = 1, and fs = 0 or fsx = 0 (i 2 c bus format, wait inserted) (c) when fs = 1 and fsx = 1 (synchronous serial format) figure 23.12 iric setting timing and scl control section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 491 of 1174 rej09b0329-0200 23.3.7 automatic switching from formatless transfer to i 2 c bus format transfer setting the sw bit in ddcswr to 1 selects the iic0 formatless transfer operation. when an scl falling edge is detected, the operating mode automatically switches from formatless transfer to i 2 c bus format transfer (slave mode). for automatic switching to be possible, the following four conditions must be observed: 1. the same data pin (sda) is used in common for formatless transfer and i 2 c bus format transfer. 2. separate clock pins are used for formatless transfer and i 2 c bus format transfer (sync1 for formatless, and scl for i 2 c bus format) 3. the scl pin is kept high during formatless transfer. 4. register bits other than the trs bit in iccr are set to appropriate values so that i 2 c bus format transfer can be performed. the operating mode is automatically switched from formatless transfer to i 2 c bus format transfer when an scl falling edge is detected and the sw bit in ddcswr is automatically cleared to 0. to switch the mode from i 2 c bus format transfer to formatless transfer, set the sw bit to 1 by software. during formatless transfer, do not modify the bits that control the i 2 c bus interface operating mode, such as the msl or trs bit. when switching from the i 2 c bus format transfer to formatless transfer, specify the formatless tr ansfer direction (transmit or receive) by setting or clearing the trs bit, then set the sw bit to 1. after the automatic switching from formatless transfer to i 2 c bus format transfer (slave mode), the trs bit is auto matically cleared to 0 to enter the slave address receive wait state. if an scl falling edge is detected during formatless transfer, the i 2 c does not wait for the stop condition but switches the operating mode immediately. note: the iic0 is not provided (incorporated in) for the h8s/2197s and h8s/2196s. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 492 of 1174 rej09b0329-0200 23.3.8 noise canceler the logic levels at the scl and sda pins are routed through noise cancelers before being latched internally. figure 23.13 shows a block diagram of the noise canceler circuit. the noise canceler consists of two cascaded la tches and a match detector. the scl (or sda) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. if they do not agree, the previous value is held. scl or sda input signal internal scl or sda signal sampling clock sampling clock system clock period c latch q d c latch q d match detector figure 23.13 block diagram of noise canceler 23.3.9 sample flowcharts figures 23.14 to 23.17 show sample flowcharts for using the i 2 c bus interface in each mode. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 493 of 1174 rej09b0329-0200 start initialize read bbsy in iccr no bbsy = 0? yes set mst = 1 and trs = 1 in iccr write bbsy = 1 and scp = 0 in iccr clear iric in iccr read iric in iccr no yes iric = 1? write transmit data in icdr read ackb in icsr ackb = 0? no yes no yes transmit mode? write transmit data in icdr read iric in iccr iric = 1? no yes clear iric in iccr read ackb in icsr end of transmission or ackb = 1? no yes write bbsy = 0 and scp = 0 in iccr end master receive mode read iric in iccr no iric = 1? clear iric in iccr [1] initialize [2] test the status of the scl and sda lines. [3] select master transmit mode. [4] start condition issuance [5] wait for a start condition generation [6] set transmit data for the first byte (slave address + r/ w ). (after writing icdr, clear iric immediately) [7] wait for 1 byte to be transmitted. [8] test the acknowledge bit, transferred from slave device. [10] wait for 1 byte to be transmitted. [11] test for end of transfer [12] stop condition issuance [9] set transmit data for the second and subsequent bytes. (after writing icdr, clear iric immediately) figure 23.14 flowchart for master transmit mode (example) section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 494 of 1174 rej09b0329-0200 master receive mode read icdr clear iric in iccr iric = 1? clear iric in iccr read iric in iccr iric = 1? last receive ? yes yes no no no yes yes yes no yes read icdr read iric in iccr read iric in iccr iric = 1? last receive ? clear iric in iccr read iric in iccr clear iric in iccr set ackb = 1 in icsr set trs = 1 in iccr clear iric in iccr set wait = 0 in icmr read icdr write bbsy = 0 and scp = 0 in iccr end no iric = 1? no set trs = 0 in iccr set wait = 1 in icmr set ackb = 0 in icsr read iric in iccr [1] select receive mode [2] start receiving. the first read is a dummy read. after reading icdr, please clear iric immediately. [3] wait for 1 byte to be received. (8th clock falling edge) [4] clear iric to trigger the 9th clock. (to end the wait insertion) [5] wait for 1 byte to be received. (9th clock risig edge) [6] read the received data. [7] clear iric [8] wait for the next data to be received. (8th clock falling edge) [9] clear iric to trigger the 9th clock. (to end the wait insertion) [10] set ackb = 1 so as to return no acknowledge, or set trs = 1 so as not to issue extra clock. [12] wait for 1 byte to be received. [14] stop condition issuance. [13] set wait = 0. read icdr. clear iric. (note: after setting wait = 0, iric should be cleared to 0) [11] clear iric to trigger the 9th clock. (to end the wait insertion) figure 23.15 flowchart for master receive mode (example) section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 495 of 1174 rej09b0329-0200 start end initialize read iric flag in iccr read aas and adz flags in icsr read trs bit in iccr read iric flag in iccr clear iric flag in iccr clear iric flag in iccr clear iric flag in iccr read icdr read icdr read icdr set ackb = 0 in icsr general call address processing * description omitted set mst = 0 and trs = 0 in iccr iric = 1? no yes read iric flag in iccr set ackb = 0 in icsr iric = 1? no yes trs = 0? iric = 1? no no yes yes yes aas = 1 and adz = 0? [2] [1] [3] [8] [5] [6] [4] [7] slave transmit mode last receive? no no yes select slave receive mode. wait for 1 byte to be received (slave address) start receiving. the first read is a dummy read. wait for the transfer to end. set acknowledge data for the last receive. start the last receive. wait for the transfer to end. read the last receive data. [1] [2] [3] [4] [5] [6] [7] [8] figure 23.16 flowchart for slave transmit mode (example) section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 496 of 1174 rej09b0329-0200 end write transmit data in icdr clear iric flag in iccr clear iric flag in iccr read ackb bit in icsr set trs = 0 in iccr read icdr read iric flag in iccr iric = 1? yes yes no no [1] [4] [5] [2] [3] slave transmit mode end of transmission (ackb = 1)? clear iric in iccr set transmit data for the second and subsequent bytes. wait for 1 byte to be transmitted. test for end of transfer. select slave receive mode. dummy read (to release the scl line). [1] [2] [3] [4] [5] figure 23.17 flowchart for slave receive mode (example) 23.3.10 initializing internal status the i 2 c can forcibly initialize the i 2 c internal status when a dead lock occurs during communication. initialization is enabled by (1) setting the clr3 to clr0 bits in ddcswr, or (2) clearing the ice bit. for details on clr3 to clr0 settings, refer to section 23.2.8, ddc switch register (ddcswr). (1) initialized status this function initializes the following: ? tdre and rdrf internal flags ? transmit/receive sequencer and internal clock counter ? internal latches (wait, clock, or data output) which holds the levels output from the scl and sda pins this function does not initialize the following: ? register contents (icdr, sar, sarx, icmr, iccr, icsr, ddcswr, and stcr) section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 497 of 1174 rej09b0329-0200 ? internal latches which holds the register read information to set or clear the flags in icmr, iccr, icsr, and ddcswr ? bit counter (bc2 to bc0) value in icmr ? sources of interrupts generated (interrupts that has been transferred to the interrupt controller) (2) notes on initialization ? interrupt flags and interrupt sources are not cleared; clear them by software if necessary. ? other register flags cannot be assumed to be cleared, either; clear them by software if necessary. ? when initialization is specified by the ddcswr settings, the data written to the clr3 to clr0 bits are not held. when initializing the i 2 c, be sure to use the mov instruction to write to all the clr3 to clr0 bits at the same time; do not use bit manipulation instructions such as bclr. when reinitializi ng the module status, all the clr3 to clr0 bits must be rewritten to at the same time. ? if a flag is cleared during transfer, the i 2 c module stops transfer immediately, and releases the control of the scl and sda pins. before st arting again, set the registers to appropriate values to make a correct communication if necessary. this module initializing function does not modify the bbsy bit value, but in some cases, depending on the scl and sda pin status and the release timing, the signal waveforms at the scl and sda pins may indicate the stop condition, and accordingly the bbsy bit may be cleared. other bits or flags may be affected in the same way by module initialization. to avoid these problems, take the following procedure to initialize the i 2 c: 1. initialize the i 2 c by setting the clr3 to clr0 bits or the ice bit. 2. execute a stop condition issuing instruction to clear the bbsy bit to 0 (writing 0 to bbsy and scp), and wait for two cycles of the transfer clock. 3. initialize the i 2 c again by setting the clr3 to clr0 bits or the ice bit. 4. set the registers in i 2 c to appropriate values. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 498 of 1174 rej09b0329-0200 23.4 usage notes 1. in master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. to output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check th at scl and sda are both low, then issue the instruction that generates the stop condition. note that the scl may briefly remain at a high level immediately after bbsy is cleared to 0. 2. either of the following two conditions will start the next transfer. pay attention to these conditions when reading or writing to icdr. a. write access to icdr when ice = 1 and trs = 1 (including automatic transfer from icdrt to icdrs) b. read access to icdr when ice = 1 and tr s = 0 (including automatic transfer from icdrs to icdrr) 3. table 23.5 shows the timing of scl and sda output in synchronization with the internal clock. timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance, series resistance, and parallel resistance. table 23.5 i 2 c bus timing (scl and sda output) item symbol output timing unit notes scl output cycle time t sclo 28 t cyc to 256 t cyc ns scl output high pulse width t sclho 0.5 t sclo ns scl output low pulse width t scllo 0.5 t sclo ns sda output bus free time t bufo 0.5 t sclo ?1 t cyc ns start condition output hold time t staho 0.5 t sclo ?1 t cyc ns retransmission start condition output setup time t staso 1 t sclo ns stop condition output setup time t stoso 0.5 t sclo +2 t cyc ns data output setup time (master) 1 t scllo ?3 t cyc ns data output setup time (slave) t sdaso 1 t scll ?(6 t cyc or 12 t cyc * ) ns data output hold time t sdaho 3 t cyc ns figure 31.8 (reference) note: * 6 t cyc when iicx is 0, 12 t cyc when 1. 4. scl and sda input is sampled in synchronization with the internal clock. the ac timing therefore depends on the system clock cycle t cyc , as shown in table 31.6. note that the i 2 c bus interface ac timing specifications will not be met with a system clock frequency of less than 5 mhz. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 499 of 1174 rej09b0329-0200 5. the i 2 c bus interface specification for the scl rise time t sr is under 1000 ns (300 ns for high- speed mode). in master mode, the i 2 c bus interface monitors the scl line and synchronizes one bit at a time during communication. if t sr (the time for scl to go from low to v ih ) exceeds the time determined by the input clock of the i 2 c bus interface, the high period of scl is extended. the scl rise time is determined by the pull-up resistance a nd load capacitance of the scl line. to insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that th e scl rise time does not exceed the values given in table 23.6. table 23.6 permissible scl rise time (t sr ) values time indication [ns] iicx t cyc indication i 2 c bus specification (max.) = 8 mhz = 10 mhz normal mode 1000 937 750 0 7.5 t cyc high-speed mode 300 1 17.5 t cyc normal mode 1000 high-speed mode 300 6. the i 2 c bus interface specifications for the scl an d sda rise and fall times are under 1000 ns and 300 ns. the i 2 c bus interface scl and sda output timing is prescribed by t cyc , as shown in table 23.5. however, because of the rise and fall times, the i 2 c bus interface specifications may not be satisfied at the maximum transfer rate. table 23.7 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. t bufo fails to meet the i 2 c bus interface specifications at any fr equency. the solution is either (a) to provide coding to secure the n ecessary interval (approximately 1 s) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input timing permits this output timing for use as slave devices connected to the i 2 c bus. t scllo in high-speed mode and t staso in standard mode fail to satisfy the i 2 c bus interface specifications for worst- case calculations of t sr /t sf . possible solutions that should be investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the speci fications, or (c) selecting devices whose input timing permits this output timing for use as slave devices connected to the i 2 c bus. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 500 of 1174 rej09b0329-0200 7. precautions on reading icdr at the end of master receive mode when terminating the master receive mode, se t trs bit to 1, and select "write" for iccr bbsy = 0 and scp = 0. this forces to move sda from low to high level when scl is at high level, thereby generating the stop condition. now you can read received data from icdr. if, however, any data is remaining on the buffer, received data on icdrs is not transferred to icdr , thus you won't be able to read the second byte data. when it is required to read the second byte data, issue the stop condition from the master receive state (trs bit is 0). before reading data from icdr register, make sure that bbsy bit on iccr register is 0, stop condition is generated and bus is made free. if you try to read received data after the stop condition issue instruction (setting iccr's bbsy = 0 and scp = 0 to write) has been executed but before the actual stop condition is generated, clock may not be appropriately signaled when the next master sending mode is turned on. thus, reasonable care is needed for dete rmining when to read the received data. after the master receive is complete, if you want to re-write iic control bit (such as clearing mst bit) for switching the sending/receiving mode or mo difying settings, it must be done during period (a) indicated in figure 23.18 (after making sure iccr register bbsy bit is cleared to 0). sda scl internal clock bbsy bit bit 0 a (a) 8 9 stop condition start condition start condition is issued generation of the stop condition is checked (bbsy = 0 is set to read) the stop condition issue instruction (bbsy = 0 and scp = 0 set to write) is executed master receive mode icdr read inhibit period figure 23.18 precautions on reading the master receive data section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 501 of 1174 rej09b0329-0200 8. notes on start condition issuance for retransmission figure 23.19 shows the timing of start condition issuance for retransmission, and the timing for subsequently writing data to icdr, together with the corresponding flowchart. after start condition issuance is done and determined the start condition, write the transmit data to icdr. iric = 1 ? scl = low ? iric = 1 ? write transmit data to icdr write bbsy = 1, scp = 0 (icsr) clear iric in icsr read scl pin start condition issuance? other processing no [1] [2] [3] [4] [5] no no yes yes yes yes no [1] wait for end of 1-byte transfer [2] determine wheter scl is low [3] issue restart condition instruction for transmission [4] determine whether start condition is generated or not [5] set transmit data (slave address + r/ w ) note: program so that processing instruction [3] to [5] is executed continuously. [5] icdr write (next transmit data) [4] iric determination [2] determination of scl=low [1] iric determination scl sda ack bit 7 9 iric start condition (retransmission) [3] issue restart condition instruction for retransmission figure 23.19 flowchart and timing of start condition instruction issuance for retransmission section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 502 of 1174 rej09b0329-0200 9. notes on i 2 c bus interface stop condition instruction issuance if the rise time of the 9th scl acknowledge ex ceeds the specification because the bus load capacitance is large, or if there is a slave device of the type th at drives scl low to effect a wait, issue the stop condition instruction after reading scl and determining it to be low, as shown below. stop condition scl iric [1] determination of scl = low 9th clock vih high period secured [2] stop condition instruction issuance sda as waveform rise is late, scl is detected as low figure 23.20 timing of stop condition issuance section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 503 of 1174 rej09b0329-0200 table 23.7 i 2 c bus timing (with maximum influence of t sr /t sf ) time indication (at maximum transfer rate) [ns] item t cyc indication t sr /t sf influence (max.) i 2 c bus specification (min.) = 8 mhz = 10 mhz normal mode ? 1000 4000 t sclho 0.5 t sclo (?t sr ) high-speed mode ? 300 600 normal mode ? 250 4700 t scllo 0.5 t sclo (?t sf ) high-speed mode ? 250 1300 normal mode ? 1000 4700 3875 * 1 3900 * 1 t bufo 0.5 t sclo ?1 t cyc (?t sr ) high-speed mode ? 300 1300 825 * 1 850 * 1 normal mode ? 250 4000 4625 4650 t staho 0.5 t sclo ?1 t cyc (?t sf ) high-speed mode ? 250 600 875 900 normal mode ? 1000 4700 9000 9000 t staso 1 t sclo (?t sr ) high-speed mode ? 300 600 2200 2200 normal mode ? 1000 4000 4250 4200 t stoso 0.5 t sclo +2 t cyc (?t sr ) high-speed mode ? 300 600 1200 1150 normal mode ? 1000 250 3325 3400 t sdaso (master) 1 t scllo * 3 ?3 t cyc (-t sr ) high-speed mode ? 300 100 625 700 normal mode ? 1000 250 2200 2500 t sdaso (slave) 1 t scll * 3 ?12 t cyc * 2 (?t sr ) high-speed mode ? 300 100 ? 500 * 1 ? 200 * 1 normal mode 0 0 375 300 t sdaho 3 t cyc high-speed mode 0 0 notes: 1. does not meet the i 2 c bus interface specification. remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. the values in the above table will vary depending on the settings of the iicx bit and bits cks0 to cks2. depending on the frequency it may not be possible to achieve the maximum transfer rate; therefore, whether or not the i 2 c bus interface specifications are met must be determined in accordance with the actual setting conditions. 2. value when the iicx bit is set to 1. when the iicx bit is cleared to 0, the value is (t scll ? 6 t cyc ). 3. calculated using the i 2 c bus specification values (standard mode: 4700 ns min.; high- speed mode: 1300 ns min.). section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 504 of 1174 rej09b0329-0200 10. notes on wait function ? conditions to cause this phenomenon when both of the following conditions are satisfied, the clock pulse of the 9th clock could be outputted continuously in master mode using the wait function due to the failure of the wait insertion after the 8th clock fall. (1) setting the wait bit of the icmr register to 1 and operating wait, in master mode (2) if the iric bit of interrupt flag is cleared from 1 to 0 between the fall of the 7th clock and the fall of the 8th clock. ? error phenomenon normally, wait state will be cancelled by clearing the iric flag bit from 1 to 0 after the fall of the 8th clock in wait state. in this cas e, if the iric flag b it is cleared between the 7th clock fall and the 8th clock fall, the iric flag clear- data will be retained internally. therefore, the wait state will be cancelled right after wait insertion on 8th clock fall. ? restrictions please clear the iric flag before the rise of the 7th clock (the counter value of bc2 through bc0 should be 2 or greater), after the iric flag is set to 1 on the rise of the 9th clock. if the iric flag-clear is delayed due to the interrupt or other processes and the value of bc counter is turned to 1 or 0, please confirm the scl pins are in l? state after the counter value of bc2 through bc0 is turned to 0, and clear the iric flag. (see figure 23.21.) scl bc2?bc0 transmit/receive data a asd 7 6 5 4 3 2 1 0 7 6 5 1 2 3 4 5 6 7 8 9 1 2 3 0 iric flag clear unavailable iric flag clear available iric flag clear available 9 a iric (operation example) scl = ?l? confirm iric clear when bc2-0 2 iric clear transmit/receive data figure 23.21 iric flag clear timing on wait operation section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 505 of 1174 rej09b0329-0200 11. notes on icdr reads and iccr access in slave transmit mode in a transmit operation in the slave mode of the i 2 c bus interface, do not read the icdr register or read or write to the iccr register during the period indicated by the shaded portion in figure 23.22. normally, when interrupt processing is triggered in synchronization with the rising edge of the 9th clock cycle, the period in question has already elapsed when the transition to interrupt processing takes place, so there is no problem w ith reading the icdr register or reading or writing to the iccr register. to ensure that the interrupt processing is performed properly, one of the following two conditions should be applied. (1) make sure that reading received data from the icdr register, or reading or writing to the iccr register, is completed before the ne xt slave address receive operation starts. (2) monitor the bc2 to bc0 counter in the icmr register and, when the value of bc2 to bc0 is 000 (8th or 9th clock cycle), allow a waiting time of at least 2 transfer clock cycles in order to involve the problem period in question before reading from the icdr register, or reading or writing to the iccr register. sda r/w waveforms if problem occurs bit 7 icdr write data transmission period when icdr reads and iccr reads and writes are prohibited (6 system clock cycles) detection of 9th clock cycle rising edge a 89 scl trs address received figure 23.22 icdr read and iccr access timing in slave transmit mode section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 506 of 1174 rej09b0329-0200 12. notes on trs bit setting in slave mode from the detection of the rising edge of the 9th clock cycle or of a stop condition to when the rising edge of the next scl pin signal is detected (the period indicated as (a) in figure 23.23) in the slave mode of the i 2 c bus interface, the value set in the trs bit in the iccr register is effective immediately. however, at other times (indicated as (b) in figure 23.23) the value set in the trs bit is put on hold until the next rising edge of the 9th clock cycle or stop cond ition is detected, rather than taking effect immediately. this results in the actual internal value of the trs bit remaining 1 (transmit mode) and no acknowledge bit being sent at th e 9th clock cycle address receive completion in the case of an address receive operation following a rest art condition input with no stop condition intervening. when receiving an address in the slave mode , clear the trs bit to 0 during the period indicated as (a) in figure 23.23. to cancel the holding of the sc l bit low by the wait function in the slave mode, clear the trs bit to 0 and then perform a dummy read of the icdr register. (a) restart condition icdr dummy read detection of 9th clock cycle rising edge trs bit set detection of 9th clock cycle rising edge 89 (b) data transmission sda scl trs 123456789 a address reception trs bit setting hold time figure 23.23 trs bit setting timing in slave mode section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 507 of 1174 rej09b0329-0200 13. notes on arbitration lost in master mode the i 2 c bus interface recognizes the data in tr ansmit/receive frame as an address when arbitration is lost in master mode and a transition to slave receive mode is automatically carried out. when arbitration is lost not in the first frame but in the second frame or subsequent frame, transmit/receive data that is not an address is co mpared with the value set in the sar or sarx register as an address. if the receive data matches with the address in the sar or sarx register, the i 2 c bus interface erroneously recognizes that the address call has occurred. (see figure 23.24.) in multi-master mode, a bus conflict could happen. when the i 2 c bus interface is operated in master mode, check the state of the al bit in the icsr register every time after one frame of data has been transmitted or received. when arbitration is lost during transmitting the second frame or subsequent frame, take avoidance measures. ssla r/ w ssla r/ w a data2 ssla r/ w a sla r/ w a data3 a data4 data1 i 2 c bus interface (master transmit mode) transmit data match transmit timing match ? receive address is ignored ? automatically transferred to slave receive mode ? receive data is recognized as an address ? when the receive data matches to the address set in the sar or sarx register, the i 2 c bus interface operates as a slave device ? arbitration is lost ? the al flag in icsr is set to 1 transmit data does not match other device (master transmit mode) i 2 c bus interface (slave receive mode) data contention a a a figure 23.24 diagram of erroneous operation when arbitration is lost though it is prohibited in the normal i 2 c protocol, the same problem may occur when the mst bit is erroneously set to 1 and a transition to master mode is occurred during data transmission or reception in slave mode. in multi-master mode, pay attention to the setting of the mst bit when a bus conflict may occur. in this case, the mst bit in the iccr register should be set to 1 according to the order below. (a) make sure that the bbsy flag in the iccr register is 0 and the bus is free before setting the mst bit. (b) set the mst bit to 1. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 508 of 1174 rej09b0329-0200 (c) to confirm that the bus was not entered to the busy state while the mst bit is being set, check that the bbsy flag in the iccr register is 0 imme diately after the mst bit has been set. 14. notes on interrupt occurrence after ackb reception ? conditions to cause this failure the iric flag is set to 1 when both of the following conditions are satisfied. ? 1 is received as the acknowledge bit for transm it data and the ackb bit in icsr is set to 1 ? rising edge of the 9th transmit/recei ve clock is input to the scl pin when the above two conditions are satisfied in slave receive mode, an unnecessary interrupt occurs. figure 23.25 shows the note on interrupt occurren ce in slave mode after receiving 1 as the acknowledge bit (ackb = 1). (1) for the last transmit data in master transmit mode or sl ave transmit mode, 1 is received as the acknowledge bit. if the acke bit in iccr is set to 1 at this time, the ackb bit in icsr is set to 1. (2) after switching to slave receive mode , the start condition is input, and address reception is performed next. (3) even if the received address does not ma tch the address set in sar or sarx, the iric flag is set to 1 at the rise of the 9th transmit/receive clock, thus causing an interrupt to occur. note that if the slave address matches, an interrupt is to be generated at the rise of the 9th transmit/receive clock as normal operation, so this is not erroneous operation. ? restriction in a transmit operation of the i 2 c bus interface module, carry out the following countermeasures. (1) after 1 is received as the acknowledge b it for transmit data, cl ear the acke bit in iccr to 0 to clear the ackb bit to 0. (2) to enable acknowledge bit reception afterwards, set the acke bit to 1 again. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 509 of 1174 rej09b0329-0200 sda scl a ackb bit (1) acknowledge bit is received and the ackb bit is set to 1. 89 123456789 iric flag start condition 12 n stop condition stop condition detection data (2) address that does not match is received. master transmit mode or slave transmit mode countermeasure: clear the acke bit to 0 to clear the ackb bit. slave reception mode address (3) unnecessary interrupt occurs (received address is invalid). figure 23.25 note on interrupt occurren ce in slave mode after ackb = 1 reception 15. notes on trs bit setting and icdr register access ? conditions to cause this failure low-fixation of the scl pins is cancelled incorrectly when the following conditions are satisfied. (1) master mode figure 23.26 shows the notes on icdr reading (trs = 1) in master mode. (1) when previously received 2-bytes data remains in icdr unread (icdrs are full). (2) reads icdr register after switching to transmit mode (trs = 1). (rdrf = 0 state) (3) sets to receive mode (trs = 0), afte r transmitting rev.1 frame of issued start condition by master mode. (2) slave mode figure 23.27 shows the notes on icdr writing (trs = 0) in slave mode. (1) writes icdr register in receive mode (trs = 0), after entering the start condition by slave mode (tdre = 0 state). address match with rev.1 frame, receive 1 by r/w bit, and switches to transmit mode (trs = 1). when these conditions are satisfied, the low fixation of the scl pins is cancelled without icdr register access after rev.1 frame is transferred. section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 510 of 1174 rej09b0329-0200 ? restriction please carry out the following countermeasures when transmitting/receiving via the iic bus interface module. (1) please read the icdr registers in recei ve mode, and write them in transmit mode. (2) in receiving operation with master mode, please issue the start condition after clearing the internal flag of the ii c bus interface module, using clr3 to clr0 bit of the ddcswr register on bus-free state (bbsy = 0). sda scl a trs bit detection of 9th clock rise (trs = 1) address 8 rdrf bit start condition 12 a 3 stop condition icdr read trs = 0 setting data icdrs data full along with icdrs: icdrr transfer cancel condition of scl = low fixation is set. (3) trs = 0 (2) rdrf = 0 (1) icdrs data full 9 12345678 9 figure 16.26 notes on icdr reading with trs = 1 setting in master mode section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 511 of 1174 rej09b0329-0200 sda scl a trs bit trs = 0 setting address 89 8 9 tdre bit start condition 12 a 3 stop condition icdr write data (2) trs = 1 (1) tdre = 0 4 automatic trs = 1 setting by receiving r/w = 1 along with icdrs: icdrr transfer cancel condition of scl = low fixation 1234567 figure 16.27 notes on icdr writing with trs = 0 setting in slave mode section 23 i 2 c bus interface (iic) rev.2.00 jan. 15, 2007 page 512 of 1174 rej09b0329-0200 section 24 a/d converter rev.2.00 jan. 15, 2007 page 513 of 1174 rej09b0329-0200 section 24 a/d converter 24.1 overview this lsi incorporates a 10-bit successive-approximations a/d converter that allows up to 12 analog input channels to be selected. 24.1.1 features a/d converter has the following features. ? 10-bit resolution ? 12 input channels ? sample and hold function ? choice of software, hardware (internal signal) triggering or external triggering for a/d conversion start. ? a/d conversion end interrupt request generation section 24 a/d converter rev.2.00 jan. 15, 2007 page 514 of 1174 rej09b0329-0200 24.1.2 block diagram figure 24.1 shows a block diagram of the a/d converter. /2 /4 adtrg interrupt request an0 vref av cc av ss reference voltage sample-and- hold circuit chopper type comparator an1 an2 an3 an4 an5 an6 an7 an8 an9 ana anb dfg adtrg (hsw timing generator) internal data bus legend: adr ahr : software trigger a/d result register : hardware trigger a/d result register adtrg, dfg adtrg : hardware trigger : a/d external trigger input adcr adcsr : a/d control register : a/d control/status register adtsr: a/d trigger selection register - + 10-bit d/a hardware control circuit control circuit analog multiplexer successive approximation register a d r a h r a d c s r a d c r a d t s r figure 24.1 block diagram of a/d converter section 24 a/d converter rev.2.00 jan. 15, 2007 page 515 of 1174 rej09b0329-0200 24.1.3 pin configuration table 24.1 summarizes the input pins used by the a/d converter. table 24.1 a/d converter pins name abbrev. i/o function analog power supply pin av cc input analog block power supply and a/d conversion reference voltage analog ground pin av ss input analog block ground and a/d conversion reference voltage analog input pin 0 an0 input analog input channel 0 analog input pin 1 an1 input analog input channel 1 analog input pin 2 an2 input analog input channel 2 analog input pin 3 an3 input analog input channel 3 analog input pin 4 an4 input analog input channel 4 analog input pin 5 an5 input analog input channel 5 analog input pin 6 an6 input analog input channel 6 analog input pin 7 an7 input analog input channel 7 analog input pin 8 an8 input analog input channel 8 analog input pin 9 an9 input analog input channel 9 analog input pin a ana input analog input channel a analog input pin b anb input analog input channel b a/d external trigger input pin adtrg input external trigger input for starting a/d conversion section 24 a/d converter rev.2.00 jan. 15, 2007 page 516 of 1174 rej09b0329-0200 24.1.4 register configuration table 24.2 summarizes the registers of the a/d converter. table 24.2 a/d converter registers name abbrev. r/w size initial value address * 2 software trigger a/d result register h adrh r byte h'00 h'd130 software trigger a/d result register l adrl r byte h'00 h'd131 hardware trigger a/d result re gister h ahrh r byte h'00 h'd132 hardware trigger a/d result register l ahrl r byte h'00 h'd133 a/d control register adcr r/w byte h'40 h'd134 a/d control/status register adcsr r (w) * 1 byte h'01 h'd135 a/d trigger selection register adtsr r/w byte h'fc h'd136 port mode register 0 pmr0 r/w byte h'00 h'ffcd notes: 1. only 0 can be written in bits 7 and 6, to clear the flag. bits 3 to 1 are read-only. 2. lower 16 bits of the address. section 24 a/d converter rev.2.00 jan. 15, 2007 page 517 of 1174 rej09b0329-0200 24.2 register descriptions 24.2.1 software-triggered a/ d result register (adr) adrh adrl 10 32 54 ?? ?? ?? ?? ?? ?? 7 0 r 6 0 r 9 0 r 8 0 r 11 0 r 10 0 r 0 r 0 r 0 r adr9 adr8 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 0 r 12 13 14 15 0 0 0 0 0 0 bit : initial value : r/w : the software-triggered a/d result register (adr) is a register that stores the result of an a/d conversion started by software. the a/d-converted data is 10-bit data. upon completion of software-triggered a/d conversion, the 10-bit result data is transferred to adr and the data is retained until the next software- triggered a/d conversion completion. the upper 8 bits of the data are stored in the upper bytes (bits 15 to 8) of adr, and the lower 2 bits are stored in the lower bytes (bits 7 and 6). bits 5 to 0 are always read as 0. adr can be read by the cpu at any time, but the adr value during a/d conversion is not fixed. the upper bytes can always be read directly, but the data in the lower bytes is transferred via a temporary register (temp). for details, see section 24.3, interface to bus master. adr is a 16-bit read-only register which is initia lized to h'0000 at a reset, and in module stop mode, standby mode, watch mode, subactive mode and subsleep mode. 24.2.2 hardware-triggered a/ d result register (ahr) ahrh ahrl 10 32 54 ?? ?? ?? ?? ?? ?? 7 0 r 6 0 r 9 0 r 8 0 r 11 0 r 10 0 r 0 r 0 r 0 r ahr9 ahr8 ahr7 ahr6 ahr5 ahr4 ahr3 ahr2 ahr1 ahr0 0 r 12 13 14 15 0 0 0 0 0 0 bit : initial value : r/w : the hardware-triggered a/d result register (ahr) is a register that stores the result of an a/d conversion started by hardware (internal signal: adtrg and dfg) or by external trigger input ( adtrg ). the a/d-converted data is 10-bit data. upon completion of hardware- or external-triggered a/d conversion, the 10-bit result data is transferred to ahr and the data is retained until the next hardware- or external- triggered a/d conversion completion. the upper 8 bits of the data are stored in the upper bytes (bits 15 to 8) of ahr, and the lower 2 bits are stored in the lower bytes (bits 7 and 6). bits 5 to 0 are always read as 0. section 24 a/d converter rev.2.00 jan. 15, 2007 page 518 of 1174 rej09b0329-0200 ahr can be read by the cpu at any time, but the ahr value during a/d conversion is not fixed. the upper bytes can always be read directly, but the data in the lower bytes is transferred via a temporary register (temp). for details, see section 24.3, interface to bus master. ahr is a 16-bit read-only register which is initia lized to h'0000 at a reset, and in module stop mode, standby mode, watch mode, subactive mode and subsleep mode. 24.2.3 a/d control register (adcr) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 5 0 6 ? ? 1 7 r/w r/w r/w hch1 0 r/w ck hch0 sch3 sch2 sch1 sch0 bit : initial value : r/w : adcr is a register that sets a/d conversion speed and selects analog input channel. when executing adcr setting, make sure that the sst and hst flags in adcsr is set to 0. adcr is an 8-bit readable/writable register that is initialized to h'40 by a reset, and in module stop mode, standby mode, watch mode, subactive mode and subsleep mode. bit 7 ? clock select (ck): sets a/d conversion speed. bit 7 ck description 0 conversion frequency is 266 states (initial value) 1 conversion frequency is 134 states note: a/d conversion starts when 1 is written in sst, or when hst is set to 1. the conversion period is the time from when this start flag is set until the flag is cleared at the end of conversion. actual sample-and-hold takes place (repeatedly) during the conversion frequency shown in figure 24.2. section 24 a/d converter rev.2.00 jan. 15, 2007 page 519 of 1174 rej09b0329-0200 conversion frequency note: irq sampling; conversion period (134 or 266 states) interrupt request flag irq sampling (cpu) states instruction execution mov.b write start flag when conversion ends, the start flag is cleared and the interrupt request flag is set. the cpu recognizes the interrupt in the last execution state of an instruction, and executes interrupt exception handling after completing the instruction. figure 24.2 internal op eration of a/d converter bit 6 ? reserved: this bit cannot be modified and is always read as 1. bits 5 and 4 ? hardware channel sel ect (hch1, hch0): these bits select the analog input channel that is converted by hardware triggering or triggering by an external input. only channels an8 to anb are available for hardware- or external-triggered conversion. bit 5 bit 4 hch1 hch0 analog input channel 0 an8 (initial value) 0 1 an9 1 0 ana 1 anb section 24 a/d converter rev.2.00 jan. 15, 2007 page 520 of 1174 rej09b0329-0200 bits 3 to 0 ? software channel select (sch3 to sch0): these bits select the analog input channel that is converted by software triggering. when channels an0 to an7 are used, appropriate pin settings must be made in port mode register 0 (pmr0). for pin settings, see section 24.2.6, port mode register 0 (pmr0). bit 3 bit 2 bit 1 bit 0 sch3 sch2 sch1 sch0 analog input channel 0 an0 (initial value) 0 1 an1 0 an2 0 1 1 an3 0 an4 0 1 an5 0 an6 0 1 1 1 an7 0 an8 0 1 an9 0 ana 0 1 1 anb 1 1 * * no channel selected for software-triggered conversion legend: * don't care. note: if conversion is started by software when sch3 to sch0 are set to 11 ** , the conversion result is undetermined. hardware- or external-triggered conversion, however, will be performed on the channel selected by hch1 and hch0. section 24 a/d converter rev.2.00 jan. 15, 2007 page 521 of 1174 rej09b0329-0200 24.2.4 a/d control/status register (adcsr) 0 ? ? 0 1 0 r 2 0 r 3 0 4 0 r/w 5 0 6 7 r/(w) * r r/w adie 0 r/(w) * send sst hst busy scnl hend 1 bit : initial value : r/w : note: * only 0 can be written to bits 7 and 6, to clear the flag. the a/d status register (adcsr) is an 8-bit register that can be used to start or stop a/d conversion, or check the status of the a/d converter. a/d conversion starts when 1 is written in sst flag. a/d conversion can also start by setting hst flag to 1 by hardware- or external-triggering. for adtrg start by hsw timing generator in hardware triggering, see section 26.4, hsw (head- switch) timing generator. when conversion ends, the converted data is stored in the software-triggered a/d result register (adr) or hardware-triggered a/d result register (ahr), and the sst or hst bit is cleared to 0. if software-triggering and hardware- or external-triggering are generated at the same time, priority is given to hardware- or external-triggering. adcsr is an 8-bit register whic h is initialized to h'01 by a reset, and in module stop mode, standby mode, watch mode, subactive mode and subsleep mode. bit 7 ? software a/d end flag (send): indicates the end of a/d conversion. bit 7 send description 0 [clearing condition] (initial value) 0 is written after reading 1 1 [setting condition] software-triggered a/d conversion has ended section 24 a/d converter rev.2.00 jan. 15, 2007 page 522 of 1174 rej09b0329-0200 bit 6 ? hardware a/d end flag (hend): indicates that hardware- or external-triggered a/d conversion has ended. bit 6 hend description 0 [clearing condition] (initial value) 0 is written after reading 1 1 [setting condition] hardware- or external-triggered a/d conversion has ended bit 5 ? a/d interrupt enable (adie): selects enable or disable of interrupt (adi) generation upon a/d conversion end. bit 5 adie description 0 interrupt (adi) upon a/d conversion end is disabled (initial value) 1 interrupt (adi) upon a/d conversion end is enabled bit 4 ? software a/d start flag (sst): indicates or controls the start and end of software- triggered a/d conversion. this bit remains 1 during software-triggered a/d conversion. when 0 is written in this bit, software-triggered a/d conversion operation can forcibly be aborted. bit 4 sst description read: indicates that software-triggered a/d conversion has ended or been stopped (initial value) 0 write: software-triggered a/d conversion is aborted 1 read: indicates that software-triggered a/d conversion is in progress write: starts software-triggered a/d conversion section 24 a/d converter rev.2.00 jan. 15, 2007 page 523 of 1174 rej09b0329-0200 bit 3 ? hardware a/d status flag (hst): indicates the status of hard ware- or external-triggered a/d conversion. when 0 is written in this bit, a/d conversion is aborted regardless of whether it was hardware-triggered or external-triggered. bit 3 hst description read: hardware- or external-triggered a/d conversion is not in progress (initial value) 0 write: hardware- or external-triggered a/d conversion is aborted 1 hardware- or external-triggered a/d conversion is in progress bit 2 ? busy flag (busy): during hardware- or external-triggered a/d conversion, if software attempts to start a/d conversion by writing to the sst bit, the sst bit is not modified and instead the busy flag is set to 1. this flag is cleared when the hardware-triggered a/d result register (ahr) is read. bit 2 busy description 0 no contention for a/d conversion (initial value) 1 indicates an attempt to execute software-triggered a/d conversion while hardware- or external-triggered a/d conversion was in progress bit 1 ? software-triggered convers ion cancel flag (scnl): indicates that software-triggered a/d conversion was canceled by the start of hardware-triggered a/d conversion. this flag is cleared when a/d conversion is started by software. bit 1 scnl description 0 no contention for a/d conversion (initial value) 1 indicates that software-triggered a/d conversion was canceled by the start of hardware-triggered a/d conversion bit 0 ? reserved: this bit cannot be modified and is always read as 1. section 24 a/d converter rev.2.00 jan. 15, 2007 page 524 of 1174 rej09b0329-0200 24.2.5 trigger select register (adtsr) 0 1 2 3 0 4 r/w 5 6 7 ? ? ? ? ? ? ? ? ? ? ? ? trgs1 0 r/w trgs0 111111 bit : initial value : r/w : the trigger select register (adtsr) selects hard ware- or external-triggered a/d conversion start factor. adtsr is an 8-bit readable/writabl e register that is initialized to h'fc by a reset, and in module stop mode, standby mode, watch mode, subactive mode and subsleep mode. bits 7 to 2 ? reserved: these bits cannot be modified and are always read as 1. bits 1 and 0 ? trigger select (trgs1, trgs0): these bits select hardware- or external- triggered a/d conversion start factor. set these bits when a/d conversion is not in progress. bit 1 bit 0 trgs1 trgs0 description 0 hardware- or external-triggered a/d conversion is disabled (initial value) 0 1 hardware-triggered (adtrg) a/d conversion is selected 1 0 hardware-triggered (dfg) a/d conversion is selected 1 external-triggered ( adtrg ) a/d conversion is selected 24.2.6 port mode register 0 (pmr0) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 6 0 7 pmr04 pmr03 pmr02 pmr01 pmr00 0 r/w pmr07 r/w r/w r/w pmr06 pmr05 bit : initial value : r/w : port mode register 0 (pmr0) controls switching of each pin function of port 0. switching is specified for each bit. pmr0 is an 8-bit readable/writable register and is initialized to h'00 by a reset. section 24 a/d converter rev.2.00 jan. 15, 2007 page 525 of 1174 rej09b0329-0200 bits 7 to 0 ? p07/an7 to p00/an0 pin switching (pmr07 to pmr00): these bits set the p0n/ann pin as the input pin for p0n or as the ann pin for a/d conversion analog input channel. bit n pmr0n description 0 p0n/ann functions as a general-purpose input port (initial value) 1 p0n/ann functions as an analog input channel note: n = 7 to 0 24.2.7 module stop control register (mstpcr) 7 1 mstp15 r/w mstpcrh 6 1 mstp14 r/w 5 1 mstp13 r/w 4 1 mstp12 r/w 3 1 mstp11 r/w 2 1 mstp10 r/w 1 1 mstp9 r/w 0 1 mstp8 r/w 7 1 mstp7 r/w 6 1 mstp6 r/w 5 1 mstp5 r/w 4 1 mstp4 r/w 3 1 mstp3 r/w 2 1 mstp2 r/w 1 1 mstp1 r/w 0 1 mstp0 r/w mstpcrl bit : initial value : r/w : mstpcr consists of 8-bit readable/writable registers and performs module stop mode control. when the mstp2 bit in mstpcr is set to 1, a/d converter operation stops at the end of the bus cycle and a transition is made to module stop mode. for details, see section 4.5, module stop mode. mstpcr is initialized to h'ffff by a reset bit 2 ? module stop (mstp2): specifies the a/d converter module stop mode. mstpcrl bit 2 mstp2 description 0 a/d converter module stop mode is cleared 1 a/d converter module stop mode is set (initial value) section 24 a/d converter rev.2.00 jan. 15, 2007 page 526 of 1174 rej09b0329-0200 24.3 interface to bus master adr and ahr are 16-bit registers, but the data bus to the bus master is only 8 bits wide. therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (temp). a data reading from adr and ahr is performed as follows. when the upper byte is read, the upper byte value is transferred to the cpu and the lower byte value is transferred to temp. next, when the lower byte is r ead, the temp contents are transferred to the cpu. when reading adr and ahr, always read the upper byte before the lower byte. it is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. figure 24.3 shows the data flow for adr access. the data flow for ahr access is the same. bus master (h'aa) adrh (h'aa) adrl (h'40) lower byte read bus master (h'40) adrh (h'aa) adrl (h'40) temp (h'40) temp (h'40) module data bus module data bus bus interface bus interface upper byte read figure 24.3 adr access opera tion (reading h'aa40) section 24 a/d converter rev.2.00 jan. 15, 2007 page 527 of 1174 rej09b0329-0200 24.4 operation the a/d converter operates by successive approximations with 10-bit resolution. 24.4.1 software-trigg ered a/d conversion a/d conversion starts when software sets the software a/d start flag (sst bit) to 1. the sst bit remains set to 1 during a/d conversion, and is automatically cleared to 0 when conversion ends. conversion can be software-triggered on any of the 12 channels provided by analog input pins an0 to anb. bits sch3 to sch0 in adcr select the analog input pin used for software- triggered a/d conversion. pins an8 to anb are also available for hardware- or external-triggered conversion. when conversion ends, send flag in adcsr bit is set to 1. if adie bit in adcsr is also set to 1, an a/d conversion end interrupt occurs. if the conversion time or input channel selection in adcr needs to be changed during a/d conversion, to avoid malfunctions, first clear the sst bit to 0 to halt a/d conversion. if software writes 1 in the sst bit to start software-triggered conversion while hardware- or external-triggered conversion is in progress, the hardware- or external-triggered conversion has priority and the software-triggered conversion is not executed. at this time, busy flag in adcsr is set to 1. the busy flag is cleared to 0 when the hardware-t riggered a/d result register (ahr) is read. if conversion is triggered by hardware while software-triggered conversion is in progress, the software-triggered conversion is immediately can celed and the sst flag is cleared to 0, and scnl flag in adcsr is set to 1. the scnl flag is cl eared when software writes 1 in the sst bit to start conversion after the hardware-triggered conversion ends. section 24 a/d converter rev.2.00 jan. 15, 2007 page 528 of 1174 rej09b0329-0200 24.4.2 hardware- or extern al-triggered a/d conversion the system contains the hardware trigger function that allows to turn on a/d conversion at a specified timing by use of the hardware trigger (internal signals: adtrg and dfg) and the incoming external trigger ( adtrg ). this function can be used to measure an analog signal that varies in synchronization with an external signal at a fixed timing. to execute hardware- or external-triggered a/d conversion, select appropriate start factor in trgs1 and trgs0 bits in adtsr. when the selected triggering occurs, hst flag in adcsr is set to 1 and a/d conversion starts. the hst flag remains 1 during a/d conversion, and is automatically cleared to 0 when conversion ends. for adtrg start by hsw timing generator in hardware triggering, see section 26.4, hsw (head-switch) timing generator. setting of the analog input pins on four channels from an8 to anb can be modified with the hardware trigger or the incoming external trigger. setting is done from hch1 and hch0 bits on adcr. pins an8 to anb are also available for software-triggered conversion. when conversion ends, hend flag in adcsr is set to 1. if adie bit in adcsr is also set to 1, an a/d conversion end interrupt occurs. if the conversion time or input channel selection in adcr needs to be changed during a/d conversion, to avoid malfunctions, first clear the hst flag to 0 to halt a/d conversion. if software writes 1 in the sst bit to start software-triggered conversion while hardware- or external-triggered conversion is in progress, the hardware- or external-triggered conversion has priority and the software-triggered conversion is not executed. at this time, busy flag in adcsr is set to 1. the busy flag is cleared to 0 when the hardware-t riggered a/d result register (ahr) is read. if conversion is triggered by hardware while software-triggered conversion is in progress, the software-triggered conversion is i mmediately canceled and the sst flag is cleared to 0, and scnl flag in adcsr is set to 1 (the sc nl flag is cleared when software writes 1 in the sst bit to start conversion after the hardware-triggered conversion ends). the analog input channel changes automatically from the channel that was undergoing software-triggered conversion (selected by bits sch3 to sch0 in adcr) to the channel selected by bits hch1 and hch0 in adcr for hardware- or external-triggered conversion. after the hardware- or external-triggered conversion ends, the channel reverts to the channel select ed by the software-triggered conversion channel select bits in adcr. hardware- or external-triggered conversion has priority over software-triggered conversion, so the a/d interrupt-handling routine should check the scnl and busy flags when it processes the converted data. section 24 a/d converter rev.2.00 jan. 15, 2007 page 529 of 1174 rej09b0329-0200 24.5 interrupt sources when a/d conversion ends, send or hend flag in adcsr is set to 1. the a/d conversion end interrupt (adi) can be enabled or disabled by adie bit in adcsr. figure 24.4 shows the block diagram of a/d conversion end interrupt. a/d conversion end interrupt (adi) to interrupt controller a/d control/status register (adcsr) send hend adie figure 24.4 block diagram of a/d conversion end interrupt section 24 a/d converter rev.2.00 jan. 15, 2007 page 530 of 1174 rej09b0329-0200 section 25 address trap controller (atc) rev.2.00 jan. 15, 2007 page 531 of 1174 rej09b0329-0200 section 25 address trap controller (atc) 25.1 overview the address trap controller (atc) is capable of generating interrupt by setting an address to trap, when the address set a ppears during bus cycle. 25.1.1 features address to trap can be set independently at three points. 25.1.2 block diagram figure 25.1 shows a block diagram of the address trap controller. atcr legend: tar0 to 2 interrupt request modules bus internal bus atcr tar0 tar1 tar2 trap condition comparator bus interface : address trap control register : trap address register 0 to 2 figure 25.1 block diagram of atc section 25 address trap controller (atc) rev.2.00 jan. 15, 2007 page 532 of 1174 rej09b0329-0200 25.1.3 register configuration table 25.1 register list name abbrev. r/w initial value address * address trap control register atcr r/w h'f8 h'ffb9 trap address register 0 tar0 r/w h'f00000 h'ffb0 to h'ffb2 trap address register 1 tar1 r/w h'f00000 h'ffb3 to h'ffb5 trap address register 2 tar2 r/w h'f00000 h'ffb6 to h'ffb8 note: * lower 16 bits of the address. 25.2 register descriptions 25.2.1 address trap control register (atcr) 0 0 1 0 r/w 2 0 r/w 3 1 4 1 5 1 6 1 7 ? ? ? ? ? ? ? ? ? ? r/w trc2 trc1 trc0 1 bit : initial value : r/w : bits 7 to 3 ? reserved: these bits cannot be modified and are always read as 1. bit 2 ? trap control 2 (trc2): sets on/off operation of the address trap function 2. bit 2 trc2 description 0 address trap function 2 disabled (initial value) 1 address trap function 2 enabled bit 1 ? trap control 1 (trc1): sets on/off operation of the address trap function 1. bit 1 trc1 description 0 address trap function 1 disabled (initial value) 1 address trap function 1 enabled section 25 address trap controller (atc) rev.2.00 jan. 15, 2007 page 533 of 1174 rej09b0329-0200 bit 0 ? trap control 0 (trc0): sets on/off operation of the address trap function 0. bit 0 trc0 description 0 address trap function 0 disabled (initial value) 1 address trap function 0 enabled 25.2.2 trap address register 2 to 0 (tar2 to tar0) 0 0 1 0 r/w 2 0 r/w 3 4 5 6 7 r/w a18 a17 a16 0 0 r/w 0 r/w r/w a23 a22 a21 0 0 r/w r/w a20 a19 0 0 1 0 r/w 2 0 r/w 3 4 5 6 7 r/w a10 a9 a8 0 0 r/w 0 r/w r/w a15 a14 a13 0 0 r/w r/w a12 a11 0 ? ? 1 0 r/w 2 0 r/w 3 4 5 6 7 a2 a1 0 0 r/w 0 r/w r/w a7 a6 a5 0 0 r/w r/w a4 a3 0 bit : initial value : r/w : bit : initial value : r/w : bit : initial value : r/w : the tar is composed of three 8-bit readable/writable registers (tarna, b, and c) (n = 2 to 0) the tar sets the address to trap. the function of the tar2 to tar0 is the same. the tar is initialized to h'00 by a reset. tara bits 7 to 0: addresses 23 to 16 (a23 to a16) tarb bits 7 to 0: addresses 15 to 8 (a15 to a8) tarc bits 7 to 0: addresses 7 to 1 (a7 to a1) if the value installed in this register and internal address buses a23 to a1 match as a result of comparison, an interruption occurs. for the address to trap, set to the address where the first byte of an instruction exists. in the case of other addresses, it may not be considered that the condition has been satisfied. bit 0 of this register is fixed at 0. the address to trap becomes an even address. the range where comparison is made is h' 000000 to h'fffffe. section 25 address trap controller (atc) rev.2.00 jan. 15, 2007 page 534 of 1174 rej09b0329-0200 25.3 precautions in usage address trap interrupt arises 2 states after prefet ching the trap address. trap interrupt may occur after the trap instruction has been executed, depending on a combination of instructions immediately preceding the set ting up of the address trap. if the instruction to trap immediately follows the branch instruction or the conditional branch instruction, operation may differ, depending on whether the condition was satisfied or not, or the address to be stacked may be located at the bran ch. figures 25.2 to 25.22 show specific operations. for information as to where the next instruction prefetch occurs during the execution cycle of the instruction, see appendix a.5, bus status during instruction execution of this manual or section 2.7 bus state during execution of instruction of the h8s/2600 and h8s/2000 series software manual. (r: w next is the next instruction prefetch.) 25.3.1 basic operations after terminating the execution of the instruction being executed in the second state from the trap address prefetch, the address trap interrupt exception handling is started. 1. figure 25.2 shows the operation when the instru ction immediately preceding the trap address is that of 3 states or more of the execution cycle and the next instruction prefetch occurs in the state before the last 2 states. the address to be stacked is 0260. address bus interrupt request signal mov execution mov instruc- tion pre-fetch nop instruc- tion pre-fetch internal opera- tion data read start of exception handling immediately preceding instruction address 025e mov.b @er3+,r2l 0260 nop (er3 = h'0000) 0262 nop 0264 nop 025e 0260 0000 0262 * trap setting address the underlines address is the one to be actually stacked. note: in the figure above, the nop instruction is used as the typical example of instruction with execution cycle of 1 state. other instructions with the execution cycle of 1 state also apply (ex. mov.b, rs, rd). * figure 25.2 basic operations (1) section 25 address trap controller (atc) rev.2.00 jan. 15, 2007 page 535 of 1174 rej09b0329-0200 2. figure 25.3 shows the operation when the instru ction immediately preceding the trap address is that of 2 states or more of the execution cycle and the next instruction prefetch occurs in the second state from the last. the address to be stacked is 0268. address bus interrupt request signal mov execution nop execution start of exception handling immediately preceding instruction address 0266 mov.b r2l, @0000 0268 nop 026a nop 026c nop * 0266 026a 0268 0000 026c data read mov instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch notes: the underlined address is the one to be actually stacked. * trap setting address figure 25.3 basic operations (2) 3. figure 25.4 shows the operation when the instru ction immediately preceding the trap address is that of 1 state or 2 states or more and the prefet ch occurs in the last state. the address to be stacked is 025c. address bus interrupt request signal nop execu- tion nop execu- tion nop execu- tion start of exception handling immediately preceding instruction address 0256 nop 0258 nop 025a nop 025c nop 025e nop * 0256 025c 0258 025a 025e nop instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch notes: the underlined address is the one to be actually stacked. * trap setting address figure 25.4 basic operations (3) section 25 address trap controller (atc) rev.2.00 jan. 15, 2007 page 536 of 1174 rej09b0329-0200 25.3.2 enabling the address trap function becomes valid after executing one instruction following the setting of the enable bit of the address trap control register (atcr) to 1. 029c bset #0, @trcr * 029e mov.w r0, r1 02a0 mov.b r1l, r3h 02a2 nop 02a4 cmp.w r0, r1 02a6 nop after executing the mov instruction, the address trap interrupt does not arise, and the next instruction is executed. note: * trap setting address figure 25.5 enabling 25.3.3 bcc instruction 1. when the condition is satisfied by bcc instruction (8-bit displacement) if the trap address is the next instruction to the bcc instruction and the condition is satisfied by the bcc instruction and then branched, transition is made to the address trap interrupt after executing the instruction at the branch. the address to be stacked is 02a8. address bus interrupt request signal beq execu- tion cmp execu- tion 029c 02a8 029e 02a6 02aa 029c beq next:8 029e nop 02a0 nop 02a2 nop 02a4 nop 02a6 cmp.w r0, r1 02a8 nop (next = h'02a6) * start of exception handling beq instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch cmp instruc- tion pre-fetch notes: the underlined address is the one to be actually stacked. * trap setting address figure 25.6 when the condition satisfie d by bcc instruction (8-bit displacement) section 25 address trap controller (atc) rev.2.00 jan. 15, 2007 page 537 of 1174 rej09b0329-0200 2. when the condition is not satisfied by bcc instruction (8-bit displacement) if the trap address is the next instruction to the bcc instruction and the condition is not satisfied by the bcc instruction and thus it fails to branch, transition is made to the address trap interrupt after executing the trap address in struction and prefetching the next instruction. the address to be stacked is 02a2. address bus interrupt request signal 029e 02a2 02a0 02a8 02a4 029e beq next:8 02a0 nop 02a2 nop 02a4 nop 02a6 nop 02a8 cmp.w r0, r1 02aa nop (next = h'02a8) * beq execu- tion nop execu- tion start of exception handling beq instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch cmp instruc- tion pre-fetch next: notes: the underlined address is the one to be actually stacked. * trap setting address figure 25.7 when the condition not satisf ied by bcc instructio n (8-bit displacement) section 25 address trap controller (atc) rev.2.00 jan. 15, 2007 page 538 of 1174 rej09b0329-0200 3. when condition is not satisfied by bcc instruction (16- bit displacement) if the trap address is the next instruction to the bcc instruction and the condition is not satisfied by the bcc instruction and thus it fails to branch, transition is made to the address trap interrupt after executing the trap addr ess instruction (if the trap address instruction is that of 2 states or more. if the instruction is that of 1 state, after executing two instructions). the address to be stacked is 02c0. address bus interrupt request signal start of exception handling 02b8 02c0 02bc 02be 02c2 02ba 02b8 beq next:16 02bc nop 02be nop 02c0 nop 02c2 nop 02c4 nop (next = h'02c4) * beq execution nop execu- tion nop execu- tion data fetch internal opera- tion beq instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch next: notes: the underlined address is the one to be actually stacked. * trap setting address figure 25.8 when the condition not satisfie d by bcc instruction (16-bit displacement) section 25 address trap controller (atc) rev.2.00 jan. 15, 2007 page 539 of 1174 rej09b0329-0200 4. when the condition is not satisfied by bcc instruction (trap address at branch) when the trap address is at th e branch of the bcc instruction and the condition is not satisfied by the bcc instruction and thus it fails to branch, transition is made into the address trap interrupt after executing the next instruction (if the next instruction is that of 2 states or more. if the next instruction is that of 1 state, after executing two instructions). the address to be stacked is 0262. address bus interrupt request signal start of exception handling 025c 0262 0266 025e 0260 0264 025c beq next:8 025e nop 0260 nop 0262 nop 0264 nop 0266 cmp.w r0, r1 0268 nop (next = h'0266) beq execution nop execu- tion nop execu- tion * beq instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch cmp instruc- tion pre-fetch next: notes: the underlined address is the one to be actually stacked. * trap setting address figure 25.9 when the condition no t satisfied by bcc instruction (trap address at branch) section 25 address trap controller (atc) rev.2.00 jan. 15, 2007 page 540 of 1174 rej09b0329-0200 25.3.4 bsr instruction 1. bsr instruction (8-bit displacement) when the trap address is the next instruction to the bsr instruction and the addressing mode is an 8-bit displacement, transition is made to th e address trap interrupt after prefetching the instruction at the branch. the a ddress to be stacked is 02c2. address bus interrupt request signal bsr execution stack saving 0294 sp ? 4 02c2 0296 sp ? 2 02c4 0294 bsr @er0 0296 nop 0298 nop 02c2 mov.w r4, @out 02c4 nop : : (@er0 = h'02c2) * start of exception handling bsr instruc- tion pre-fetch nop instruc- tion pre-fetch mov instruc- tion pre-fetch notes: the underlined address is the one to be actually stacked. * trap setting address figure 25.10 bsr instru ction (8-bit displacement) section 25 address trap controller (atc) rev.2.00 jan. 15, 2007 page 541 of 1174 rej09b0329-0200 25.3.5 jsr instruction 1. jsr instruction (register indirect) when the trap address is the next instruction to the jsr instruction and the addressing mode is a register indirect, transition is made to the address trap interrupt after prefetching the instruction at the branch. the a ddress to be stacked is 02c8. address bus interrupt request signal jsrexecution stack saving start of exception handling 029a sp ? 4 02c8 029c sp ? 2 02ca 029a jsr @er0 029c nop 029e nop 02c8 mov.w r4, @out 02ce nop : : (@er0 = h'02c8) * jsr instruc- tion pre-fetch nop instruc- tion pre-fetch mov instruc- tion pre-fetch notes: the underlined address is the one to be actually stacked. * trap setting address figure 25.11 jsr instruction (register indirect) section 25 address trap controller (atc) rev.2.00 jan. 15, 2007 page 542 of 1174 rej09b0329-0200 2. jsr instruction (memory indirect) when the trap address is the next instruction to the jsr instruction and the addressing mode is memory indirect, transition is made to the address trap interrupt after prefetching the instruction at the branch. the a ddress to be stacked is 02ea. address bus interrupt request signal jsr execution stack saving start of exception handling 0294 sp ? 2 sp ? 4 02ea 006c 0296 006e 02ec 0294 jsr @@h'6c:8 0296 nop 0298 nop 02ea nop 02ec nop : : 006c h'02ea : : * data fetch jsr instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch notes: the underlined address is the one to be actually stacked. * trap setting address figure 25.12 jsr inst ruction (memory indirect) section 25 address trap controller (atc) rev.2.00 jan. 15, 2007 page 543 of 1174 rej09b0329-0200 25.3.6 jmp instruction 1. jmp instruction (register indirect) when the trap address is the next instruction to the jmp instruction and the addressing mode is a register indirect, transition is made to the address trap interrupt after prefetching the instruction at the branch. the a ddress to be stacked is 02aa. address bus interrupt request signal jmp execution mov.l execution data fetch start of exception handling 029a 02a8 02aa 02a4 029c 02a6 02ac 029a jmp @er0 029c nop 029e nop 02a0 nop 02a2 nop 02a4 mov.l #data, er1 02aa nop (@er0 = h'02a4) * jmp instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch mov instruc- tion pre-fetch notes: the underlined address is the one to be actually stacked. * trap setting address figure 25.13 jmp instruction (register indirect) 2. jmp instruction (memory indirect) when the trap address is the next instruction to the jmp instruction and the addressing mode is memory indirect, transition is made to the address trap interrupt after prefetching the instruction at the branch. the a ddress to be stacked is 02e4. section 25 address trap controller (atc) rev.2.00 jan. 15, 2007 page 544 of 1174 rej09b0329-0200 address bus interrupt request signal jmp execution start of exception handling 0294 006c 02e4 006c 0296 006e 02e6 0294 jmp @@h'6c:8 0296 nop 0298 nop 02e4 nop 02e6 nop : : 006c h'02e4 : : * data fetch internal opera- tion jmp instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch notes: the underlined address is the one to be actually stacked. * trap setting address figure 25.14 jmp inst ruction (memory indirect) 25.3.7 rts instruction when the trap address is the next instruction to the rts instruction, transition is made to the address trap interrupt after reading the ccr and pc from the stack and pref etching the instruction at the return location. the address to be stacked is 0298. address bus break interrupt request signal rts execution start of exception handling 02ac sp 0298 sp 02ae sp+2 029a stack saving 0296 bsr sub 0298 nop 029a nop 02ac rts (@er0 = h'02c8) 02ae nop * : : internal opera- tion rts instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch notes: the underlined address is the one to be actually stacked. * trap setting address figure 25.15 rts instruction section 25 address trap controller (atc) rev.2.00 jan. 15, 2007 page 545 of 1174 rej09b0329-0200 25.3.8 sleep instruction 1. sleep instruction 1 when the trap address is the sleep instruction and th e instruction execution cycle immediately preceding the sleep inst ruction is that of 2 states or more and prefetch does not occur in the last state, the s leep instruction is not executed and transition is made to the address trap interrupt without going into sleep mode. the address to be stacked is 0274. address bus interrupt request signal start of exception handling 0272 fff9 0274 sp ? 4 sp ? 2 0276 0272 mov.b r2l, @fff8 0274 sleep 0276 nop 0278 nop : : * data write mov execution sleep cancel mov instruc- tion pre-fetch nop instruc- tion pre-fetch sleep instruc- tion pre-fetch notes: the underlined address is the one to be actually stacked. * trap setting address figure 25.16 sleep instruction (1) section 25 address trap controller (atc) rev.2.00 jan. 15, 2007 page 546 of 1174 rej09b0329-0200 2. sleep instruction 2 when the trap address is the sleep instruction and th e instruction execution cycle immediately preceding the sleep inst ruction is that of 1 state 2 states or more and prefetch occurs in the last state, this puts in the sleep mode after ex ecution of the sleep instruction, and the sleep mode is cancelled by the address tr ap interrupt and transition is made to the exception handling. the address to be stacked is 0264. address bus interrupt request signal start of exception handling 0260 0262 sp ? 2 sp ? 4 0264 0260 nop 0262 sleep 0264 nop 0266 nop : : * nop execution sleep execution sleep mode nop instruc- tion pre-fetch sleep instruc- tion pre-fetch nop instruc- tion pre-fetch notes: the underlined address is the one to be actually stacked. * trap setting address figure 25.17 sleep instruction (2) section 25 address trap controller (atc) rev.2.00 jan. 15, 2007 page 547 of 1174 rej09b0329-0200 3. sleep instruction 3 when the trap address is the ne xt instruction to the sleep inst ruction, this puts in the sleep mode after execution of the sleep instructi on, and the sleep mode is cancelled by the address trap interrupt and transition is made to the exception handling. the address to be stacked is 0282. address bus interrupt request signal start of exception handling 0280 sp ? 2 sp ? 4 0282 027e nop 0280 sleep 0282 nop 0284 nop : : * sleep execution sleep mode sleep instruc- tion pre-fetch nop instruc- tion pre-fetch notes: the underlined address is the one to be actually stacked. * trap setting address figure 25.18 sleep instruction (3) section 25 address trap controller (atc) rev.2.00 jan. 15, 2007 page 548 of 1174 rej09b0329-0200 4. sleep instruction 4 (sta ndby or watch mode setting) when the trap address is the sleep instruction and the instru ction immediatel y preceding the sleep instruction is that of 1 state or 2 states or more and prefetch occurs in the last state, this puts in the standby (watch) mode after execution of the sleep instruction. after that, if the standby (watch) mode is cancelled by the nmi inte rrupt, transition is made to nmi interrupt following the ccr and pc (at the address of 0266) stack saving and vector reading. however, if the address trap interrupt arises before st arting execution of the nmi interrupt processing, transition is made to the address trap exception handling. the address to be stacked is the starting address of the nmi interrupt processing. address bus interrupt request signal address trap interruption 0262 0264 0266 sp ? 2 spca sp ? 2 0262 nop 0264 sleep 0266 nop * sleep execution nmi interrupt standby mode nop instruc- tion pre-fetch nop instruc- tion pre-fetch sleep instruc- tion pre-fetch note: * trap setting address figure 25.19 sleep instruction (4) (standby or watch mode setting) section 25 address trap controller (atc) rev.2.00 jan. 15, 2007 page 549 of 1174 rej09b0329-0200 5. sleep instruction 5 (sta ndby or watch mode setting) when the trap address is the next instruction to the sleep instruction, this puts in the standby (watch) mode after execution of the sleep instru ction. after that, if the standby (watch) mode is cancelled by the nmi interruption, transition is made to the nmi interrupt following the ccr and pc (at the address of 0266) stack saving and vector reading. however, if the address trap interrupt arises before starting execution of the nmi interrupt processing, transition is made to the address trap exception handling. th e address to be stacked is the starting address of the nmi interrupt processing. address bus interrupt request signal address trap interrupt 0280 0282 0284 sp ? 2 spca sp ? 2 0280 nop 0282 sleep 0284 nop * sleep execution nmi interruption standby mode nop instruc- tion pre-fetch sleep instruc- tion pre-fetch note: * trap setting address figure 25.20 sleep instruction (5) (standby or watch mode setting) 25.3.9 competing interrupt 1. general interrupt (interrupt other than nmi) when the atc interrupt request is made at the timing in (1) (a) against the general interrupt request, the interruption appears to take place in the atc at the timing earlier than usual, because higher priority is assigned to the at c interrupt processing (s imultaneous interrupt with the general interrupt has no effect on processing). the address to be stacked is 029e. for comparison, the case wh ere the trap address is set at 02a0 if no general interrupt request was made is shown in (2). the address to be stacked is 02a4. section 25 address trap controller (atc) rev.2.00 jan. 15, 2007 page 550 of 1174 rej09b0329-0200 address bus general interrupt request signal interrupt request signal mov execution data write data write start of general interrupt processing range of start of atc interrupt processing (1) 029c nop 0296 mov.b r2l, @port 029a nop 029e nop 02a0 nop 02a2 nop 02a4 nop 0296 port 029e sp ? 2 sp ? 4 vector vector 0298 nop execu- tion nop execu- tion mov execution nop execu- tion nop execu- tion nop execu- tion nop execu- tion nop execu- tion 029a 029c 02a0 address bus interrupt request signal data read data read start of atc interrupt processing set one of these to the trap address (2) 029c nop 0296 mov.b r2l, @port 029a nop 029e nop 02a0 nop trap address 02a2 nop 02a4 nop 0296 port 029e 0298 02a0 02a2 02a4 sp ? 2 029a 029c 02a6 (a) mov instruc- tion pre-fetch mov instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch address to be stacked figure 25.21 competing in terrupt (general interrupt) section 25 address trap controller (atc) rev.2.00 jan. 15, 2007 page 551 of 1174 rej09b0329-0200 2. in case of nmi when the nmi interruption request is made at the timing in (1) (a) against the atc interrupt request, the interrupt appears to take place in nmi at the timing earlier than usual, because higher priority is assigned to the nmi interrupt processing. the atc interrupt processing starts after fetching the instruction at the starting address of the nmi interrupt processing. the address to be stacked is 02e0 for the nmi and 340 for the atc. when the atc interrupt request is made at the timing in (2) (b) against the nmi interrupt request, the atc interrupt processing starts after fetching the instruction at the starting address of the nmi interrupt processing. the address to be stacked is 02e6 for the nmi and 0340 for the atc. section 25 address trap controller (atc) rev.2.00 jan. 15, 2007 page 552 of 1174 rej09b0329-0200 address bus nmi interrupt request signal atc interrupt request signal start of atc inter- rupt processing (1) 02e0 nop 02dc nop 02de nop 02e2 nop 02e4 nop 02e6 nop 02e8 nop 02dc sp ? 4 0340 sp ? 6 sp ? 8 vector vector vector vector 02de nmi vector read 02e0 0342 sp ? 2 02e2 (2) set one of these to the trap address (1) set to the trap address nmi interrupt processing start of atc interrupt processing address bus nmi interrupt request signal atc interrupt request signal start of atc interrupt processing (2) 02dc 02e2 02e4 sp ? 4 sp ? 2 0340 vector vector vector 02de 02e0 0342 02e6 02e8 (b) (a) nmi interrupt processing : : 0340 the starting address of nmi interrupt : : nop execu- tion nop execu- tion nop instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch nop instruc- tion pre-fetch figure 25.22 competing interrupt (in case of nmi) section 26 servo circuits rev.2.00 jan. 15, 2007 page 553 of 1174 rej09b0329-0200 section 26 servo circuits 26.1 overview 26.1.1 functions servo circuits for a video cassette recorder are included on-chip. the functions of the servo circuits can be divided into four groups, as listed in table 26.1. section 26 servo circuits rev.2.00 jan. 15, 2007 page 554 of 1174 rej09b0329-0200 table 26.1 servo circuit functions group function description ctl i/o amplifier gain variable input amplifier output amplifier with rewrite mode cfgduty compensation input duty accuracy: 50 2% (zero cross type comparator) dfg, dpg separation/overlap input overlap input available: three-level input method, dfg noise mask function reference signal generators v compensation, field detection, external signal sync, v sync in rec mode, ref30 signal output to outside hsw timing generator head-switching signals, fifo 20 stages compatible with dfg counter soft-reset four-head high-speed switching circuit for special playback chroma-rotary/head-amplifier switching output 12-bit pwm improved speed of carrier frequency frequency division circuit with cfg mask, no cfg for phase or ctl mask (1) input and output circuits sync detection circuit noise count, field discrimination, hsync compensation, hsync detection noise mask drum speed error detector lock detector function, pause at the counter overflow, r/w error latch register, limiter function drum phase error detector latch signal selectable, r/w error latch register capstan speed error detector lock detector function, pause at the counter overflow, r/w error latch register, limiter function capstan phase error detector r/w error latch register (2) error detectors x-value adjustment and tracking adjustment circuit (separate setting available) (3) phase and gain compensation digital filter computation circuit computations performed automatically by hardware output gain variable: 2 to 64 (exponents of 2) (partial write in z -1 (high-order 8 bits) available) additional v signal circuit valid in special playback (4) other circuits ctl circuit duty discrimination circuit, ctl head r/w control, compatible with wide aspect 26.1.2 block diagram figure 26.1 shows a block diagram of the servo circuits. section 26 servo circuits rev.2.00 jan. 15, 2007 page 555 of 1174 rej09b0329-0200 4-head special playback controller - + sv1(p30) excap(p81) ( ) sv2(p31) ( ) exctl(p82) ) + + + + + - + + - - ctl head ctl amp ctl head cfg cap pwm drm pwm dfg dpg(p87) videoff audioff vpulse h.amp sw(p84) c.rotary(p83) comp(p85) csync exttrg(p86) osch rec:on adtrig (hsw) ep pwm es es ep rec rec pb.asm ctlfb pb.ctl pb. asm (ntsc) dvctl gain control by re g ister settin g ref30,ref30x,cref, ctlmoni,dvcfg, dfg,dpg,dfg,etc internal si g nal monitor controller (pal) ref30x rec-ctl dutyi/o (duty deter- minator) (assemble recordin g ) dvcfg dvcfg2 gain up. xe:on vd rp0 to b/ (p60 to 67, p74 to 77) sync separator rec-ctl g enerator viss circuit noise det. a/d converter timer x1 timer l timer r an pins pwm x-value adjustment gain up. rp0 to b/ (p60 to 67, p74 to 77) ppg0 to 7/ (p70 to 77) ppg0 to 7/ (p70 to 77) ref30p(pb:30hz,rec:1/2vd) cref res system clock additional v pulse g enerator head-switch timin g g enerator drum system reference si g nal capstan system reference si g nal phase error detector phase error detector di g ital filter di g ital filter di g ital filter di g ital filter frequency divider frequency divider speed error detector speed error detector figure 26.1 block diagram of servo circuits section 26 servo circuits rev.2.00 jan. 15, 2007 page 556 of 1174 rej09b0329-0200 26.2 servo port 26.2.1 overview this lsi is equipped with seventeen pins dedicated to the servo circuit and twenty-nine pins multiplexed with general-purpose ports. it also ha s an input amplifier to amplify ctl signals, a ctl output amplifier, a ctl schmitt comparator, and a cfg zero cross type comparator. the ctl input amplifier allows gain adjustment by software. dfg and dpg signals, which control the drum, can be input as separate signals or an overlapped signal. sv1 and sv2 pins allow internal signals of the servo circuit to be output for monitoring. the signals to be output can be selected out of eight kinds of signals. see the description of servo monitor control register (svmcr) in section 26.2.5, register description. 26.2.2 block diagram 1. dfg and dpg input circuit the dfg and dpg input pins have on-chip schmit circuits. figure 26.2 shows the input circuit of dfg and dpg. dpg sw dfg dpg dfg dpg dpg sw res+lpm figure 26.2 input circuit of dfg and dpg section 26 servo circuits rev.2.00 jan. 15, 2007 page 557 of 1174 rej09b0329-0200 2. cfg input circuit the cfg input pin has an amplifier and a zero cross type comparator. figure 26.3 shows the input circuit of cfg. + - + - + - cfgcomp cfgcomp p250 ref m250 s r f/f o stp vref vref cfg bias cfg res+modulestop figure 26.3 cfg input circuit section 26 servo circuits rev.2.00 jan. 15, 2007 page 558 of 1174 rej09b0329-0200 3. ctl input circuit the ctl input pin has an amplifier. figure 26.4 shows the input circuit of ctl. - + + - ctlfb ctlsmt(i) ctlfb ctlref ctlbias ctlgr0 ctlgr3 to 1 ampshort (rec-ctl) pb-ctl(+) note: be sure to connect a capacitor between ctlamp (o) and ctlsmt (i) note pb-ctl(-) ampon (pb-ctl) - + ctlamp(o) ctl(+) ctl( - ) figure 26.4 ctl input circuit 26.2.3 pin configuration table 26.2 shows the pin configuration of the servo circuit. p30, p31, p6n, p7n, and p81 to p87 are general-purpose ports. as for p3, p6, p7, and p8, see section 10, i/o port. section 26 servo circuits rev.2.00 jan. 15, 2007 page 559 of 1174 rej09b0329-0200 table 26.2 pin configuration name abbrev. i/o function servo v cc pin sv cc input power source pin for servo circuit servo v ss pin sv ss input power source pin for servo circuit audio head switching pin audio ff output audio head switching signal output video head switching pin video ff output video head switching signal output capstan mix pin cappwm output 12-bit pwm square wave output drum mix pin drmpwm output 12-bit pwm square wave output additional v pulse pin vpulse output additional v signal output color rotary signal output pin p83/c.rotary i/o, output general-purpose port/control signal output port for processing color signals head amplifier switching pin p84/h.amp sw i/o, output general-purpose port/pre-amplifier output selection signal input compare signal input pin p85/comp i/o, input general-purpose port/pre-amplifier output result signal input ctl (+) i/o pin ctl (+) i/o ctl signal input/output ctl (-) i/o pin ctl (-) i/o ctl signal input/output ctl bias input pin ctlbias input ctl primary amplifier bias supply ctl amp (o) output pin ctlamp (o) output ctl amplifier output ctl smt (i) input pin ctlsmt (i) input ctl schmitt amplifier input ctl fb input pin ctlfb input ctl amplifier high-range characteristics control ctl ref output pin ctlref output ctl amplifier reference voltage output capstan fg amplifier input pin cfg input cfg signal amplifier input drum fg input pin dfg input dfg signal input drum pg input pin p87/dpg i/o, input general-purpose port/dpg signal input external ctl signal input pin p82/exctl i/o, input general-purpose port/external ctl signal input/ composite sync signal input pin csync input composite sync signal input external reference signal input pin p86/exttrg i/o, input general-purpose port/external reference signal input external capstan signal input pin p81/excap i/o, input general-purpose port/external capstan signal input servo monitor signal output pin 1 p30/sv1 i/o, output general-purpose port/servo monitor signal output servo monitor signal output pin 2 p31/sv2 i/o, output general-purpose port/servo monitor signal output ppg output pin p7n/ppgn i/o, output general-purpose port/ppg output rtp output pin p6n/rpn, p7n/rpn i/o, output general-purpose port/rtp output section 26 servo circuits rev.2.00 jan. 15, 2007 page 560 of 1174 rej09b0329-0200 26.2.4 register configuration table 26.3 shows the register configuration of the servo port section. table 26.3 register configuration name abbrev. r/w size initial value address servo port mode register spmr r/w byte h'5f h'd0a0 servo monitor control register svmcr r/w byte h'c0 h'd0a3 ctl gain control register ctlgr r/w byte h'c0 h'd0a4 26.2.5 register description servo port mode register (spmr) 0 1 1 1 ? 2 1 ? 3 1 4 1 ? 0 r/w 5 6 ? ? 7 ????? 0 r/w ctlstop ? ? cfgcomp 1 bit : initial value : r/w : spmr is an 8-bit read/write register that switches the cfg input system. it is initialized to h'5f by a reset or in stand-by mode. bit 7 ? ctlstop bit (ctlstop): controls whether the ctl circuit is operated or stopped. bit 7 ctlstop description 0 ctl circuit operates (initial value) 1 ctl circuit stops operation bit 6 ? reserved: cannot be modified and is always read as 1. section 26 servo circuits rev.2.00 jan. 15, 2007 page 561 of 1174 rej09b0329-0200 bit 5 ? cfg input system switching bit (cfgcomp) : selects whether the cfg input signal system is set to the zero cross type comparator system or digital signal input system. bit 5 cfgcomp description 0 cfg signal input system is set to the zero cross type comparator system. (initial value) 1 cfg signal input system is set to the digital signal input system. bits 4 to 0 ? reserved: cannot be modified and are always read as 1. servo monitor control register (svmcr) 0 0 1 0 2 0 3 0 4 0 5 6 7 ? ? ? ? svmcr4 svmcr3 svmcr2 svmcr1 svmcr0 1 1 r/w r/w r/w 0 svmcr5 r/w r/w r/w bit : initial value : r/w : svmcr is an 8-bit read/write register that selects the monitor signal output from the sv1 and sv2 pins when the p30/sv1 pin is used as the sv1 monitor output pin or when the p31/sv2 pin is used as the sv2 monitor output pin. it is initialized to h'c0 by a reset or in stand-by mode. bits 7 and 6 ? reserved: cannot be modified and are always read as 1. bits 5 to 3 ? sv2 pin servo monitor output control(svmcr5 to svmcr3): select the servo monitor signal output from the sv2 pin. bit 5 bit 4 bit 3 svmcr5 svmcr4 svmcr3 description 0 outputs ref30 signal to sv2 output pin. (initial value) 0 1 outputs capref30 signal to sv2 output pin. 0 outputs cref signal to sv2 output pin. 0 1 1 outputs ctlmoni signal to sv2 output pin. 0 outputs dvcfg signal to sv2 output pin. 0 1 outputs cfg signal to sv2 output pin. 0 outputs dfg signal to sv2 output pin. 1 1 1 outputs dpg signal to sv2 output pin. section 26 servo circuits rev.2.00 jan. 15, 2007 page 562 of 1174 rej09b0329-0200 bits 2 to 0 ? sv1 pin servo monitor output control (svmcr2 to svmcr0): select the servo monitor signal output from the sv1 pin. bit 2 bit 1 bit 0 svmcr2 svmcr1 svmcr0 description 0 outputs ref30 signal to sv1 output pin. (initial value) 0 1 outputs capref30 signal to sv1 output pin. 0 outputs cref signal to sv1 output pin. 0 1 1 outputs ctlmoni signal to sv1 output pin. 0 outputs dvcfg signal to sv1 output pin. 0 1 outputs cfg signal to sv1 output pin. 0 outputs dfg signal to sv1 output pin. 1 1 1 outputs dpg signal to sv1 output pin. ctl gain control register (ctlgr) 0 0 1 0 2 0 3 0 4 0 5 6 7 ? ? ? ? ctlfb ctlgr3 ctlgr2 ctlgr1 ctlgr0 1 1 r/w r/w r/w 0 ctle/a r/w r/w r/w bit : initial value : r/w : ctlgr is an 8-bit read/write register that turns on or off the ctlfb switch in the ctl amplifier circuit and specifying the ctl amplifier gain. it is initialized to h'c0 by a reset or in stand-by mode. bits 7 and 6 ? reserved: cannot be modified and are always read as 1. bit 5 ? ctl selection bit (ctle/ a ): controls whether the amplifier output or exctl is used as the ctlp signal supplie d to the ctl circuit. bit 5 ctle/ a description 0 amp output (initial value) 1 exctl section 26 servo circuits rev.2.00 jan. 15, 2007 page 563 of 1174 rej09b0329-0200 bit 4 ? sw bit of the feedback section of ctl amplifier (ctlfb): turns on or off the switch of the feedback sec tion to adjust the gain. see figure 26.4. bit 4 ctlfb description 0 turns off ctlfb sw (initial value) 1 turns on ctlfb sw bits 3 to 0 ? ctl amplifier gain setting bits (ctlgr3 to ctlgr0): set the output gain of the ctl amplifier. bit 3 bit 2 bit 1 bit 0 ctlgr3 ctlgr2 ctlgr1 ctlgr0 ctl output gain 0 34.0 db (initial value) 0 1 36.5 db 0 39.0 db 0 1 1 41.5 db 0 44.0 db 0 1 46.5 db 0 49.0 db 0 1 1 1 51.5 db 0 54.0 db 0 1 56.5 db 0 59.0 db 0 1 1 61.5 db 0 64.0 db 0 1 66.5 db * 0 69.0 db * 1 1 1 1 71.5 db * note: * with a setting of 65.0 db or more, the ctlamp is in a very sensitive status. when configuring the set board, take a countermeasure against noise around the control head signal input port. also, consider well the setting of the filter between the ctlamp and the ctlsmt. section 26 servo circuits rev.2.00 jan. 15, 2007 page 564 of 1174 rej09b0329-0200 26.2.6 dfg/dpg input signals dfg and dpg signals can be input either as separate signals or as an overlapped signal. when the latter is selected (pmr87 = 1), take care to control the input levels of dfg and dpg. figure 26.5 shows dfg/dpg input signals. dpg dpg schmitt level 3.45/3.55 v il /v ih dfg schmitt level 1.85/1.95 v il /v ih dfg (1) dpg/dfg separate input (pmr87 = 0) dpg schmitt level dfg/dpg (2) dpg/dfg overlapped input (pmr87 = 1) dfg schmitt level figure 26.5 dfg/dpg input signals section 26 servo circuits rev.2.00 jan. 15, 2007 page 565 of 1174 rej09b0329-0200 26.3 reference sign al generators 26.3.1 overview the reference signal generators consist of a re f30 signal generator and a cref signal generator and create the reference signals (ref30 and cref signals) used in phase comparison, etc. the ref30 signal is used to control the phase of the drum and capstan. the cref signal is used if ref30 signal cannot be used as the reference signal to control the phase of the capstan in rec mode. each signal generator consists of a 16-bit counter which uses the servo clock s/2 (or s/4) as its clock source, a reference period register, and a comparator. the value set in the reference period register shoul d be 1/2 of the desired reference signal period. 26.3.2 block diagram figure 26.6 shows the block diagram of ref30 signal generator. figure 26.7 shows that of cref signal generator. section 26 servo circuits rev.2.00 jan. 15, 2007 page 566 of 1174 rej09b0329-0200 s = fosc/2 s/2 s/4 dummy read external frequency signal (exttrg) field detection signal w w r/w w w ww pb rec pb , asm rec/pb v noise detection signal ref30 ref30p video ff vd match mask clear w r/w w internal bus r/w internal bus toggle rcs ref30 counter register (16 bits) od/ev vst fds veg edge detec- tion edge detec- tion vna cvs rex tbc reference period buffer 1 (16 bits) reference period register 1 (16 bits) comparator (16 bits) counter (16 bits) figure 26.6 ref30 signal generator section 26 servo circuits rev.2.00 jan. 15, 2007 page 567 of 1174 rej09b0329-0200 s/2 s/4 ww cref dvcfg2 pb(asm) rec match clear counter clear toggle edge detection crd w rcs reference period register 2 (16 bits) reference period buffer 2 (16 bits) comparator (16 bits) counter (16 bits) internal bus s r q dummy read s = fosc/2 figure 26.7 block diagram of cref signal generator 26.3.3 register configuration table 26.4 shows the register configura tion of the reference signal generators. table 26.4 register configuration name abbrev. r/w size initial value address reference period mode register rfm w byte h'00 h'd096 reference period register 1 rfd w word h'ffff h'd090 reference period register 2 crf w word h'ffff h'd092 ref30 counter register rfc r/w word h'0000 h'd094 reference period mode register 2 rfm2 r/w byte h'fe h'd097 section 26 servo circuits rev.2.00 jan. 15, 2007 page 568 of 1174 rej09b0329-0200 26.3.4 register description reference period mode register (rfm) 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 rex crd od/ev vst veg 0 w rcs w w w vna cvs bit : initial value : r/w : rfm is an 8-bit write-only register which determines the operational state of the reference signal generators. if a read is attempted, an undetermined value is read out. it is initialized to h'00 by a reset and in stand-by and module stop modes. rfm is accessible in byte units only. if accessed by a word, correct operation is not guaranteed. bit 7 ? clock source selection bit (rcs): selects the clock source supplied to the counter. ( s = fosc/2) bit 7 rcs description 0 s/2 (initial value) 1 s/4 bit 6 ? mode selection bit (vna): selects the mode for controlling transition to free-run operation when the ref30 signal is generated synchronously with the vd signal in rec mode: automatic mode which controls the transition by the v noise detection signal detected by the sync signal detection circuit, or manual mode which controls the transition by software. bit 6 vna description 0 manual mode (initial value) 1 automatic mode section 26 servo circuits rev.2.00 jan. 15, 2007 page 569 of 1174 rej09b0329-0200 bit 5 ? manual selection bit (cvs): selects whether the ref30 signal is generated synchronously with vd or it is operated in free-run state in the manual mode (vna = 0). (this selection is ignored in pb mode except in tbc mode.) bit 5 cvs description 0 synchronous with vd (initial value) 1 free-run operation bit 4 ? external signals sync selection bit (rex): selects whether the ref30 signal is generated synchronously with vd, in free-run state or synchronously with the external signal. (valid in both pb and rec modes.) bit 4 rex description 0 vd signal or free-run (initial value) 1 synchronous with external signal bit 3 ? dvcfg2 sync selection bit (crd): selects whether the reset timing in the cref signal generation is immediately after switching the mode or it is synchronous with the dvcfg2 signal immediately after the mode switching. bit 3 crd description 0 on switching the mode (initial value) 1 synchronous with dvcfg2 signal bit 2 ? odd/even edge switching selection bit (od/ev): selects whether the ref30p signal is generated by the rising edge (even) or falling edge (odd) of the field signal in rec mode. bit 2 od/ev description 0 generated at the rising edge of the field signal (initial value) 1 generated at the falling edge of the field signal section 26 servo circuits rev.2.00 jan. 15, 2007 page 570 of 1174 rej09b0329-0200 bit 1 ? video ff counter set (vst): selects whether the ref30 counter register value is set on or off by the video ff signal when the drum phase is in fix on in the pb mode. bit 1 vst description 0 counter set off by video ff signal (initial value) 1 counter set on by video ff signal bit 0 ? video ff edge selection bit (veg): selects the edge at which ref30 counter is set (vst = 1) by the video ff signal. bit 0 veg description 0 set at the rising edge of video ff signal (initial value) 1 set at the falling edge of video ff signal reference period register 1 (rfd) 15 1 ref15 w 14 1 ref14 w 13 1 ref13 w 12 1 ref12 w 11 1 ref11 w 10 1 ref10 w 9 1 ref9 w 8 1 ref8 w 7 1 ref7 w 6 1 ref6 w 5 1 ref5 w 4 1 ref4 w 3 1 ref3 w 2 1 ref2 w 1 1 ref1 w 0 1 ref0 w bit : initial value : r/w : the reference period register 1 (rfd) is a buffe r register which generates the reference signal (ref30) for playback, vd compensation for recording, and the reference signals for free-running. it is an 16-bit write-only register accessible in word units only. if a read is attempted, an undetermined value is read out. the value set in rfd should be 1/2 of the desire d reference signal period. care is required when vd is unstable, such as when the field is weak (synchronization with vd cannot be acquired if a value less than 1/2 is set in rec). when data is written in rfd, it is stored in the buffer once, and then fetched into rfd by a match signal of the comparator. (the data which generates the reference signal is updated by the match signal.) a forcible write, such as initial setting, etc., should be done by a dummy read of rfd. if a byte-write in rfd is attempted, correct operation is not guaranteed. rfd is initialized to h'ffff by a reset, and in stand-by and module stop modes. use bit 7 (asm) and bit 6 (rec/pb) in the ctl mode register (ctlm) in the ctl circuit to switch between record and playback modes. use bit 4 (cr/rf bit) in the capstan phase error detection control register (cpgcr) to switch between ref30 and cref for capstan phase control. section 26 servo circuits rev.2.00 jan. 15, 2007 page 571 of 1174 rej09b0329-0200 reference period register 2 (crf) 15 1 crf15 w 14 1 crf14 w 13 1 crf13 w 12 1 crf12 w 11 1 crf11 w 10 1 crf10 w 9 1 crf9 w 8 1 crf8 w 7 1 crf7 w 6 1 crf6 w 5 1 crf5 w 4 1 crf4 w 3 1 crf3 w 2 1 crf2 w 1 1 crf1 w 0 1 crf0 w bit : initial value : r/w : the reference period register 2 (crf) is an 16-bit write-only buffer register which generates the reference signals to control the capstan phase ( cref). crf is accessible in word units only. if a read is attempted, an undetermined value is read out. the value set in crf should be 1/2 of the desired reference signal period. when data is written in crf, it is stored in the buffer once, and then fetched into crf by a match signal of the comparator. (the data which generates the reference signal is updated by the match signal.) a forcible write, such as initial setting, etc., should be done by a dummy read of crf. if a byte-write in crf is attempted, correct ope ration is not guaranteed. crf is initialized to h'ffff by a reset and in stand-by and module stop modes. use bit 4 (cr/rf bit) in the capstan phase error detection control register (cpgcr) to switch between ref30 and cref for capstan phase control. see section 26.9, capstan phase error detector. ref30 counter register (rfc) 15 0 rfc15 14 0 rfc14 13 0 rfc13 12 0 rfc12 11 0 rfc11 10 0 rfc10 9 0 rfc9 8 0 rfc8 7 0 rfc7 6 0 rfc6 5 0 rfc5 4 0 rfc4 3 0 rfc3 2 0 rfc2 1 0 rfc1 0 0 rfc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit : initial value : r/w : the ref30 counter register (rfc) is a register which determines the initial value of the free-run counter when it generates ref30 signals in playback. when data is written in rfc, its value is written in the counter by a match signal of the comparator. if the bit 1 (vst) of rfm is set to 1, the counter is set by the video ff signal when th e drum phase is in fix on. the counter setting by the video ff signal should be done by setting b it 1 (vst) and bit 0 (veg) of the rfm. do not set the rfc to a value greater than 1/2 of the reference period register 1 (rfd) value. rfc is a read/write register. if a read is attemp ted, the value of the counter is read out. if a byte- access is attempted, correct operation is not guar anteed. rfc is initialized to h'0000 by a reset and in stand-by and module stop modes. section 26 servo circuits rev.2.00 jan. 15, 2007 page 572 of 1174 rej09b0329-0200 reference period mode register 2 (rfm2) 0 0 1 1 2 1 3 1 4 1 5 6 7 ? ? ? ? ? ? tbc ? ? ? ? ? ? r/w fds 1 11 r/w bit : initial value : r/w : rem2 is an 8-bit read/write register which determines the operational state of the reference signal generators. it is initialized to h'fe by a reset and in stand-by and module stop modes. rfm2 is a byte access- only register; if accessed by a word, co rrect operation is not guaranteed. bit 7 ? tbc selection bit (tbc): selects whether the reference signal in pb mode is generated by the vd signal or by the free-run counter. bit 7 tbc description 0 generated by the vd signal 1 generated by the free-run counter (initial value) bits 6 to 1 ? reserved: cannot be modified and are always read as 1. bit 0 ? field selection bit (fds): determines whether selection between odd or even is made for the field signal when pb mode was switched over to rec mode, or these signals are synchronized with vd signals within a phase error of 90 immediately after the switching over. bit 0 fds description 0 generated by the vd signal of odd or even selected (initial value) 1 generated by the vd signal within mode transition phase error of 90 section 26 servo circuits rev.2.00 jan. 15, 2007 page 573 of 1174 rej09b0329-0200 26.3.5 operation ? operation of ref30 signal generator the ref30 signal generator generates the referen ce signals required to control the phase of the drum and capstan. to generate the ref30 signal, set the 1/2 the refe rence period to the reference period register 1 (rfd) corresponding to the 50 percent duty cycle. in playback mode, the ref30 signal is generated by free-running the ref30 signal genera tor. the generator has the external signal synchronization function, and if the bit 4 (rex) of the reference period mode register (rfm) is set to 1, it generates the ref30 signal from the external signal (exttgr). in record mode, the reference signal is genera ted from the vd signal generated in the sync detector. any vd drop-out caused by weak field intensity, etc., is compensated by a value set in rfd. to cope with the vd noises, the generator automatically masks the vd for a period about 75% of the rfd setting after ref30 signal was changed due to vd. in record mode, the generation of the reference signal either by vd or free-run operation can be controlled automatically using the v noise detection signal de tected in the sync signal detection circuit or manually by software. select which is used by setting bit 6 (vna) or 5 (cvs) of rfm. the phase of the toggle output of the ref30 signal is cleared to l level when the mode shifts from pb to rec (asm). also the frame servo function can be set, allowing for control of the phase of ref30 signals with the field signal detected in the sync signal detection circuit. use bit 2 (od/ev) of rfm for such control. see the description of ctl mode register (ctlm) in section 26.13.5, register description, as for switching over between pb, asm and rec. ? operation of the mask circuit the ref30 signal generator has a toggle mask circuit and a counter mask (counter set signal mask) circuit built-in. each mask circuit masks irregular vd signals which may occur when the vd signal is unstable because of weak field intensity, etc., in record mode. the toggle mask and counter mask circuits mask the vd automatically for about 75% of double the period set in the reference period register 1 (rfd) after vd signal was detected (see figure 26.9). if a vd signal dropped out and v was compensated, the toggle mask circuit begins masking, but the counter mask circuit does not begin masking for about 25% of the period. if vd signal was detected during such a period, the circuit does masking for about 75% of the period after the vd detection. if not detected, it does masking for about 75% of the period after v was compensated (see figures 26.10 and 26.11). section 26 servo circuits rev.2.00 jan. 15, 2007 page 574 of 1174 rej09b0329-0200 ? timing of the ref30 signal generation figures 26.8 to 26.12 show the timing of the generation of ref30 and ref30p signals. counter set counter set counter set value set in reference period register 1 (rfd) counter value set in ref30 counter register (rfc) ref30 ref30p figure 26.8 ref30 signals in playback mode section 26 servo circuits rev.2.00 jan. 15, 2007 page 575 of 1174 rej09b0329-0200 sampling sampling sampling value set in reference period register 1 (rfd) selected vd (od/ev = 0) counter mask (clear signal mask) counter value set in ref30 counter register (rfc) ref30 vd toggle mask field signal ref30p hsw drum phase counter t about 75% masking period masking period figure 26.9 generati on of reference signal in r ecord mode (normal operation) section 26 servo circuits rev.2.00 jan. 15, 2007 page 576 of 1174 rej09b0329-0200 sampling cleared cleared cleared drop-out of v value set in reference period register 1 (rfd) selected vd (od/ev = 0) counter mask (clear signal mask) counter value set in ref30 counter register (rfc) ref30 vd toggle mask field signal ref30p hsw drum phase counter sampling t sampling about 75% about 75% about 75% about 75% about 25% masking period masking period figure 26.10 generation of the reference signal when in rec (v dropped out) section 26 servo circuits rev.2.00 jan. 15, 2007 page 577 of 1174 rej09b0329-0200 sampling cleared cleared cleared dislocation of v value set in reference period register 1 (rfd) selected vd (od/ev = 0) counter mask (clear signal mask) counter value set in ref30 counter register (rfc) ref30 vd toggle mask field signal ref30p hsw drum phase counter sampling t sampling about 75% about 75% about 75% about 75% masking period masking period figure 26.11 generation of the reference signal when in rec (v dislocated) section 26 servo circuits rev.2.00 jan. 15, 2007 page 578 of 1174 rej09b0329-0200 cleared cleared reset value set in reference period register 1 (rfd) counter value set in ref30 counter register (rfc) external sync signal ref30 ref30p figure 26.12 generation of ref30 signal by the external sync signal ? cref signal generator the cref signal generator generates the cref signal which is the reference signal to control the phase of capstan. to generate the cref signal, set the 1/2 the reference period to the reference period register 2 (crf). if the set value matches the counter value, a toggle waveform is generated corresponding to the 50 percent duty cycle, and a one-shot pulse is output at each rising edge of the waveform. the counter of cref signal ge nerator is initialized to h'0000 and the phase of the toggle is cleared to l level when the mode shifts from pb (asm) to rec. the timing of clearing is selectable between immediately after the transition from pb (asm) to rec and the timing of dvcfg2 after the transition. use bit 3 (crd) of the reference period mode register (rfm) for this selection. in the capstan phase error detection circuit, either ref30 signal or cref signal can be selected for the reference signal. use either of them according to the use of the system. use the cref signal to control the phase of the capstan at a period which is different from the period used to control the phase of the drum. for the switching between ref30 and cref in the capstan phase control, see the description of capstan phase error detection control register (cpgcr) in section 26.9.4, register description. section 26 servo circuits rev.2.00 jan. 15, 2007 page 579 of 1174 rej09b0329-0200 ? timing chart of the cref signal generation figures 26.13 to 26.15 show the generation of cref signal. cleared cleared cleared value set in reference period register 2 (crf) counter toggle signal cref figure 26.13 generation of cref signal section 26 servo circuits rev.2.00 jan. 15, 2007 page 580 of 1174 rej09b0329-0200 cleared cleared cleared value set in reference period register 2 (crf) counter period set in crf rec pb(asm) toggle signal rec/pb cref figure 26.14 cref signal when pb is switched to rec (when crd bit = 0) section 26 servo circuits rev.2.00 jan. 15, 2007 page 581 of 1174 rej09b0329-0200 cleared cleared cleared value set in reference period register 2 (crf) counter period set in crf toggle signal rec/pb cref dvcfg2 rec pb(asm) figure 26.15 cref signal when pb is switched to rec (when crd bit = 1) section 26 servo circuits rev.2.00 jan. 15, 2007 page 582 of 1174 rej09b0329-0200 figures 26.16 and 26.17 show ref30 (ref30p) when pb is switched to rec. cleared cleared cleared cleared cleared value set in reference period register 1 (rfd) selected vd * (od/ev = 0) note: * in the field discrimination mode counter mask (clear signal mask) counter value set in ref30 counter register (rfc) ref30 vd (except in pb) rec(asm) pb toggle mask field signal rec/pb ref30p about 75% masking period masking period figure 26.16 generation of the reference signal when pb is switched to rec (1) section 26 servo circuits rev.2.00 jan. 15, 2007 page 583 of 1174 rej09b0329-0200 value set in reference period register 1 (rfd) selected vd (od/ev = 0) counter mask (clear signal mask) counter value set in ref30 counter register (rfc) ref30 vd (except in pb) rec(asm) pb toggle mask field signal rec/pb ref30p about 50% cleared cleared cleared cleared masking period masking period figure 26.17 generation of the reference signal when pb is switched to rec (2) section 26 servo circuits rev.2.00 jan. 15, 2007 page 584 of 1174 rej09b0329-0200 figures 26.18 to 26.21 show ref30 (ref30p) when pb is switched to rec (where fds bit = 1). cleared cleared cleared value set in reference period register 1 (rfd) fds bit = 1 counter mask (clear signal mask) counter value set in ref30 counter register (rfc) ref30 vd (except in pb) rec(asm) pb toggle mask rec/pb ref30p masking period masking period figure 26.18 generation of the reference signal when pb is switched to rec where rfd bit is 1 (1) section 26 servo circuits rev.2.00 jan. 15, 2007 page 585 of 1174 rej09b0329-0200 value set in reference period register 1 (rfd) fds bit = 1 counter mask (clear signal mask) counter value set in ref30 counter register (rfc) ref30 vd (except in pb) rec(asm) pb toggle mask rec/pb ref30p masking period masking period 25% 25% 25% figure 26.19 generation of the reference signal when pb is switched to rec where rfd bit is 1 (when vd signal is not detected) (2) section 26 servo circuits rev.2.00 jan. 15, 2007 page 586 of 1174 rej09b0329-0200 cleared cleared value set in reference period register 1 (rfd) fds bit = 1 counter mask (clear signal mask) counter value set in ref30 counter register (rfc) ref30 vd (except in pb) rec(asm) pb toggle mask rec/pb ref30p masking period masking period 25% max. figure 26.20 generation of the reference signal when pb is switched to rec where rfd bit is 1 (3) section 26 servo circuits rev.2.00 jan. 15, 2007 page 587 of 1174 rej09b0329-0200 cleared cleared value set in reference period register 1 (rfd) fds bit = 1 counter mask (clear signal mask) counter value set in ref30 counter register (rfc) ref30 vd (except in pb) rec(asm) pb toggle mask rec/pb ref30p masking period masking period 25% max. figure 26.21 generation of the reference signal when pb is switched to rec where rfd bit is 1 (4) section 26 servo circuits rev.2.00 jan. 15, 2007 page 588 of 1174 rej09b0329-0200 26.4 hsw (head-switch) timing generator 26.4.1 overview the hsw timing generator consists of a 5-bit dfg counter, a 16-bit timer counter, a matching circuit, and two 31-bit 10-stage fifos. the 5-bit counter counts the dfg pulses following a dpg pulse. each of them determines the timing to reset the 16-bit timer counter for each field. the 16-bit timer counter is a timer clocked by a s/4 clock source, and can be used as a programmable pattern generator (ppg) as well as a free-running counter (frc). if used as a free-running counter, it is cleared by overflow of the prescaler unit. accordingly, two frcs operate synchronously. the matching circuit compares the timing data in the most significant 16 bits of fifo with the 16-bit timer counter, and controls the output of the pattern data set in the least significant 15 bits of fifo. 26.4.2 block diagram figure 26.22 shows a block diagram of the hsw timing generator. section 26 servo circuits rev.2.00 jan. 15, 2007 page 589 of 1174 rej09b0329-0200 r w w r/w r/w w r/w r/w strig irrhsw2 isel2 audioff videoff hsw nhsw mlevel vpulse adtrg irrhsw1 r vd pb w r/w r/w cleared cleared clk w r , ncdfg frcovf dpg cksl vff/nff internal bus w fpdra fpdrb ftpra ftprb w isel1 ofg fifo output pattern register 1 fifo output pattern register 2 sofg lop r/w r/w r r w w clra,b ovwa,b empa,b fla,b r/w r/w hsm2 hsm1 hslp edg hsw loop stage number setting register internal bus fgr20ff frt cclr edge detector control circuit fifo 1 (31 bits 10 stages) 15 bits p77 to 70 (ppg output) fifo timing pattern register 1 fifo timing pattern register 2 16 bits fifo2 (31 bits 10 stages) 15 bits 16 bits fifo output selector & output buffer 15 bits 16 bits dfcrb dfcra dfcra hsm2 hsm2 capture hsm2 dfcra dfcra dfg reference register 1 comparator (5 bits) comparator (5 bits) dfg reference register 2 dfctr 5-bit counter compare circuit (16 bits) ftctr (16 bits) 16-bit timer counter s/4 s/8 figure 26.22 block diagram of the hsw timing generator section 26 servo circuits rev.2.00 jan. 15, 2007 page 590 of 1174 rej09b0329-0200 26.4.3 hsw timing generator configuration the hsw timing generator is composed of the elements shown in table 26.5. table 26.5 configuration of the hsw timing generator element function hsw mode register 1 (hsm1) confirmation/determination of this circuits' operating status hsw mode register 2 (hsm2) confirmation/determination of this circuits' operating status hsw loop stage number setting register (hslp) setting of number of loop stages in loop mode fifo output pattern register 1 (fpdra) output pattern register of fifo1 fifo output pattern register 2 (fpdrb) output pattern register of fifo2 fifo timing pattern register 1 (ftpra) output timing register of fifo1 fifo timing pattern register 2 (ftprb) output timing register of fifo2 dfg reference register 1 (dfcra) setting of reference dfg edge for fifo1 dfg reference register 2 (dfcrb) setting of reference dfg edge for fifo2 fifo timer capture register (ftctr) capture register of timer counter dfg reference count register (dfctr) dfg edge count fifo control circuit fifo status control dfg count compare circuit ( 2) detection of match between dfcr and dfg counters 16-bit timer counter 16-bit free-run timer counter 31-bit x 20 stage fifo first in first out data buffer 31-bit fifo data buffer data storing buffer for the first stage of fifo 16-bit compare circuit detection of match between timer counter and fifo data buffer fpdra and fpdrb are intermediate buffers ; an ftpra and ftprb write results in simultaneous writing of all 31 bits to the fifo. the fifo has two 31-bit x 10-stage data buffers; its operating status is controlled by hsm1 and hsm2. data is stored in the 31-bit data buffer. the values of ftpra/ftprb and the timer counter are compared, and if they match, the 15-bit pattern data is output to each function. audioff, videoff, and ppg (p70 to p77) are outputs from the corresponding pins, adtrg is the a/d converter hardware start signal, vpulse and mlevel signals are the signals for generating the additional v pulses, and hsw and nhsw signals are the same as videoff signals used for the phase control of the drum. the 16-bit timer counter is initialized by the overflow of the prescaler unit in the free-run mode (frt bit of hsm2 = 1), or by section 26 servo circuits rev.2.00 jan. 15, 2007 page 591 of 1174 rej09b0329-0200 a signal indicating a match between dfcra/dfcrb and the 5-bit dfg counter in dfg reference mode. 26.4.4 register configuration table 26.6 shows the register configuration of the hsw timing generator. table 26.6 register configuration name abbrev. r/w size initial value address hsw mode register 1 hsm1 r/w byte h'30 h'd060 hsw mode register 2 hsm2 r/w byte h'00 h'd061 hsw loop stage number setting register hslp r/w byte undetermined h'd062 fifo output pattern register 1 fpdra w word undetermined h'd064 fifo timing pattern register 1 * ftpra w word undetermined h'd066 fifo output pattern register 2 fpdrb w word undetermined h'd068 fifo timing pattern register 2 ftprb w word h'ffff h'd06a dfg reference register 1 * dfcra w byte undetermined h'd06c dfg reference register 2 dfcrb w byte undetermined h'd06d fifo timer capture register * ftctr r word h'0000 h'd066 dfg reference count register * dfctr r byte h'e0 h'd06c note: * ftpra and ftctr, as well as dfcra and dfctr, are allocated to the same addresses. 26.4.5 register description hsw mode register 1 (hsm1) 0 0 1 0 r/w 2 0 r/(w) * 3 0 4 1 r 1 r 5 6 0 7 empa ovwb ovwa clrb clra 0 r flb r/w r/(w) * r fla empb bit : initial value : r/w : note: * only 0 can be written hsm1 is an 8-bit register which confirms and determines the operational state of the hsw timing generator. section 26 servo circuits rev.2.00 jan. 15, 2007 page 592 of 1174 rej09b0329-0200 bits 7 to 4 are read-only bits, and write is disabl ed. all the other bits accep t both read and write. it is initialized to h'30 by a reset or in stand-by mode. bit 7 ? fifo2 full flag (flb): when the flb bit is 1, it indicates that the fifo2 is full of the timing pattern data and the output pattern data. if a write is attempted in this state, the write operation becomes invalid, an interrupt is generated, the ovwb flag (bit 3) is set to 1, and the write data is lost. wait until space becomes available in the fifo2, then write again. bit 7 flb description 0 fifo2 is not full, and can accept data input. (initial value) 1 fifo2 is full of data. bit 6 ? fifo1 full flag (fla): when the fla bit is 1, it indicates that the fifo1 is full of the timing pattern data and the output pattern data. if a write is attempted in this state, the write operation becomes invalid, an interrupt is generated, the ovwa flag (bit 2) is set to 1, and the write data is lost. wait until space becomes available in the fifo1, then write again. bit 6 fla description 0 fifo1 is not full, and can accept data input. (initial value) 1 fifo1 is full of data. bit 5 ? fifo2 empty flag (empb): indicates that fifo2 has no data, or that all the data has been output in single mode. bit 5 empb description 0 fifo2 contains data. 1 fifo2 contains no data. (initial value) section 26 servo circuits rev.2.00 jan. 15, 2007 page 593 of 1174 rej09b0329-0200 bit 4 ? fifo1 empty flag (empa): indicates that fifo1 has no data, or that all the data has been output in single mode. bit 4 empa description 0 fifo1 contains data. 1 fifo1 contains no data. (initial value) bit 3 ? fifo2 overwrite flag (ovwb): if a write is attempted when the fifo2 is full of the timing pattern data and the output pattern data (f lb bit = 1), the write operation becomes invalid, an interrupt is generated, the ovwb flag is set to 1, and the write data is lost. wait until space becomes available in the fifo2, then write again. write 0 to clear the ovwb flag, becau se it is not cleared automatically. bit 3 ovwb description 0 normal operation. (initial value) 1 indicates that a write in fifo2 was attempted when fifo2 was full of data. clear this flag by writing 0 to this bit. bit 2 ? fifo1 overwrite flag (ovwa): if a write is attempted when the fifo1 is full of the timing pattern data and the output pattern data (f la bit = 1), the write operation becomes invalid, an interrupt is generated, the ovwa flag is set to 1, and the write data is lost. wait until space becomes available in the fifo1, then write again. write 0 to clear the ovwa flag, becau se it is not cleared automatically. bit 2 ovwa description 0 normal operation. (initial value) 1 indicates that a write in fifo1 was attempted when fifo1 was full. clear this flag by writing 0 to this bit. section 26 servo circuits rev.2.00 jan. 15, 2007 page 594 of 1174 rej09b0329-0200 bit 1 ? fifo2 pointer clear (clrb): clears the fifo2 write position pointer. after 1 is written, the bit immediately reverts to 0. writing 0 in this bit has no effect. bit 1 clrb description 0 normal operation. (initial value) 1 clears the fifo2 pointer. bit 0 ? fifo1 pointer clear (clra): clears the fifo1 write position pointer. after 1 is written, the bit immediately reverts to 0. writing 0 in this bit has no effect. bit 0 clra description 0 normal operation (initial value) 1 clears the fifo1 pointer hsw mode register 2 (hsm2) 0 0 1 0 r 2 0 r/w 3 0 4 0 r/w 0 r/w 5 6 0 7 edg isel1 sofg ofg vff/nff 0 r/w frt w r/w r fgr2off lop bit : initial value : r/w : hsm2 is an 8-bit register which confirms and determines the operational state of the hsw timing generator. bit 1 is a read-only bit, and write is disabled. bit 0 is a write-only bit, and if a read is attempted, an undetermined value is read out. a ll the other bits accept both read and write. it is initialized to h'00 by a reset or in stand-by mode. bit 7 ? free-run bit (frt): selects whether the matching timing is determined by the dpg counter and timer, or by the frc. bit 7 frt description 0 5-bit dfg counter + 16-bit timer counter (initial value) 1 16-bit frc section 26 servo circuits rev.2.00 jan. 15, 2007 page 595 of 1174 rej09b0329-0200 bit 6 ? frg2 clear stop bit (fgr2off): disables clearing of the co unter by the dfg register 2. the fifo group, including both fifo1 and fifo2, is available. bit 6 fgr2off description 0 enables clearing of the16-bit timer counter by dfg register 2 (initial value) 1 disables clearing of the16-bit timer counter by dfg register 2 bit 5 ? mode selection bit (lop): selects the output mode of fifo. if the loop mode is selected, lob3 to lob0 bits and loa3 to loa0 bits become valid. if the lop bit is modified, the pointer which counts the writing position of fifo is cleared . in this case, the last output data is kept. bit 5 lop description 0 single mode (initial value) 1 loop mode bit 4 ? dfg edge selection bit (edg): selects the edge by which to count dfg pulses. bit 4 edg description 0 counts by the rising edge of dfg (initial value) 1 counts by the falling edge of dfg bit 3 ? interrupt selection bit (isel1): selects the interrupt source. (irrhsw1) bit 3 isel1 description 0 generates an interrupt request by the rising edge of the strig signal of fifo (initial value) 1 generates an interrupt request by the matching signal of fifo section 26 servo circuits rev.2.00 jan. 15, 2007 page 596 of 1174 rej09b0329-0200 bit 2 ? fifo output group selection bit (sofg): selects whether 20 stages of fifo1 + fifo2 or only 10 stages of fifo1 are used. if 20-stage output mode is used in single mode, data must be written to fifo1 and fifo2. monitor the output fifo group flag (ofg) and control data writing by software. all the data of fifo1 is output, then all the data of fifo2 is output. these steps are repeated. if 10-stage output mode is used, the data of fifo2 is not reflected. modifying the sofg bit from 0 to 1, then again to 0 initializes the control signal of the fifo output stage to the fifo1 side. bit 2 sofg description 0 20-stage output of fifo1 + fifo2 (initial value) 1 10-stage output of fifo1 only bit 1 ? output fifo group flag (ofg): indicates the fifo group which is outputting. bit 1 ofg description 0 pattern is being output by fifo1 (initial value) 1 pattern is being output by fifo2 bit 0 ? output switching bit between videoff and narrowff (vff/nff): switches the signal output from the videoff pin. bit 0 vff/nff description 0 videoff output (initial value) 1 narrowff output section 26 servo circuits rev.2.00 jan. 15, 2007 page 597 of 1174 rej09b0329-0200 hsw loop stage number setting register (hslp) 0 * 1 * r/w 2 * r/w 3 * 4 * r/w 5 * 6 * 7 r/w r/w r/w lob1 r/w lob2 * r/w lob3 lob0 loa3 loa2 loa1 loa0 bit : initial value : r/w : hslp is an 8-bit read/write register that sets the number of the loop stages when the hsw timing generator is in loop mode. it is valid when bit 5 (lop) of hsm2 is 1. bits 7 to 4 set the number of fifo2 stages. bits 3 to 0 set the number of fifo1 stages. it is not initialized by a reset or in stand-by or module stop mode; accordingly be sure to set the number of the stages when the loop mode is used. section 26 servo circuits rev.2.00 jan. 15, 2007 page 598 of 1174 rej09b0329-0200 bits 7 to 4 ? fifo2 stage number setting bits (lob3 to lob0): set the number of fifo2 stages in loop mode. they are valid only when the loop mode is set (lop bit of hsm2 is 1). hsm2 hslp bit 5 bit 7 bit 6 bit 5 bit 4 lop lob3 lob2 lob1 lob0 description 0 * * * * single mode (initial value) 0 only 0th stage of fifo2 is output 0 1 0th and 1st stages of fifo2 are output 0 0th to 2nd stages of fifo2 are output 0 1 1 0th to 3rd stages of fifo2 are output 0 0th to 4th stages of fifo2 are output 0 1 0th to 5th stages of fifo2 are output 0 0th to 6th stages of fifo2 are output 0 1 1 1 0th to 7th stages of fifo2 are output 0 0th to 8th stages of fifo2 are output 1 1 0 0 1 0th to 9th stages of fifo2 are output 0 1 1 0 0 1 0 1 1 1 setting prohibited legend: * don't care. section 26 servo circuits rev.2.00 jan. 15, 2007 page 599 of 1174 rej09b0329-0200 bits 3 to 0 ? fifo1 stage number setting bits (loa3 to loa0): set the number of fifo1 stages in loop mode. they are valid only when the loop mode is set (lop bit of hsm2 is 1). hsm2 hslp bit 5 bit 3 bit 2 bit 1 bit 0 lop loa3 loa2 loa1 loa0 description 0 * * * * single mode (initial value) 0 only 0th stage of fifo1 is output 0 1 0th and 1st stages of fifo1 are output 0 0th to 2nd stages of fifo1 are output 0 1 1 0th to 3rd stages of fifo1 are output 0 0th to 4th stages of fifo1 are output 0 1 0th to 5th stages of fifo1 are output 0 0th to 6th stages of fifo1 are output 0 1 1 1 0th to 7th stages of fifo1 are output 0 0th to 8th stages of fifo1 are output 1 1 0 0 1 0th to 9th stages of fifo1 are output 0 1 1 0 0 1 0 1 1 1 setting prohibited legend: * don?t care. section 26 servo circuits rev.2.00 jan. 15, 2007 page 600 of 1174 rej09b0329-0200 fifo output pattern register 1 (fpdra) 8 * 9 * w 10 * w 11 * 12 * w * w 13 14 * 15 ? ? narrowffa vffa affa vpulsea mlevela 1 w w w adtrga striga 0 * 1 * w 2 * w 3 * 4 * w * w 5 6 * 7 ppga4 ppga3 ppga2 ppga1 ppga0 * w ppga7 w w w ppga6 ppga5 bit : initial value : r/w : bit : initial value : r/w : note : * undefined fpdra is a buffer register for the fifo1 output pattern register. the output pattern data written in fpdra is written at the same time to the position of the fifo1 pointed by the buffer pointer. be sure to write the output pattern data in fpdra before writing it in ftpra. fpdra is an 16-bit write-only register. only a word access is valid. if a byte access is attempted, correct operation is not guaranteed. no read is valid. if a read is attempted, an undetermined value is read out. it is not initialized by a reset, or in stand-by or module stop mode; accordingly be sure to write data before use. bit 15 ? reserved: cannot be read or modified. bit 14 ? a/d trigger a bit (adtrga): indicates a hardware trigger signal for the a/d converter. bit 13 ? s-triga bit (striga): indicates a signal that generates an interrupt. when the strigb is selected by the isel, modifying this bit from 0 to 1 generates an interrupt. bit 12 ? narrowffa bit (narrowffa): controls the narrow video head. bit 11 ? videoffa bit (vffa): controls the video head. bit 10 ? audioffa bit (affa): controls the audio head. bit 9 ? vpulsea bit (vpulsea): used for generating an additional v signal. for details, refer to section 26.12, additional v signal generator. bit 8 ? mlevela bit (mlevela): used for generating an additional v signal. for details, refer to section 26.12, additional v signal generator. bits 7 to 0 ? ppg output signal a bits (ppga7 to ppga0): used for outputting a timing control signal from port 7 (ppg). section 26 servo circuits rev.2.00 jan. 15, 2007 page 601 of 1174 rej09b0329-0200 fifo output pattern register 2 (fpdrb) 8 * 9 * w 10 * w 11 * 12 * w * w 13 14 * 15 ? ? narrowffb vffb affb vpulseb mlevelb 1 w w w adtrgb strigb 0 * 1 * w 2 * w 3 * 4 * w * w 5 6 * 7 ppgb4 ppgb3 ppgb2 ppgb1 ppgb0 * w ppgb7 w w w ppgb6 ppgb5 bit : initial value : r/w : bit : initial value : r/w : note : * undefined fpdrb is a buffer register for the fifo2 output pattern register. the output pattern data written in fpdrb is written at the same time to the position of the fifo2 pointed by the buffer pointer. be sure to write the output pattern data in fpdrb before writing it in ftprb. fpdrb is an 16-bit write-only regi ster. only a word access is valid . if a byte access is attempted, correct operation is not guaranteed. no read is valid. if a read is attempted, an undetermined value is read out. it is not initialized by a reset, or in stand-by or module stop mode; accordingly be sure to write data before use. bit 15 ? reserved: cannot be read or modified. bit 14 ? a/d trigger b bit (adtrgb): indicates a hardware trigger signal for the a/d converter. bit 13 ? s-trigb bit (strigb): indicates a signal that generates an interrupt. when the strigb is selected by the isel, modifying this bit from 0 to 1 generates an interrupt. bit 12 ? narrowffb bit (narrowffb): controls the narrow video head. bit 11 ? videoffb bit (vffb): controls the video head. bit 10 ? audioffb bit (affb): controls the audio head. bit 9 ? vpulseb bit (vpulseb): used for generating an additional v signal. for details, refer to section 26.12, additional v signal generator. bit 8 ? mlevelb bit (mlevelb): used for generating an additional v signal. for details, refer to section 26.12, additional v signal generator. bits 7 to 0 ? ppg output signal b bits (ppgb7 to ppgb0): used for outputting a timing control signal from port 7 (ppg). section 26 servo circuits rev.2.00 jan. 15, 2007 page 602 of 1174 rej09b0329-0200 fifo timing pattern register 1 (ftpra) 0 * 1 * w 2 * w 3 * 4 * w * w 5 6 * 7 ftpra4 ftpra3 ftpra2 ftpra1 ftpra0 * w ftpra7 w w w ftpra6 ftpra5 bit : initial value : r/w : 8 * 9 * w 10 * w 11 * 12 * w * w 13 14 * 15 ftpra12 ftpra11 ftpra10 ftpra9 ftpra8 * w ftpra15 w w w ftpra14 ftpra13 bit : initial value : r/w : note : * undefined ftpra is a register to write the timing pattern data of fifo1. the timing data written in fpdra is written at the same time to the position of the fifo1 pointed by the buffer pointer together with the buffer data of fpdra. ftpra is an 16-bit write-only regi ster. only a word access is valid . if a byte access is attempted, correct operation is not guaranteed. it is not initialized by a reset or in stand-by or module stop mode; accordingly be sure to write data before use. note: the same address is assigned to the ftpra and the fifo timer capture register (ftctr). accordingly, the value of ftctr is read out if a read is attempted. fifo timing pattern register 2 (ftprb) 8 * 9 * w 10 * w 11 * 12 * w * w 13 14 * 15 ftprb12 ftprb11 ftprb10 ftprb9 ftprb8 * w ftprb15 w w w ftprb14 ftprb13 bit : initial value : r/w : 0 * 1 * w 2 * w 3 * 4 * w * w 5 6 * 7 ftprb4 ftprb3 ftprb2 ftprb1 ftprb0 * w ftprb7 w w w ftprb6 ftprb5 bit : initial value : r/w : note : * undefined ftprb is a register to write the timing pattern data of fifo2. the timing data written in fpdrb is written at the same time to the position of the fifo2 pointed by the buffer pointer together with the buffer data of fpdrb. ftprb is an 16-bit write-only re gister. only a word access is va lid. if a byte access is attempted, correct operation is not guaranteed. if a read is attempted, an undetermined value is read out. it is not initialized by a reset or in stand-by or module stop mode; accordingly be sure to write data before use. section 26 servo circuits rev.2.00 jan. 15, 2007 page 603 of 1174 rej09b0329-0200 dfg reference register 1 (dfcra) 0 * 1 * w 2 * w 3 * 4 * w 0 w 5 6 0 7 dfcra4 dfcra3 dfcra2 dfcra1 dfcra0 0 w isel2 w w w cclr cksl bit : initial value : r/w : note : * undefined dfcra is a register which determines the operation of the hsw timing generator as well as the starting point of the timing of fifo1. dfcra is an 8-bit write-only register. it is not initialized by a reset or in stand-by or module stop mode; accordingly be sure to write data before use. note: the same address is assigned to the df cra and the dfg reference counter register (dfctr). accordingly, the value of dfctr is read out in the low-order five bits if a read is attempted. bit 7 ? interrupt selection bit (isel2): selects the interrupt source. (irrhsw2) bit 7 isel2 description 0 generates an interrupt request by the clear signal of the 16-bit timer counter (initial value) 1 generates an interrupt request by the vd signal in pb mode bit 6 ? dfg counter clear bit (cclr): forcibly clears the 5-bit dfg counter by software. after 1 is written, the bit immediately reverts to 0. writing 0 in this bit has no effect. bit 6 cclr description 0 normal operation (initial value) 1 clears the 5-bit dfg counter section 26 servo circuits rev.2.00 jan. 15, 2007 page 604 of 1174 rej09b0329-0200 bit 5 ? 16-bit timer counter clock so urce selection bit (cksl): selects the clock source of the 16-bit timer counter. bit 5 cksl description 0 s/4 (initial value) 1 s/8 bits 4 to 0 ? fifo1 output timing setting bits (dfcra4 to dfcra0): determines the starting point of the timing of fifo1. the initial value is undetermined. be sure to set a value after a reset or stand-by. it is valid only if bit 7 (frt bit) of hsm2 is 0. dfg reference register 2 (dfcrb) 0 * 1 * w 2 * w 3 * 4 * w 5 6 1 7 ? ? ? ? ? ? dfcrb4 dfcrb3 dfcrb2 dfcrb1 dfcrb0 w w 11 bit : initial value : r/w : note : * undefined dfcrb is a register which determines the starting point of the timing of fifo2. dfcrb is an 8-bit write-only register. if a read is attempted, an undetermined value is read out. bits 7 to 5 are reserved; they cannot be modified an d are always read as 1. it is not initialized by a reset or in stand-by or module stop mode; accord ingly be sure to write data before use. bits 4 to 0 ? fifo2 output timing setting bits (dfcrb4 to dfcrb0): sets the starting point of the timing of fifo2. the value after reset or after stand-by mode is entered is undetermined; be sure to write data before use. it is valid only if bit 7 (frt bit) of hsm2 is 0. section 26 servo circuits rev.2.00 jan. 15, 2007 page 605 of 1174 rej09b0329-0200 fifo timer capture register (ftctr) 8 0 9 0 r 10 0 r 11 0 12 0 r 0 r 13 14 0 15 ftctr12 ftctr11 ftctr10 ftctr9 ftctr8 0 r ftctr15 r r r ftctr14 ftctr13 bit : initial value : r/w : 0 0 1 0 r 2 0 r 3 0 4 0 r 0 r 5 6 0 7 ftctr4 ftctr3 ftctr2 ftctr1 ftctr0 0 r ftctr7 r r r ftctr6 ftctr5 bit : initial value : r/w : ftcrt is a register to display the count of the 16-bit timer counter. ftcrt is an 16-bit read-only register. it captures the counter value when the vd signal is detected in pb mode. only a word access is accepted. if a byte access is attempted, correct operation is not guaranteed. it is initialized to h'0000 by a reset or in stand-by mode. note: the same address is assigned to the ftctr and the fifo timing pattern register 1 (ftpra). accordingly, if a write is attempted, the value is written in ftpra. dfg reference count register (dfctr) 0 0 1 0 r 2 0 r 3 0 4 0 r 5 6 1 7 ? ? ? ? ? ? dfctr4 dfctr3 dfctr2 dfctr1 dfctr0 r r 11 bit : initial value : r/w : dfctr is a register to count dfg pulses. dfctr is an 8-bit read-only register. bits 7 to 5 are reserved; they cannot be modified and are always read as 1. it is initialized to h'e0 by a reset or in stand-by mode. note: the same address is assigned to the dfctr and the dfg reference register 1 (dfcra). accordingly, if a write is attempted, the value is written in dfcra. bits 4 to 0?dfg pulse count bits (dfctr4 to dfctr0): these bits count dfg pulses. section 26 servo circuits rev.2.00 jan. 15, 2007 page 606 of 1174 rej09b0329-0200 26.4.6 operation 5-bit dfg counter: the 5-bit dfg counter increments the count at the dfg edges selected by the edg bit of hsw mode register 2. the dfg counter is cleared by a dpg rising edge, or by writing to the cclr bit of the dfg reference register 1. 16-bit timer counter: the 16-bit timer counter can operate in dfg reference mode or in free- running mode. ? dfg reference mode the timer counter operates by referencing the dfg signal. when the 5-bit dfg counter value matches the value specified in the dfg reference register 1 or 2, the 16-bit timer counter is initialized; this is the start point of the fifo output timing. in dfg reference mode, the start point specifying method can be selected by the fgr2off bit of the hsw mode register 2: one way is to specify both fifo1 and fifo2 by only one register (dfg reference register 1), and the other is to specify fifo1 and fifo2 by dfg reference registers 1 and 2, respectively. when only the dfg reference register 1 is used, the continuous values must be set to fifo1 and fifo2 as the timing patters. ? free-running mode the timer counter operates in a ssociation with the prescaler un it. when the 18-bit free-running counter in the prescaler unit overflows, the 16-bit timer counter in the hsw timing generator is initialized; this is the start point of the fifo output timing. compare circuit: the compare circuit compares the 16-bit timer counter value with the fifo timing pattern, and when they match, the compare circuit generates a trigger signal for outputting the next-stage fifo data. fifo: the fifo generates a head switch signal for vcr and patterns for servo control. data is set to fifo by using the fifo timing pattern registers 1 and 2, and fifo output pattern registers 1 and 2. the fifo operates in single mode and loop mode. in these two modes, the number of output stages can be selected by the fifo output group selection bit: 20-stage output using both fifo1 and fifo2 or 10-stage output using only fifo1. ? single mode the output pattern data is output when the timing pattern matches the counter value. the data, once output, is lost, and the internal pointer is decrementd by 1. after the last data is output, the fifo stops operation until data is written again. when 20-stage output is used, writing in fifo1 and fifo2 must be controlled by software. section 26 servo circuits rev.2.00 jan. 15, 2007 page 607 of 1174 rej09b0329-0200 ? loop mode the data output cycle is repeated from stage 0 to the final stage selected in the hsw loop number setting register. as in single mode, the output pattern data is output when the timing pattern matches the counter value. in loop mode, the fifo data is retained. data in each fifo group can be modified in loop mode. the fifo group currently outputting data can be checked by the ofg bit of the hsw mode register 2; after checking the outputting fifo group, clear the fifo group which is not outputting data, then write new data to it. writing new data must be completed before the fifo group starts operation. the fifo cannot be modified partially because the write pointer is outside the loop stages. figures 26.23 and 26.24 show examples of the timing waveform and operation of the hsw timing generator. section 26 servo circuits rev.2.00 jan. 15, 2007 page 608 of 1174 rej09b0329-0200 dpg 01 ta1 ta2 tb1 ta3 ta1 234567891011 01 2 v.ff a.ff clear a clear b example of setting: dfcra = h'02, dfcrb = h'08, hslp = h'21, dfg falling edge dfg figure 26.23 example of timing waveform of hsw (for 12 dfg pulses) section 26 servo circuits rev.2.00 jan. 15, 2007 page 609 of 1174 rej09b0329-0200 output pattern data s/4 w w ftprb fifo2 tb0 pb9 tb5 pb4 tb4 pb3 tb3 pb2 tb2 pb1 tb1 pb0 w w fpdra output select buffer output data buffer comparator ftpra fifo1 ta0 pa9 ta5 pa4 ta4 pa3 ta3 pa2 ta2 pa1 ta1 pa0 internal bus fpdrb timer counter figure 26.24 example of operati on of the hsw timing generator section 26 servo circuits rev.2.00 jan. 15, 2007 page 610 of 1174 rej09b0329-0200 ? example of operation in single mode (20 stages of fifo used) 1. set to single mode (lop = 0) 2. write the output pattern data (pa0) to fpdra. 3. write the output timing (t a1 ) to ftpra. t a1 is written in fifo1 together with pa0. this initializes the output pattern data to pa0. 4. repeat the steps in the same way, until pa1, pa2, etc., are set. 5. write the output pattern data (pb0) to fpdrb. 6. write the output timing (t b1 ) to ftprb. t b1 is written in fifo2 together with pb0. this initializes the output pattern data to pb0. 7. repeat these steps in the same way, until pb1, pb2, etc., are set. by step 3, the pattern data of pa0 is output. if t a1 matches with the timer counter, the pattern data of pa1 is output. if t a2 matches with the timer counter, the pattern data of pa2 is output. . . . after this sequence is repeated and all the pattern data set in fifo1 is output, the pattern data of fifo2 is output. after the pattern data is output, the pointer is decremented by 1. care is required, however, because matching of t a0 is not detected until data is written in fifo2. matching of t b0 also is not detected until data is written in fifo1 again. section 26 servo circuits rev.2.00 jan. 15, 2007 page 611 of 1174 rej09b0329-0200 ? example of the operation in loop mode mode 1. set the number of loop stages in hslp register (e.g. hslp = h'44) 2. write the output pattern data (pa0) to fpdra. 3. write the output timing (t a1 ) to ftpra. t a1 is written in fifo1 together with pa0. this initializes the output pattern data to pa0. 4. repeat the steps in the same way, until pa1, pa2, etc., are set. 5. write the output pattern data (pb0) to fpdrb. 6. write the output timing (t b1 ) to ftprb. t b1 is written in fifo2 together with pb0. this initializes the output pattern data to pb0. 7. repeat the steps in the same way, until pb1, pb2, etc., are set. by step 3, the pattern data pa0 is output. if t a1 matches the timer counter, the pattern data pa1 is output. if t a2 matches the timer counter, the pattern data pa2 is output. . . . if t a4 matches the timer counter, the pattern data pa4 is output. if t a5 matches the timer counter, the pattern data pb0 is output. if t b1 matches the timer counter, the pattern data pb1 is output. . . . if t b4 matches the timer counter, the pattern data pb4 is output. if t b5 matches the timer counter, the pattern data pa0 is output. . . . section 26 servo circuits rev.2.00 jan. 15, 2007 page 612 of 1174 rej09b0329-0200 26.4.7 interrupts the hsw timing generator generates interrupts under the following conditions. 1. irrhsw1 occurs when pattern data is written (ovwa, ovwb = 1) while fifo is full (full). 2. irrhsw1 occurs when matching is detected while the strig bit of fifo is 1. 3. irrhsw1 occurs when the values of the 16-bit timer counter and 16-bit timing pattern register match. 4. irrhsw2 occurs when the 16 -bit timer counter is cleared. 5. irrhsw2 occurs when a vd signal (capture signa l of the timer capture re gister) is received in pb mode. condition 2 or 3, as well as 4 or 5, are selected by isel1 and isel2. section 26 servo circuits rev.2.00 jan. 15, 2007 page 613 of 1174 rej09b0329-0200 26.4.8 cautions ? when both the 5-bit dfg counter and 16-bit timer counter are operating, the latter is not cleared if input of dpg and dfg signals is stopped. this leads to free-running of the 16-bit timer counter, and periodical detection of matching by the 16-bit timer counter. in such a case, the period of the output from the hsw timing generator is independent from dpg or dfg. ? specify the mode setting bit (lop) of the hsw mode register 2 (hsm2) immediately before writing the fifo data. ? input the rising edge of dpg and dfg count edge at different timings. if they are input at the same timing, counting up dfg and clearing the 5-bit dfg counter occur simultaneously. in this case, the latter will take precedence. this leads to the dfg counter lag by 1. figure 26.25 shows the input timing of dpg and dfg. ? if stop of the drum system is required when fifo output is being used in the 20-stage output mode, modify the sofg bit of hsm2 register from 0 to 1, then again to 0 by software, and be sure to initialize the fifo output stage to the fifo1 side. also clear and rewrite the data of fifo1 and fifo2. dpg i tp fg | > (1 state) tp fg dfg note: when the 5-bit dfg counter increments count at the rising edge of dfg figure 26.25 input timing of dpg and dfg section 26 servo circuits rev.2.00 jan. 15, 2007 page 614 of 1174 rej09b0329-0200 26.5 high-speed switching circuit for four-head special playback 26.5.1 overview this high-speed switching circuit generates a color rotary signal (c.rotary) and head-amplifier switching signal (h.amp sw) for use in four-head special playback. a pre-amplifier output comparison result signal is input from the comp pin. the signal output to the c.rotary pin is a chroma signal processing control signal. the signal output at the h.amp sw pin is a pre-amplifier output select signal. to reduce the width of noise bars, the c.rotary and h.amp sw signals are synchronized to the horizontal sync signal (osch). osch is made by adding supplemented h, which has been separated from csync signal in the sync signal detector circuit. for more details of osch, see section 26.15, sync signal detector. if the vcr system does not require this circuit, c.rotary, h.amp sw, and comp pins can be used as the i/o port. section 26 servo circuits rev.2.00 jan. 15, 2007 page 615 of 1174 rej09b0329-0200 26.5.2 block diagram figure 26.26 shows the block diagram of this circuit. w w synchronization control chcr w chcr rtp0 h.amp sw c.rotary osch (synchronization) comp narrowff videoff w chcr internal bus internal bus hah crh w chcr sig3 to 0 hswpol v/n decoding circuit figure 26.26 high-speed switching circuit for four-hea d special playback 26.5.3 pin configuration table 26.7 summarizes the pin configuration of the high-speed switching circuit for four-head special playback. if this circuit is not used, the pins can be used as i/o port. see section 26.2, servo port. table 26.7 pin configuration namea abbrev. i/o function compare input pin comp input input of pre-amplifier output result signal color rotary signal output pin c.rotary output output of chroma processing control signal head amplifier switch pin h.amp sw output output of pre-amplifier output select signal section 26 servo circuits rev.2.00 jan. 15, 2007 page 616 of 1174 rej09b0329-0200 26.5.4 register description register configuration table 26.8 shows the register configuration of the high-speed switching circuit for four-head special playback. table 26.8 register configuration name abbrev. r/w size initial value address special playback control register chcr w byte h'00 h'd06e special playback control register (chcr) 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 hah sig3 sig2 sig1 sig0 0 w v/n w w w hswpol crh bit : initial value : r/w : chcr is an 8-bit write-only register. it cannot be read. it is initialized to h'00 by a reset, or in standby or module stop mode. bits 7 ? hsw signal select bit (v/n): selects the hsw signal to be used at special playback. bit 7 v/n description 0 video ff signal output (initial value) 1 narrow ff signal output bit 6 ? comp polarity select bit (hswpol): selects the polarity of the comp signal. bit 6 hswpol description 0 positive (initial value) 1 negative section 26 servo circuits rev.2.00 jan. 15, 2007 page 617 of 1174 rej09b0329-0200 bit 5 ? c.rotary synchronization control bit (crh): synchronizes c.rotary signal with the osch signal. bit 5 crh description 0 synchronous (initial value) 1 asynchronous bit 4 ? h.ampsw synchronization control bit (hah): synchronizes h.ampsw signal with the osch signal. bit 4 hah description 0 synchronous (initial value) 1 asynchronous bits 3 to 0 ? signal control (sig3 to sig0): these bits, combin ed with the state of the comp input pin, control the outputs at the c.rotary and h.ampsw pins. bit 3 bit 2 bit 1 bit 0 output pins sig3 sig2 sig1 sig0 c.rotary h.amp sw 0 * * l l (initial value) 0 hsw l 0 1 hsw h 0 l hsw 0 1 1 1 h hsw 0 hsw ex-or comp comp 0 1 hsw ex-nor comp comp 0 hsw e-or rtp0 rtp0 1 1 1 * hsw ex-nor rtp0 rtp0 legend: * don?t care. section 26 servo circuits rev.2.00 jan. 15, 2007 page 618 of 1174 rej09b0329-0200 26.6 drum speed error detector 26.6.1 overview drum speed error control holds the drum at a constant revolution speed, by measuring the period of the dfg signal. a digital counter detects the speed error against a preset value. the speed error data is processed and added to phase error data in a digital filter. this filter controls a pulse-width modulated (pwm) output, which controls the revolution speed and phase of the drum. the dfg input signal is reshaped into a square wave by a reshaping circuit, and sent to the speed error detector as the dfg signal. the speed error detector uses the system cloc k to measure the period of the dfg signal, and detects the error against a preset data value. th e preset data is the value that results from measuring the dfg signal period with the clock signal when the drum motor is running at the correct speed. the error detector operates by latching a counter value when it detects an edge of the dfg signal. the latched count provides 16 bits of speed error data for the digital filter to operate on. the digital filter processes and adds the speed error data to phase error data from the drum phase control system, then sends the result to the pwm as drum error data. 26.6.2 block diagram figure 26.27 shows a block diagram of the drum speed error detector. section 26 servo circuits rev.2.00 jan. 15, 2007 page 619 of 1174 rej09b0329-0200 w w r udf ovf lock 2 up clear latch preset dfvcr dfrlor dfvcr dfpr dfvcr dfvcr dfvcr dfucr fgcr dfer dfrvcr error data (16 bits) to dfu addfgn ncdfg dfrudr internal bus w r/w internal bus r/w w r/w r/w r/w r/w (r)/w lock 1 up s r f/f q s r f/f dfrcs1,0 df-r/unr lock counter (2 bits) q s r f/f q lock range detector lock range data 1 (16 bits) dpcnt error data limiter control circuit dfefon dfess drf edge detector , error data (16 bits) counter (16 bits) dfovf irrdrm2 irrdrm1 to drockon dfu preset data (16 bits) lock range data 2 (16 bits) dfcs1,0 s s/2 s/4 s/8 figure 26.27 block diagram of the drum speed error detector section 26 servo circuits rev.2.00 jan. 15, 2007 page 620 of 1174 rej09b0329-0200 26.6.3 register configuration table 26.9 shows the register configuration of the drum speed error detector. table 26.9 register configuration name abbrev. r/w size initial value address specified dfg speed preset data register dfpr w word h'0000 h'd030 dfg speed error data register dfer r/w word h'0000 h'd032 dfg lock upper data register dfrudr w word h'7fff h'd034 dfg lock lower data register dfrldr w word h'8000 h'd036 drum speed error detection control register dfvcr r/w byte h'00 h'd038 section 26 servo circuits rev.2.00 jan. 15, 2007 page 621 of 1174 rej09b0329-0200 26.6.4 register description specified dfg speed preset data register (dfpr) 8 0 9 0 w 10 0 w 11 0 12 0 w 0 w 13 14 0 15 dfpr12 dfpr11 dfpr10 dfpr9 dfpr8 0 w dfpr15 w w w dfpr14 dfpr13 bit : initial value : r/w : 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 dfpr4 dfpr3 dfpr2 dfpr1 dfpr0 0 w dfpr7 w w w dfpr6 dfpr5 bit : initial value : r/w : the dfg speed preset data is set in dfpr. when da ta is written, the 16-bit preset data is sent to the preset circuit. the preset data can be calculated from the following equation by using h'8000* as the reference value. s/n specified dfg speed preset data = h'8000 ? ( ? 2) dfg frequency s: servo clock frequency (fosc/2) in hz dfg frequency: in hz constant 2 is the presetting interval (see figure 26.28). s/n clock source of the selected counter dfpr is a 16-bit write-only register. only a wo rd access is valid. if a byte access is attempted, correct operation is not guaranteed. dfpr cannot be read. if a read is attempted, an undetermined value is read. dfpr is initialized to h'0000 by a reset, and in standby mode and module stop mode. note: * the preset data value is calculated so that the counter will reach h'8000 when the error is zero. when the counter value is latched as error data in the dfg speed error data register (dfer), however, it is converted to a value referenced to h'0000. section 26 servo circuits rev.2.00 jan. 15, 2007 page 622 of 1174 rej09b0329-0200 dfg speed error data register (dfer) 8 0 9 0 r * /w 10 0 r * /w 11 0 12 0 r * /w 0 r * /w 13 14 0 15 dfer12 dfer11 dfer10 dfer9 dfer8 0 r * /w dfer15 r * /w r * /w r * /w dfer14 dfer13 bit : initial value : r/w : note: * note that only detected error data can be read. 0 0 1 0 r * /w 2 0 r * /w 3 0 4 0 r * /w 0 r * /w 5 6 0 7 dfer4 dfer3 dfer2 dfer1 dfer0 0 r * /w dfer7 r * /w r * /w r * /w dfer6 dfer5 bit : initial value : r/w : dfer is a 16-bit read/write register that stores 16-bit dfg speed error data. when the drum motor speed is correct, the data latched in dfer is h'0000. negative data will be latched if the speed is faster than the specified speed, and positive data if the speed is slower than the specified speed. the dfer value is sent to the digital filter either automatically or by software. only a word access is valid. if a byte access is a ttempted, correct operation is not guaranteed. dfer is initialized to h'0000 by a reset, and in standby mode and module stop mode. refer to the note specified dfg sp eed preset data register (dfpr) in section 26.6.4, register description. dfg lock upper data register (dfrudr) 8 1 9 1 w 10 1 w 11 1 12 1 w 1 w 13 14 1 15 dfrudr 12 dfrudr 11 dfrudr 10 dfrudr 9 dfrudr 8 0 w dfrudr 15 w w w dfrudr 14 dfrudr 13 bit : initial value : r/w : 0 1 1 1 w 2 1 w 3 1 4 1 w 1 w 5 6 1 7 dfrudr 4 dfrudr 3 dfrudr 2 dfrudr 1 dfrudr 0 1 w dfrudr 7 w w w dfrudr 6 dfrudr 5 bit : initial value : r/w : dfrudr is a 16-bit write-only register used to set the lock range on the upper side when drum speed lock is detected, and to set the limit value on the upper side when limiter function is in use. set a signed data to dfrudr (bit 15 is a sign-setting bit). when lock is being detected, if the drum speed is detected within the lock range, the lock counter which has been set by dfrcs 1 and 0 bits of dfvcr register decrements the count. if the set value of dfrcs 1 and 0 matches the number of times of occurrence of locking, the computation of the digital filter in the drum phase system can be controlled automatically. also, if the dfg speed error data exceeds the dfrudr value within the limiter function is in use, the dfrudr value can be used as the data for computation by the digital filter. only a word access is valid. if a byte access is atte mpted, correct operation is not guaranteed. no section 26 servo circuits rev.2.00 jan. 15, 2007 page 623 of 1174 rej09b0329-0200 read is valid. if a read is attempted, an undetermin ed value is read out. it is initialized to h'7fff by a reset, or in stand-by or module-stop mode. dfg lock lower data register (dfrldr) 8 0 9 0 w 10 0 w 11 0 12 0 w 0 w 13 14 0 15 dfrldr 12 dfrldr 11 dfrldr 10 dfrldr 9 dfrldr 8 1 w dfrldr 15 w w w dfrldr 14 dfrldr 13 bit : initial value : r/w : 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 dfrldr 4 dfrldr 3 dfrldr 2 dfrldr 1 dfrldr 0 0 w dfrldr 7 w w w dfrldr 6 dfrldr 5 bit : initial value : r/w : dfrldr is a 16-bit write-only register used to set the lock range on the lower side when drum speed lock is detected, and to set the limit value on lower side when limiter function is in use. set a signed data to dfrldr (bit 15 is a sign-setting bit). when lock is being detected, if the drum speed is detected within the lock range, the lock counter which has been set by dfrcs 1 and 0 bits of dfvcr register decrements the count. if the set value of dfrcs 1 and 0 matches the number of times of occurrence of locking, the computation of the digital filter in the drum phase system can be controlled automatically. also, if the dfg speed error data is under the dfrldr value when the limiter function is in use, the dfrldr value can be used as the data for computation by the digital filter. only a word access is valid. if a byte access is atte mpted, correct operation is not guaranteed. no read is valid. if a read is attempted, an undetermin ed value is read out. it is initialized to h'8000 by a reset, or in stand-by or module-stop mode. drum speed error detectio n control register (dfvcr) 0 0 1 0 (r) * 2 /w 2 0 r/w 3 0 4 0 r/w 0 r/(w) * 1 5 6 0 7 dfrfon df-r/unr dpcnt dfrcs1 dfrcs0 0 r/w dfcs1 (r) * 2 /w r r/w dfcs0 dfovf notes: bit : initial value : r/w : 1. only 0 can be written. 2. if read-accessed, the counter value is read out. dfvcr is an 8-bit read/write register that controls the operation of drum speed error detection. bit 3 accepts only read, and bit 5 accepts only read an d 0 write. it is initialized to h'00 by a reset, or in stand-by or module-stop mode. section 26 servo circuits rev.2.00 jan. 15, 2007 page 624 of 1174 rej09b0329-0200 bits 7 and 6 ? clock source selection bits (dfcs1, dfcs0): dfcs1 and dfcs0 select the clock to be supplied to the counter. ( s = fosc/2) bit 7 bit 6 dfcs1 dfcs0 description 0 s (initial value) 0 1 s/2 1 0 s/4 1 s/8 bit 5 ? counter overflow flag (dfovf): dfovf flag indicates the overflow of the 16-bit timer counter. it is cleared by writing 0. write 0 af ter reading 1. setting has the highest priority in this flag. if a flag set and 0 write occurs simultaneously, the latter is invalid. bit 5 dfovf description 0 normal state. (initial value) 1 indicates that overflow has occurred in the counter. bit 4 ? error data limit function selection bit (dfrfon): enables the error data limit function. (limit values are the values set in the lock range data registers (dfrudr and dfrldr)). bit 4 dfrfon description 0 disables limit function. (initial value) 1 enables limit function. bit 3 ? drum lock flag (df-r/unr): sets a flag if an underflow occurred in the drum lock counter. bit 3 df-r/unr description 0 indicates that the drum speed system is not locked. (initial value) 1 indicates that the drum speed system is locked. section 26 servo circuits rev.2.00 jan. 15, 2007 page 625 of 1174 rej09b0329-0200 bit 2 ? drum phase system filter computation automatic start bit (dpcnt): enables the filter computation of the phase system if an underflow occurred in the drum lock counter. bit 2 dpcnt description 0 disables the filter computation by dete ction of the drum lock. (initial value) 1 enables the filter computation of the pha se system when drum lock is detected. bits 1 and 0 ? drum lock counter setting bits (dfrcs1, dfrcs0): set the number of times to detect drum locks (which means the number of times dfg is detected in the range set by the lock range data register). the drum lock flag is set when the specified number of drum locks is detected. if the ncdfg signal is detected outside the lock range after data is written in dfrcs1 and dfrcs0, the data will be stored in the lock counter. note: if dfrcs1 or dfrcs0 is re ad-accessed, the counter value is read out. if bit 3 (drum lock flag) is 1 and the drum lock counter's value is 3, it indicates that the drum speed system is locked. the drum lock counter stops un til lock is released after underflow. bit 1 bit 0 dfrcs1 dfrcs0 description 0 underflow occurs after lock was detected once. (initial value) 0 1 underflow occurs after lock was detected twice. 1 0 underflow occurs after lock was detected three times. 1 underflow occurs after lock was detected four times. section 26 servo circuits rev.2.00 jan. 15, 2007 page 626 of 1174 rej09b0329-0200 26.6.5 operation the drum speed error detector detects the speed error based on the reference value set in the dfg specified speed preset register (dfpr). the referen ce value set in dfpr is preset in the counter by ncdfg signal, and the counter decrements the count by the selected clock. the timing of the counter presetting and the error da ta latching can be selected betw een the rising or falling edge of ncdfg signal. see section 26.14.4, dfg noise removal circuit. the error data detected is sent to the digital filter circuit. the error data is signed binaries. the data takes a positive number (+) if the speed is slower than the speci fied speed, a negative number (-) if the speed is faster, or 0 if it had no error (revolving at the sp ecified speed). figure 26.28 show s an example of operation to detect the drum speed. ? setting the error data limit a limit can be set to the error data sent to the digital filter circuit using the dfg lock data register (dfrudr, dfrldr). set the upper limit of the error data in dfrudr and the lower limit in dfrldr, and write 1 in dfrfon bit. if the error data is outside the limit range, the dfrldr value is sent to the digital filter circuit if a negative number is latched, or the dfrudr value if a positive number is latched, as a limit value. be sure to turn off the limit setting (dfrfon = 0) when you set the limit value. if the limit was set with the limit setting on (dfrfon = 1), result of computation is not assured. ? lock detection if an error data is detected within the lock range set in the lock data register, the drum lock flag (df-r/unr) is set by the number of the times of locking set by dfrcs1 and dfrcs0 bits, and an interrupt is requested (irrdrm2) at th e same time. the number of the occurrence of locking (once to 4 times) before the flag is set can be specified. use dfrcs1 and dfrcs0 bits for this purpose. the on/off status of the phase system digital filter computation can be controlled automatically by the status of lock detection when bit 5 (dpha bit) of the drum system digital filter control register (dfic) is 0 (phased system digital filter computation off) and dpcnt bit is 1. ? drum system speed error detection counter the drum system speed error detection counter stops the counter and sets the overflow flag (dfovf) when an overflow occurs. at the same time, it generates an interrupt request (irrdrm1). to clear dfovf, write 0 after reading 1. if setting the flag and writing 0 take place simultaneously, the latter is invalid. section 26 servo circuits rev.2.00 jan. 15, 2007 page 627 of 1174 rej09b0329-0200 ? interrupt request irrdrm1 is generated by the ncdfg signal latc h and the overflow of the error detection counter. irrdrm2 is generated by detection of lock (after the detection of the specified number of times of locking). ?value+value specified speed value latch data 0 (no error) preset value preset period (2 counts) counter ncdfg signal error data latch signal (dfg ) preset data load signal figure 26.28 example of the drum speed error detection (when the rising edge of dfg is selected) section 26 servo circuits rev.2.00 jan. 15, 2007 page 628 of 1174 rej09b0329-0200 26.6.6 f h correction in trick play mode in trick play mode, the tape speed relative to the video head changes. this change alters the horizontal sync signal (f h ), causing skew. to correct the skew, the drum motor speed must be shifted to a different speed in each trick play m ode, so as to obtain the normal horizontal sync frequency. to shift the drum motor speed, soft ware should modify the value written in the specified dfg speed preset data regi ster in the speed error detector. this f h correction can be expressed in terms of the basic frequency f f of the drum as follows. n 0 f f = f f0 n 0 + h (1 ? n) legend: n: speed multiplier (fwd = positive, rev = negative) h : h alignment (1.5h in standard mode, 0.75h in 2x mode, and 0.5h in 3x mode for vhs and systems; 1h for an 8-mm vcr) n 0 : standard h numbers within field f f0 : field frequency ntsc: n 0 = 262.5, f f0 = 59.94 pal: n 0 = 312.5, f f0 = 50.00 section 26 servo circuits rev.2.00 jan. 15, 2007 page 629 of 1174 rej09b0329-0200 26.7 drum phase error detector 26.7.1 overview the drum phase control system must start after the drum motor has reached the specified revolution speed by the speed control system. drum phase control works as follows in record and playback mode. ? record mode: phase is controlled so that the vertical blanking intervals of the video signal to be recorded will line up along the bottom edge of the tape. ? playback mode: phase is controlled so as to trace the record ed tracks accurately. a counter detects the phase error against a preset value. the phase error data is processed and added to speed error data in a digital filter. this filter controls a pulse-width modulated (pwm) output, which controls the revolution phase and speed of the drum. the dpg signal from the drum motor is reshaped into a square wave by a reshaping circuit, and sent to the phase error detector. the phase error detector compares the phase of the dpg pulse (tach pulse), which contains video head phase information, with a reference si gnal. in the actual circuit, the comparison is carried out by comparing the head-switching (hsw) signal, which is delayed by a counter that is reset by dpg, with a reference signal value. the reference signal is the ref30 signal, which differs between record and playback as follows: ? record: vsync signal extracted from the video signal to be recorded (frame rate signal, actually 1/2 vsync). ? playback: 30 hz or 25 hz signal divided from the system clock. section 26 servo circuits rev.2.00 jan. 15, 2007 page 630 of 1174 rej09b0329-0200 26.7.2 block diagram figure 26.29 shows a block diagram of the drum phase error detector. r/w r/w r/w r/w r/w r/w ref30p hsw (video ff) nhsw (narrow ff) dpgcr dpgcr dpgcr dfucr dpgcr dppr1 dppr2 r/(w) s r f/f q w w internal bus internal bus ovf lsb msb dper1 dper2 lsb msb dpovf dfeps hswes n/v latch preset error data (20 bits) to dfu edge detector sequence controller , error data (16 bits) error data (4 bits) preset data (16 bits) preset data (4 bits) counter (20 bits) irrdrm3 dpcs1,0 s s/2 s/4 s/8 s = fosc/2 figure 26.29 block diagram of drum phase error detector section 26 servo circuits rev.2.00 jan. 15, 2007 page 631 of 1174 rej09b0329-0200 26.7.3 register configuration table 26.10 shows the register configuration of the drum phase error detector. table 26.10 register configuration name abbrev. r/w size initial value address specified drum phase preset data register 1 dppr1 w byte h'f0 h'd03c specified drum phase preset data register 2 dppr2 w word h'0000 h'd03a drum phase error data register 1 dper1 r/w byte h'f0 h'd03d drum phase error data register 2 dper2 r/w word h'0000 h'd03e drum phase error detection control register dpgcr r/w byte h'07 h'd039 section 26 servo circuits rev.2.00 jan. 15, 2007 page 632 of 1174 rej09b0329-0200 26.7.4 register description drum phase preset data registers (dppr1, dppr2) dppr1 0 0 1 0 w 2 0 w 3 dppr16 dppr17 dppr18 dppr19 0 4 1 5 1 6 1 7 ? ? ? ? ? ? ? ? w w 1 bit : initial value : r/w : dppr2 8 0 9 0 w 10 0 w 11 dppr8 dppr9 dppr10 dppr11 0 12 0 13 0 14 0 15 dppr12 dppr13 dppr14 dppr15 w w w w w w 0 bit : initial value : r/w : 0 0 1 0 w 2 0 w 3 dppr0 dppr1 dppr2 dppr3 0 4 0 5 0 6 0 7 dppr4 dppr5 dppr6 dppr7 w w w w w w 0 bit : initial value : r/w : the 20-bit preset data that defines the specified drum phase is set in dppr1 and dppr2. the 20 bits are weighted as follows: bit 3 of dppr1 is the msb, and bit 0 of dppr2 is the lsb. when data is written to dppr2, the 20-bit preset data, in cluding dppr1, is loaded into the preset circuit. write to dppr1 first, and dppr2 next. the preset data can be calculated from the following equation by using h'80000* as the reference value. target phase difference = (reference signal frequency/2) ? 6.5h drum phase preset data = h'80000 - ( s/n target phase difference) s: servo clock frequency in hz (fosc/2) s/n: clock source of selected counter only a word access is valid. if a byte access is atte mpted, correct operation is not guaranteed. no read is valid. if a read is attempted, an undetermined value is read out. dppr1 and dppr2 are initialized to h'f0 and h'0000 by a reset, and in standby mode. note: * the preset data value is calculated so that the counter will reach h'80000 when the error value is zero. when the counter value is latched as error data in the drum phase error data registers (dper1 and dper2), however, it is converted to a value referenced to h'00000. section 26 servo circuits rev.2.00 jan. 15, 2007 page 633 of 1174 rej09b0329-0200 drum phase error data registers (dper1, dper2) dper1 0 0 1 0 r * /w 2 0 r * /w 3 dper16 dper17 dper18 dper19 0 4 1 5 1 6 1 7 ? ? ? ? ? ? ? ? r * /w r * /w 1 bit : initial value : r/w : dper2 8 0 9 0 r * /w 10 0 r * /w 11 dper8 dper9 dper10 dper11 0 12 0 13 0 14 0 15 dper12 dper13 dper14 dper15 r * /w r * /w r * /w r * /w r * /w r * /w 0 bit : initial value : r/w : note: * note that only detected error data can be read. 0 0 1 0 r * /w 2 0 r * /w 3 dper0 dper1 dper2 dper3 0 4 0 5 0 6 0 7 dper4 dper5 dper6 dper7 r * /w r * /w r * /w r * /w r * /w r * /w 0 bit : initial value : r/w : dper1 and dper2 constitute a 20-bit drum phase erro r data register. the 20 bits are weighted as follows: bit 3 of dper1 is the msb, and bit 0 of dper2 is the lsb. when the rotational phase is correct, the data h'00000 is latched. negative data will be latched if the drum leads the correct phase, and positive data if it lags. values in dper1 and dper 2 are transferred to the digital filter circuit. dper1 and dper are 20-bit read/write registers. when writing data to dper 1 and dper2, write to dper1 first, and then write to dper2. only a word access is valid. if a byte access is attempted, correct operation is not guaranteed. dper1 and dper2 are initialized to h'f0 and h'0000 by a reset, and in standby mode. see the note on the drum phase preset data registers (dppr1 and dppr2). section 26 servo circuits rev.2.00 jan. 15, 2007 page 634 of 1174 rej09b0329-0200 drum phase error detection control register (dpgcr) 0 1 1 2 ? ? ? ? ? ? 1 3 0 4 0 r/w r/w 5 0 6 0 7 r/(w) * dpovf r/w dpcs0 0 r/w dpcs1 n/v hswes 1 bit : initial value : r/w : note: * only 0 can be written. dpgcr is an 8-bit read/write register that controls the operation of drum phase error detection. bits 2-0 are reserved, bit 5 accepts only read and 0 write. it is initialized to h'07 by a reset or in stand-by mode. bits 7 and 6 ? clock source selection bit (dpcs1, dpcs0): these bits select the clock supplied to the counter. ( s = fosc/2) bit 7 bit 6 dpcs1 dpcs0 description 0 s (initial value) 0 1 s/2 1 0 s/4 1 s/8 bit 5 ? counter overflow flag (dpovf): dpovf flag indicates the overflow of the 20-bit counter. it is cleared by writing 0. write 0 after r eading 1. setting has the hi ghest priority in this flag. if a flag set and 0 write occurs simultaneously, the latter is invalid. bit 5 dpovf description 0 normal state (initial value) 1 indicates that a overflow has occurred in the counter bit 4 ? error data latch signal selection bit (n/v): selects the latch signal of error data. bit 4 n/v description 0 hsw (videoff) signal (initial value) 1 nhsw (narrowff) signal section 26 servo circuits rev.2.00 jan. 15, 2007 page 635 of 1174 rej09b0329-0200 bit 3 ? edge selection bit (hswes): selects the edge of the error data latch signal (hsw or nhsw). bit 3 hswes description 0 latches at the rising edge (initial value) 1 latches at the falling edge bits 2 to 0 ? reserved: cannot be modified and are always read as 1. 26.7.5 operation the drum phase error detector detects the phase error based on the reference value set in the drum specified phase preset data registers 1 and 2 (dppr1 and dppr2). the reference values set in dppr1 and dppr2 are preset in the counter by ref30p signal, and counted up by the clock selected. the latch of the error data can be se lected between the rising or falling edge of hsw (nhsw). the error data detected in the error data automatic transmission mode (dfeps bit of dfucr = 0) is sent to the digital filter circuits automatically. in soft transmission mode (dfeps bit of dfucr = 1), the data written in dper1 and dp er2 is sent to the digital filter circuit. the error data is signed binary. it takes a positive number (+) if the phase is behind the specified phase, a negative number (-) if in advance of the specified phase, or 0 if it had no phase error (revolving at the specified phase). figures 26.30 and 26.31 show examples of operation to detect a drum phase error. drum phase error detection counter: the drum phase error detection counter stops counting when an overflow or latch occurs. at the same time, it generates an interrupt request (irrdrm3), and sets the overflow flag (dpovf) if an ove rflow occurred. to clear dpovf, write 0 after reading 1. if setting the flag and writing 0 ta ke place simultaneously, the latter is invalid. interrupt request: irrdrm3 is generated by the hsw (nhsw) signal latch and the overflow of the error detection counter. section 26 servo circuits rev.2.00 jan. 15, 2007 page 636 of 1174 rej09b0329-0200 latch latch preset value counter hsw (nhsw) * ref30p preset value preset preset note: * edge selectable figure 26.30 drum phase control in playback mode (hsw rising edge selected) latch latch preset value counter hsw (nhsw) * vd ref30p preset value preset note: * edge selectable preset reset reset figure 26.31 drum phase control in r ecord mode (hsw rising edge selected) section 26 servo circuits rev.2.00 jan. 15, 2007 page 637 of 1174 rej09b0329-0200 26.7.6 phase comparison the phase comparison circuit measures the differ ence of time between the reference signal and the comparing signal with a digital counter. ref30 signal is used for the reference signal, and hsw signal (videoff) or nhsw signal (narrowff) from the hsw timing generator is used for the comparing signal. in record mode, however, the phase of ref30 signal is the same as that of the vertical sync signal (vsync) because the refere nce signal generator (ref30 generator) is reset by the vertical sync signal (vsync) in the video signals. the error detection counter latche s data at the rising or falling edge of hsw signal. the digital filter circuit performs computation using this data as 20-bit phase error data. after processing and adding the phase error data and the speed error data from the drum speed control system, the digital filter circuit sends the da ta as the error data of the drum system to the pwm modulation circuit. 26.8 capstan speed error detector 26.8.1 overview capstan speed control holds the capstan motor at a constant revolution speed, by measuring the period of the cfg signal. a digital counter detects the speed error against a preset value. the speed error data is added to phase error data in a digital filter. this filter controls a pulse-width modulated (pwm) output, which controls the revolution speed and phase of the capstan motor. the cfg input signal is downloaded by the comparator circuit, then reshaped into a square wave by a reshaping circuit, divided by the cfg divider, and sent to the speed error detector as the dvcfg signal. the speed error detector uses the system clock to measure the period of the dvcfg signal, and detects the error against a preset data value. th e preset data is the value that results from measuring the dvcfg signal period with the clock signal when the capstan motor is running at the correct speed. the error detector operates by latching a counter value when it detects an edge of the dvcfg signal. the latched count provides 16 bits of speed error data for the digita l filter to operate on. the digital filter adds the speed error data to phase error data from the capstan phase control system, then sends the result to the pwm as capstan error data. section 26 servo circuits rev.2.00 jan. 15, 2007 page 638 of 1174 rej09b0329-0200 26.8.2 block diagram figure 26.32 shows a block diagram of the capstan speed error detector. w w r udf ovf lock 2 up clear latch preset cfvcr cfrldr cfvcr cfpr cfvcr cfvcr cfvcr cfucr cfer cfrvcr error data (16 bits) to dfu dvcfg cfrudr internal bus r/w internal bus r/w w r/w r/w r/w r/w (r)/w lock 1 up s r f/f q s r f/f cfrcs1,0 cf-r/unr lock counter (2 bits) q s r f/f q lock range detector lock range data (16 bits) lock range data (16 bits) cpcnt error data limiter control circuit cfrfon cfess error data (16 bits) counter (16 bits) cfovf irrcap2 irrcap1 crockon to dfu preset data (16 bits) cfcs1,0 s s/2 s/4 s/8 figure 26.32 block diagram of capstan speed error detector section 26 servo circuits rev.2.00 jan. 15, 2007 page 639 of 1174 rej09b0329-0200 26.8.3 register configuration table 26.11 shows the register configuration of the capstan speed error detector. table 26.11 register configuration name abbrev. r/w size initial value address specified cfg speed preset data register cfpr w word h'0000 h'd050 cfg speed error data register cfer r/w word h'0000 h'd052 cfg lock upper data register cfrudr w word h'7fff h'd054 cfg lock lower data register cfrldr w word h'8000 h'd056 capstan speed error detection control register cfvcr r/w byte h'00 h'd058 section 26 servo circuits rev.2.00 jan. 15, 2007 page 640 of 1174 rej09b0329-0200 26.8.4 register description specified cfg speed pres et data register (cfpr) 8 0 9 0 w 10 0 w 11 0 12 0 w 0 w 13 14 0 15 cfpr 12 cfpr 11 cfpr 10 cfpr 9 cfpr 8 0 w cfpr 15 w w w cfpr 14 cfpr 13 bit : initial value : r/w : 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 cfpr 4 cfpr 3 cfpr2 cfpr 1 cfpr 0 0 w cfpr 7 w w w cfpr 6 cfpr 5 bit : initial value : r/w : the 16-bit preset data that defines the specified cfg speed is set in cfpr. when data is written, the 16-bit preset data is sent to the preset ci rcuit. the preset data can be calculated from the following equation by using h'8000* as the reference value. s/n cfg speed preset data = h'8000 ? ( ? 2) dvcfg frequenc y s: servo clock frequency in hz (f osc /2) dvcfg frequency: in hz the constant 2 is the preset interval (see figure 26.33). s/n: clock source of the selected counter cfpr is a 16-bit write-only register. only a wo rd acces is valid. if a byte access is attempted, correct operation is not guaranteed. cfpr is initialized to h'0000 by a reset. note: * the preset data value is calculated so that the counter will reach h'8000 when the error is zero. when the counter value is latched as error data in the cfg speed error data register (cfer), however, it is converted to a value referenced to h'0000. section 26 servo circuits rev.2.00 jan. 15, 2007 page 641 of 1174 rej09b0329-0200 cfg speed error data register (cfer) 8 0 9 0 r * /w 10 0 r * /w 11 0 12 0 r * /w 0 r * /w 13 14 0 15 cfer12 cfer11 cfer10 cfer9 cfer8 0 r * /w cfer15 r * /w r * /w r * /w cfer14 cfer13 bit : initial value : r/w : note: * note that only detected error data can be read. 0 0 1 0 r * /w 2 0 r * /w 3 0 4 0 r * /w 0 r * /w 5 6 0 7 cfer4 cfer3 cfer2 cfer1 cfer0 0 r * /w cfer7 r * /w r * /w r * /w cfer6 cfer5 bit : initial value : r/w : cfer is a 16-bit read/write register that stores 16-bit cfg speed error data. when the speed of the capstan motor is correct, the data latched in cfer is h'0000. negative data will be latched if the speed is faster than the specified speed, and positive data if the speed is slower than the specified speed. the cfer value is sent to the digital filter either automatically or by software. only a word access is valid. if a byte access is a ttempted, correct operation is not guaranteed. cfer is initialized to h'0000 by a reset, an d in module stop mode and standby mode. see the note on the specified cfg speed preset da ta register (cfpr) in section 26.8.4, register description. cfg lock upper data register (cfrudr) 8 1 9 1 w 10 1 w 11 1 12 1 w 1 w 13 14 1 15 cfrudr 12 cfrudr 11 cfrudr 10 cfrudr 9 cfrudr 8 0 w cfrudr 15 w w w cfrudr 14 cfrudr 13 bit : initial value : r/w : 0 1 1 1 w 2 1 w 3 1 4 1 w 1 w 5 6 1 7 cfrudr 4 cfrudr 3 cfrudr 2 cfrudr 1 cfrudr 0 1 w cfrudr 7 w w w cfrudr 6 cfrudr 5 bit : initial value : r/w : cfrudr is a 16-bit write-only register used to set the lock range on the upper side when capstan speed lock is detected, and to set the limit value on the upper side when limiter function is in use. when lock is being detected, if the capstan speed is detected within the lock range, the lock counter which has been set by cfrcs1 and cfrcs0 bits of cfvcr register decrements the count. if the set value of cfrcs1 and cfrcs0 matches the number of times of occurrence of locking, the computation of the digital filter in the capstan phase system can be controlled automatically. also, if the cfg speed error data exceeds the cfrudr value when the limiter function is in use, the dfrudr value can be used as the data for computation by the digital filter. only a word access is valid. if a byte access is a ttempted, correct operation is not guaranteed. a section 26 servo circuits rev.2.00 jan. 15, 2007 page 642 of 1174 rej09b0329-0200 read is invalid. if a read is attempted, an undeterm ined value is read out. it is initialized to h'7fff by a reset, or in stand-by or module-stop mode. cfg lock lower data register (cfrldr) 8 0 9 0 w 10 0 w 11 0 12 0 w 0 w 13 14 0 15 cfrldr 12 cfrldr 11 cfrldr 10 cfrldr 9 cfrldr 8 1 w cfrldr 15 w w w cfrldr 14 cfrldr 13 bit : initial value : r/w : 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 cfrldr 4 cfrldr 3 cfrldr 2 cfrldr 1 cfrldr 0 0 w cfrldr 7 w w w cfrldr 6 cfrldr 5 bit : initial value : r/w : cfrldr is a 16-bit write-only register used to set the lock range on the lower side when capstan speed lock is detected, and to set the limit value on lower side when limiter function is in use. when lock is being detected, if the drum speed is detected within the lock range, the lock counter that has been set by cfrcs 1 and 0 bits of cfvcr register decrements the count. if the set value of cfrcs 1 and 0 matches the number of times of occurrence of locking, the computation of the digital filter in the drum phase system can be controlled automatically. also, if the cfg speed error data is under the cfrldr value when the limiter function is in use, the cfrldr value can be used as the data for computation by the digital filter. only a word access is valid. if a byte access is atte mpted, correct operation is not guaranteed. no read is valid. if a read is attempted, an undetermin ed value is read out. it is initialized to h'8000 by a reset, or in stand-by or module-stop mode. capstan speed error detection control register (cfvcr) 0 0 1 0 (r) * 2 /w 2 0 r/w 3 0 4 0 r/w 0 r/(w) * 1 5 6 0 7 cfrfon cf-r/unr cpcnt cfrcs1 cfrcs0 0 r/w cfcs1 (r) * 2 /w r r/w cfcs0 cfovf notes: bit : initial value : r/w : 1. only 0 can be written. 2. if read-accessed, the counter value is read out. cfvcr is an 8-bit read/write register that controls the operation of capstan speed error detection. bit 3 accepts only read, and bit 5 accepts only read an d 0 write. it is initialized to h'00 by a reset, or in stand-by or module-stop mode. section 26 servo circuits rev.2.00 jan. 15, 2007 page 643 of 1174 rej09b0329-0200 bits 7 and 6 ? clock source selection bits (cfcs1, cfcs0): cfcs1 and cfcs0 select the clock to be supplied to the counter. ( s = fosc/2) bit 7 bit 6 cfcs1 cfcs0 description 0 s (initial value) 0 1 s/2 1 0 s/4 1 s/8 bit 5 ? counter overflow flag (cfovf): cfovf flag indicates overflow of the 16-bit counter. it is cleared by writing 0. write 0 after reading 1. setting has the highest priority in this flag. if a flag set and 0 write occurs simultaneously, the latter is invalid. bit 5 cfovf description 0 normal state. (initial value) 1 indicates that a overflow has occurred in the counter. bit 4 ? error data limit function selection bit (cfrfon): enables the error data limit function. (limit values are the values set in the lock range data register (cfrudr, cfrldr)). bit 4 cfrfon description 0 disables limit function. (initial value) 1 enables limit function. bit 3 ? capstan lock flag (cf-r/unr): sets a flag if an underflow occurred in the capstan lock counter. bit 3 cf-r/unr description 0 indicates that the capstan speed system is not locked. (initial value) 1 indicates that the capstan speed system is locked. section 26 servo circuits rev.2.00 jan. 15, 2007 page 644 of 1174 rej09b0329-0200 bit 2 ? capstan phase system filter computation automatic start bit (cpcnt): enables the filter computation of the phase system if an underflow occurred in the capstan lock counter. bit 2 cpcnt description 0 disables the filter computation by detection of the capstan lock. (initial value) 1 enables the filter computation of the phase system when capstan lock is detected. bits 1 and 0 ? capstan lock counter setting bits (cfrcs1, cfrcs0): sets the number of times to detect capstan locks (dvcfg has been de tected in the rage set by the lock range data register). the capstan lock flag is set when the specified number of capstan lock is detected. if the dvcfg signal is detected outside the lock range after data is written in cfrcs1 and cfrcs0, the data will be stored in the lock counter. note: if cfrcs1 or cfrcs0 is read-accessed, the counter value is read out. if bit 3 (capstan lock flag) is 1 and the capstan lock counter's value is 3, it i ndicates that the capstan speed system is locked. the capstan lock counter stops until lock is released after underflow. bit 1 bit 0 cfrcs1 cfrcs0 description 0 underflow occurs after lock was detected once (initial value) 0 1 underflow occurs after lock was detected twice 1 0 underflow occurs after lock was detected three times 1 underflow occurs after lock was detected four times section 26 servo circuits rev.2.00 jan. 15, 2007 page 645 of 1174 rej09b0329-0200 26.8.5 operation the capstan speed error detector detects the speed error based on the reference value set in the cfg specified speed preset register (cfpr). the reference value set in c fpr is preset in the counter by the dvcfg signal, and the counter decrements the count by the selected clock. the timing of the counter presetting and the error data latching can be selected between the rising or falling edge of dvcfg signal. see dvcfg control register (cdvc) in section 26.14.3, cfg frequency divider. the error data detected is sent to digital filter circuit. the error data is signed binaries. the data takes a positive number (+) if th e speed is slower than the specified speed, a negative number (-) if the speed is faster, or 0 if it had no error (revolving at the specified speed). figure 26.33 shows an example of operation to detect the capstan speed. setting the error data limit: a limit can be set to the error data sent to the digital filter circuit using the cfg lock data register (cfrudr, cfrldr). set the upper limit of the error data in cfrudr and the lower limit in cfrldr, and write 1 in cfrfon bit. if the error data is outside the limit range, the cfrldr value is sent to the digital filter circuit if a negative number is latched, or the cfrudr value if a positive number is latched, as a limit value. be sure to turn off the limit setting (cfrfon = 0) when you set the limit value. if the limit was set with the limit setting on (cfrfon = 1), result of computation is not assured. lock detection: if an error data is detected within the lock range set in the lock data register, the capstan lock flag (cf-r/unr) is set by the number of the times of locking set by cfrcs1 and cfrcs0 bits, and an interrupt is requested (irrcap2) at the same time. the number of the occurrence of locking (once to 4 times) before th e flag is set can be specified. use cfrcs1 and cfrcs0 bits for this purpose. the on/off state of the phase system digital filter computation can be controlled automatically by the status of lock detection when bit 5 (cpha bit) of the capstan system digital filter control register (cfic) is 0 (phased system digital filter computation off) and dpcnt bit is 1. capstan system speed error detection counter: the capstan system speed error detection counter stops the counter and sets the overflow flag (cfovf) when an overflow occurs. at the same time, it generates an interrupt request (irrcap1). to clear cfovf, write 0 after reading 1. if setting the flag and writing 0 take place simultaneously, the latter is invalid. interrupt request: irrcap1 is generated by the dvcfg signal latch and the overflow of the error detection counter. irrcap2 is generated by detection of lock (after the detection of the specified number of times of locking). section 26 servo circuits rev.2.00 jan. 15, 2007 page 646 of 1174 rej09b0329-0200 ?value +value specified speed value latch data 0 (no error) preset value preset period (2 counts) counter error data latch signal (dvcfg) preset data load signal figure 26.33 example of the capstan speed e rror detection section 26 servo circuits rev.2.00 jan. 15, 2007 page 647 of 1174 rej09b0329-0200 26.9 capstan phase error detector 26.9.1 overview the capstan phase control system must start ope ration after the capstan motor has reached the specified speed by the speed cont rol system. the capstan phase control system operates as follows in record/playback mode: ? record mode: controls the tape running so that it may run at a specified speed together with the speed control system. ? playback mode: controls the tape running so th at the recorded track may be traced correctly. any error deviated from the reference phase is detected by the digital counter. this phase error data and the speed error data is processed and added by the digital filter circuit to control the pwm output. the phase and speed of the capstan, in turn, is control this pwm output. the control signal of the capstan phase control in the record mode differ from that in playback mode. in record mode, the control is performed by the dvcfg2 signal which is generated by dividing the frequencies of the reference signal (ref30p or cref) and the cfg signal. in playback mode, it is performed by divided ri sing signal (dvctl) of the reference signal (capref30) and the playback control pulse (pb-ctl). the reference signal in record and playback modes are as follows: ? record mode: 1/2 vsync signal extracted from the video signal to be recorded. ? playback mode: signal generated by dividing the pb-ctl signal (dvctl) at its rising edge. 26.9.2 block diagram figure 26.34 shows the block diagram of the capstan phase error detector. section 26 servo circuits rev.2.00 jan. 15, 2007 page 648 of 1174 rej09b0329-0200 r/w r/w r/w r/w r/w r/w cref ref30p capref30 recref dvcfg2 dvctl cpgcr r/w cr/rf cpgcr dfucr cpgcr cppr1 cppr2 r/(w) s r f/f q w w internal bus internal bus ovf lsb msb cper1 cper2 lsb msb cpovf cfeps selcfg2 r/w ctlm r/p asm latch preset error data (20 bits) to dfu sequence controller error data (16 bits) error data (4 bits) preset data (16 bits) preset pb: x value + trk value = capref30 rec: ref30p or cref latch pb : dvctl rec : dvcfg2 preset data (4 bits) counter (20 bits) irrcap3 cpcs1,0 s s/2 s/4 s/8 s = fosc/2 figure 26.34 block diagram of capstan phase error detector section 26 servo circuits rev.2.00 jan. 15, 2007 page 649 of 1174 rej09b0329-0200 26.9.3 register configuration table 26.12 shows the register configuration of the capstan phase error detector. table 26.12 register configuration name abbrev. r/w size initial value address specified capstan phase preset data register 1 cppr1 w byte h'f0 h'd05c specified capstan phase preset data register 2 cppr2 w word h'0000 h'd05a capstan phase error data register 1 cper1 r/w byte h'f0 h'd05d capstan phase error data register 2 cper2 r/w word h'0000 h'd05e capstan phase error detection control register cpgcr r/w byte h'07 h'd059 section 26 servo circuits rev.2.00 jan. 15, 2007 page 650 of 1174 rej09b0329-0200 26.9.4 register description specified capstan phase preset data registers (cppr1, cppr2) cppr1 0 0 1 0 w 2 0 w 3 0 4 1 5 1 6 1 7 ? cppr19 cppr18 cppr17 cppr16 ? ? ? ? ? ? ? w w 1 bit : initial value : r/w : cppr2 8 0 9 0 w 10 0 w 11 cppr8 cppr9 cppr10 cppr11 0 12 0 13 0 14 0 15 cppr12 cppr13 cppr14 cppr15 w w w w w w 0 bit : initial value : r/w : 0 0 1 0 w 2 0 w 3 cppr0 cppr1 cppr2 cppr3 0 4 0 5 0 6 0 7 cppr4 cppr5 cppr6 cppr7 w w w w w w 0 bit : initial value : r/w : the 20-bit preset data that defines the specified capstan phase is set in cppr1 and cppr2. the 20 bits are weighted as follows: bit 3 of cppr1 is the msb. bit 0 of cppr2 is the lsb. when cppr2 is written to, the 20-bit preset data, including cppr1, is loaded into the preset circuit. write to cppr1 first, and cppr2 next. the preset data can be calculated from the following equation by using h'80000* as the reference value. target phase difference = reference signal frequency/2 capstan phase preset data = h'80000 ? ( s/n target phase difference) s: servo clock frequency in hz (fosc/2) s/n: clock source of selected counter only a word access is valid. if a byte access is atte mpted, correct operation is not guaranteed. no read is valid. if a read is attempted, an undetermined value is read out. cppr1 and cppr2 are initialized to h'f0 and h'0000 by a reset, and in standby mode. note: * the preset data value is calculated so that the counter will reach h'80000 when the error is zero. when the counter value is latched as error data in the capstan phase error data registers (cper1 and cper2), however, it is converted to a value referenced to h'00000. section 26 servo circuits rev.2.00 jan. 15, 2007 page 651 of 1174 rej09b0329-0200 capstan phase error data registers (cper1, cper2) 0 0 1 0 r * /w 2 0 r * /w 3 0 4 1 5 1 6 1 7 ? ? ? ? ? ? ? ? r * /w r * /w 1 bit : initial value : r/w : cper19 cper18 cper17 cper16 8 0 9 0 r * /w 10 0 r * /w 11 cper8 cper9 cper10 cper11 0 12 0 13 0 14 0 15 cper12 cper13 cper14 cper15 r * /w r * /w r * /w r * /w r * /w r * /w 0 bit : initial value : r/w : note: * note that only detected error data can be read. 0 0 1 0 r * /w 2 0 r * /w 3 cper0 cper1 cper2 cper3 0 4 0 5 0 6 0 7 cper4 cper5 cper6 cper7 r * /w r * /w r * /w r * /w r * /w r * /w 0 bit : initial value : r/w : cper1 and cper2 constitute a 20-bit capstan phase error data register. the 20 bits are weighted as follows: bit 3 of cper1 is the msb. bit 0 of cper2 is the lsb. when the rotational phase is correct, the data h'00000 is latched. negative data will be latched if the phase leads the correct phase, and positive data if it lags. values in cper1 and cper 2 are transferred to the digital filter circuit. cper1 and cper are 20-bit read/write registers. when writing data to cper 1 and cper2, write to cper1 first, and then write to cper2. only a word access is valid. if a byte access is attempted, correct operation is not guaranteed. cper1 and cper2 are initialized to h'f0 and h'0000 by a reset, and in standby mode. see the note on the capstan phase preset data registers (cppr1 and cppr2) in section 26.9.4, register description. section 26 servo circuits rev.2.00 jan. 15, 2007 page 652 of 1174 rej09b0329-0200 capstan phase error detection control register (cpgcr) 0 1 1 2 ? ? ? ? ? ? 1 3 0 4 0 r/w 5 0 6 0 7 r/w r/(w) * cpovf r/w cpcs0 0 r/w cpcs1 cr/rf selcfg2 1 note: * only 0 can be written bit : initial value : r/w : cpgcr is an 8-bit read/write register that controls the operation of capstan phase error detection. bits 2-0 are reserved, and bit 5 accepts only read and 0 write. it is initialized to h'07 by a reset or in stand-by mode. bits 7 and 6 ? clock source selection bit (cpcs1, cpcs0): these bits select the clock supplied to the counter. ( s = fosc/2) bit 7 bit 6 cpcs1 cpcs0 description 0 s (initial value) 0 1 s/2 1 0 s/4 1 s/8 bit 5 ? counter overflow flag (cpovf): cpovf flag indicates the overflow of the 20-bit counter. it is cleared by writing 0. write 0 after r eading 1. setting has the hi ghest priority in this flag. if a flag set and 0 write occurs simultaneously, the latter is invalid. bit 5 cpovf description 0 normal state (initial value) 1 indicates that a overflow has occurred in the counter bit 4 ? preset signal selection bit (cr/rf): selects the preset signal. bit 4 cr/rf description 0 presets ref30p (initial value) 1 presets cref signal section 26 servo circuits rev.2.00 jan. 15, 2007 page 653 of 1174 rej09b0329-0200 bit 3 ? latch signal selection bit (selcfg2): selects the counter preset signal and the error data latch signal data in pb (asm) mode. bit 3 selcfg2 description 0 presets capref30 signal; latches dvctl signal (initial value) 1 presets ref30p (cref) signal; latches dvcfg2 signal bits 2 to 0 ? reserved: cannot be modified and are always read as 1. 26.9.5 operation the capstan phase error detector detects the phase error based on the reference value set in the capstan specified phase preset data registers 1 and 2 (cppr1 and cppr2). the reference values set in cppr1 and cppr2 are preset in the counter by ref30p (cref) signal or capref signal, and counted up by the clock selected. the latching of the error data is performed by dvctl or dvcfg2. the error data detected in the error data automatic transmission mode (cfeps bit of dfucr = 0) is sent to the digital filter circuit automatically. in soft transmission mode (cfeps bit of dfucr = 1), the data written in cper1 and cppr2 is sent to the digital filter circuit. the error data is signed binary. it takes a positive number (+) if the phase is behind the specified phase, a negative number (-) if in advance of the specified phase, or 0 if it had no phase error (revolving at the specified phase). figures 26.35 and 26.36 show examples of operation to detect a capstan phase error. capstan phase error detection counter: the capstan phase error detection counter stops counting when an overflow or latch occurs. at the same time, it generates an interrupt request (irrcap3), and sets the overflow flag (cpovf) if overflow occurred. to clear cpovf, write 0 after reading 1. if setting the flag and writing 0 take place simultaneously, the latter is invalid. interrupt request: irrcap3 is generated by the dvctl or dvcfg2 signal latch and the overflow of the error detection counter. section 26 servo circuits rev.2.00 jan. 15, 2007 page 654 of 1174 rej09b0329-0200 latch latch preset value counter pb-ctl capref30 dvctl or dvcfg2 preset preset figure 26.35 capstan phase control in playback mode latch latch preset value counter dvcfg2 ref30p or cref preset preset figure 26.36 capstan phas e control in record mode section 26 servo circuits rev.2.00 jan. 15, 2007 page 655 of 1174 rej09b0329-0200 26.10 x-value and tracking adjustment circuit 26.10.1 overview to maintain compatibility with other vcrs, an on-chip adjustment circuit adjusts the phase of the reference signal (internal reference signal (ref30) or external reference signal (excap)) during playback. because of manufacturing tolerances, th e physical distance betw een the video head and control head (the x-value: 79.244 mm) may vary from set to set, so when a tape that was recorded on a different set is played back, the phase of th e reference signal may need to be adjusted. the adjustment can be made by a register setting. the same setting can adjust the rotational phase of the capstan motor to maintain positional alignment (tracking alignment) of the video head with the recorded tracks in autotrack ing, or when tracks that were record ed with an ep head are traced by a wider head. these tracking adjustments can be made by the acquisition of the envelope signal by the a/d converter. 26.10.2 block diagram the adjustment circuit consists of a 10-bit counter clocked by the system clock ( s or s/2), and two down-counters with load regi sters. individual setting of x-va lue adjustment can be made by x-value data register (xdr) and tracking adjustment by trk data register (trdr). the reference signal clears the 10-bit counter and sets the load register value in the down-counter with two load registers. after the adjusted reference signal is generated, clock supply stops and the circuit halts until the next reference signal is input. re f30 signal can be divided as necessary. figure 26.37 shows a block diagram. section 26 servo circuits rev.2.00 jan. 15, 2007 page 656 of 1174 rej09b0329-0200 r * /w note: * when dvref1 and dvref0 are read, values in the down counter (2 bits) are readout. s = fosc/2 s s /2 excap ref30p xtcr w w xcs xtcr w at/mu asm rec/pb xtcr w trk/x s r q s r q internal bus internal bus dvref1, 0 caprf exc/ref w w xtcr xtcr down counter edge selection , (2 bits) counter (10 bits) capref30 ref30x w x-value data register xdr (12 bits) trk value data register trdr (12 bits) down counter (12 bits) (12 bits) down counter figure 26.37 block diagram of x-value adjustment circuit section 26 servo circuits rev.2.00 jan. 15, 2007 page 657 of 1174 rej09b0329-0200 26.10.3 register description register configuration table 26.13 shows the register configuration of x-value correction and tracking correction circuits. table 26.13 register configuration name abbrev. r/w size initial value address x-value and trk-value control register xtcr r/w byte h'80 h'd074 x-value data register xdr w word h'f000 h'd070 trk-value data register trdr w word h'f000 h'd072 x-value and trk-value control register (xtcr) 0 0 1 0 r/w 2 0 w 3 0 4 0 w 5 0 6 0 7 ? ? r/w w w at/mu w caprf trk/x exc/ref xcs dvref1 dvref0 1 bit : initial value : r/w : xtcr is an 8-bit register to determine the x-value and trk-value correction circuits. bits 6 to 2 are write-only bits. no read is valid. if a read is attempted, an undetermined value is read out. bits 1 and 0 are read/write bits. only a byte access is valid for xtcr. if a wo rd access is attempted, correct operation is not guaranteed. it is initialized to h'80 by a reset, or in stand-by or module stop mode. bit 7 ? reserved: cannot be modified and is always read as 1. bit 6 ? external sync signal edge selection bit (caprf): selects the excap edge when a selection is made to generate external sync signals. bit 6 caprf description 0 signal generated at the rising edge of excap. (initial value) 1 signal generated at both edges of excap. section 26 servo circuits rev.2.00 jan. 15, 2007 page 658 of 1174 rej09b0329-0200 bit 5 ? capstan phase correction auto /manual selection bit (at/ mu ): selects whether the generation of the correction reference signal (capref30) for capstan phase control is controlled automatically or manually depending on the status of the asm and rec/ pb bits of ctl mode register. bit 5 at/ mu description 0 manual mode (initial value) 1 auto mode bit 4 ? capstan phase correction regi ster selection bit (trk/ x ): determines the method to generate the capref30 signal when at/ mu bit is 0. bit 4 trk/ x description 0 generates capref30 only by the set value of xdr. (initial value) 1 generates capref30 by the set value of xdr and trdr. bit 3 ? reference signal selection bit (exc/ref): selects the reference signal to generate the correction reference signal (capref30). bit 3 exc/ref description 0 generates the signal based on ref30p. (initial value) 1 generates the signal based on the external reference signal. bit 2 ? clock source selection bit (xcs): selects the clock source to be supplied to the 10-bit counter. bit 2 xcs description 0 s (initial value) 1 s/2 section 26 servo circuits rev.2.00 jan. 15, 2007 page 659 of 1174 rej09b0329-0200 bits 1 and 0 ? ref30p division ratio selection bit (dvref1, dvref0): select the division value of ref30p. if they are read-accessed, the co unter value is read out. (the selected division value is set by the udf of the counter.) bit 1 bit 0 dvref1 dvref0 description 0 division in 1 (initial value) 0 1 division in 2 1 0 division in 3 1 division in 4 x-value data register (xdr) 1 13 1 14 1 15 10 32 54 7 0 w 6 0 w 9 0 w 8 0 w 11 0 w 10 0 w 1 ww ww ww 12 ? ? ?? ? ? ?? xd1 xd0 xd3 xd2 xd5 xd4 xd7 xd6 xd9 xd8 xd11 xd10 0 0 0 0 0 0 bit : initial value : r/w : the x-value data register (xdr) is an 16-bit write-only register. no read is valid. if a read is attempted, an undetermined value is read out . only a word access is valid. if a byte access is attempted, correct operation is not guaranteed. set an x-value correction data to xdr, except a value which is beyond the cycle of the ctl pulse. if at/ mu = 0, trk/ x = 0 is set, capref30 can be generated only by setting the xdr. set an x-value and trk correction value in pb mode, and x- value in rec mode. it is initialized to h'f000 by a reset, or in stand-by or module stop mode. trk-value data register (trdr) 1 13 1 14 1 15 10 32 54 7 0 w 6 0 w 9 0 w 8 0 w 11 0 w 10 0 w 1 ww ww ww 12 ? ? ?? ? ? ?? trd1 trd0 trd3 trd2 trd5 trd4 trd7 trd6 trd9 trd8 trd11 trd10 0 0 0 0 0 0 bit : initial value : r/w : the trk-value data register (trdr) is an 16-bit wr ite-only register. no read is valid. if a read is attempted, an undetermined value is read out. only a word access is valid. if a byte access is attempted, correct operation is not guaranteed. set an trk-value correction data to trdr, except a value which is beyond the cycle of the ctl pulse. it is initialized to h'f000 by a rese t, or in stand-by or module stop mode. section 26 servo circuits rev.2.00 jan. 15, 2007 page 660 of 1174 rej09b0329-0200 26.11 digital filters 26.11.1 overview the digital filters required in servo control make extensive use of multiply-accumulate operations on signed integers (error data) and coefficients. a filter computation circuit (digital filter computation circuit) is provided in on-chip hardware to reduce the load on software, and to improve processing efficiency. figure 26.38 shows a block diagram of the filter circuit configuration. the filter circuit includes a high-speed 24-bit 16-bit multiplier-accumu lator, an arithmetic buffer, and an i/o processor. the digital filter computations are carried out by the high-speed multiplier-accumulator. the arithmetic buffer stores coefficients and gain constants needed in the filter computations, which are referenced by the high-speed multiplier-accumulator. the i/o processor is activated by a frequency generator signal, and determines what operation is carried out. when activated, it reads the speed error and phase error from the speed and phase error detectors and sends them to the accumulator. when the filter computation is completed, the i/o processor reads the result from the accumulator and sends it to a 12-bit pwm. at this time, the accumulation result gain can be controlled. section 26 servo circuits rev.2.00 jan. 15, 2007 page 661 of 1174 rej09b0329-0200 26.11.2 block diagram data bus accumulator end start error latch signal error data (from the error detector) motor control data (to pwm circuit) buffer/ register select & r/w address bus error check accumulation controller la (16 bits), lower accumulator ua (32 bits), upper accumulator md (32 bits), multiplied data data shifter accumulation sequence circuit buffer circuit a, b, g, etc. write-only read-only accumu- lator calculation buffer coefficient register constant register sign controller figure 26.38 block diagram of digital filter circuit section 26 servo circuits rev.2.00 jan. 15, 2007 page 662 of 1174 rej09b0329-0200 16 24 8 z -1 -+ * 1 usn-1 gks + + ofs + - + + 24 8 ws 24 8 vbs 14 4 24 8 xas 24 8 xsn 24 8 vsn 24 8 dfuout 12 24 8 es error detector ? add 0s to 8 bits after the decimal point ? add the same 8-bit value as msb right-bit shift of the decimal point along with go pwm note: go = 64, 32 are optional. go = 64, 32, 16, 8, 4, 2 24 8 usn 16 dzs11 to 0 czs11 to 0 dbs15 to 0 cbs15 to 0 16 dgks15 to 0 cgks15 to 0 dofs15 to 0 cofs15 to 0 dfic cfic dfer15 to 0 cfer15 to 0 das15 to 0 cas15 to 0 bs as gs ks go 16 es pwm digital filter control register speed system 24 8 z -1 -+ * 1 upn-1 gkp + + ofp + - 24 8 tp 24 8 vbp 24 8 xap 24 8 vpn 24 8 y phase direct test output notes: 1. see figure 26.42, z -1 initialization circuit. 2. gain control is disabled during phase output. 12 24 8 ep error detector ? add 0s to 8 bits after the decimal point ? add the same 8-bit value as msb pwm 24 8 upn dzp11 to 0 czp11 to 0 dbp15 to 0 cbp15 to 0 16 16 dgkp15 to 0 cgkp15 to 0 dofp15 to 0 cofp15 to 0 dper19 to 0 cper19 to 0 dap15 to 0 cap15 to 0 bp ap gp kp 20 16 16 ep pwm pion * 2 ? dfucr ? option cp/dp phase system overflows during accumulation are ignored, and values below the decimal point are always omitted. figure 26.39 digital filter representation section 26 servo circuits rev.2.00 jan. 15, 2007 page 663 of 1174 rej09b0329-0200 26.11.3 arithmetic buffer this buffer stores computational data used in th e digital filters. see table 26.14. write access is limited to the gain and coefficient data (z -1 ). the other data is used by hardware. none of the data can be read. table 26.14 arithmetic bu ffer register configuration buffer data length arithmetic data gain or coefficient processing data 16 bits 16 bits 16 bits phase system ep upn upn-1 (zp -1 ) vpn tp y ap bp gkp ofp ap epn bp vpn speed system es xsn usn usn-1 (zs -1 ) vsn ws as bs gks ofs as xsn bs vsn error output pwm legend: valid bits non-existent bits decimal point section 26 servo circuits rev.2.00 jan. 15, 2007 page 664 of 1174 rej09b0329-0200 26.11.4 register configuration table 26.15 shows the register configuration of the digital circuit. table 26.15 register configuration name abbrev. r/w size initial value address capstan phase gain constant cgkp w word undetermined h'd010 capstan speed gain constant cgks w word undetermined h'd012 capstan phase coefficient a cap w word undetermined h'd014 capstan phase coefficient b cbp w word undetermined h'd016 capstan speed coefficient a cas w word undetermined h'd018 capstan speed coefficient b cbs w word undetermined h'd01a capstan phase offset cofp w word undetermined h'd01c capstan speed offset cofs w word undetermined h'd01e drum phase gain constant dgkp w word undetermined h'd000 drum speed gain constant dgks w word undetermined h'd002 drum phase coefficient a dap w word undetermined h'd004 drum phase coefficient b dbp w word undetermined h'd006 drum speed coefficient a das w word undetermined h'd008 drum speed coefficient b dbs w word undetermined h'd00a drum phase offset dofp w word undetermined h'd00c drum speed offset dofs w word undetermined h'd00e drum system speed delay initialization register dzs w word h'f000 h'd020 drum system phase delay initialization register dzp w word h'f000 h'd022 capstan system speed delay initialization register czs w word h'f000 h'd024 capstan system phase delay initialization register czp w word h'f000 h'd026 drum system digital filter control register dfic r/w byte h'80 h'd028 capstan system digital filter control register cfic r/w byte h'80 h'd029 digital filter control register dfucr r/w byte h'c0 h'd02a section 26 servo circuits rev.2.00 jan. 15, 2007 page 665 of 1174 rej09b0329-0200 26.11.5 register description gain constants (cgkp, cgks, dgkp, dgks) * w 13 * w 14 * w 15 10 32 54 7 * w 6 * w 9 * w 8 * w 11 * w 10 * w * www ww ww 12 * * * * * * bit : initial value : r/w : note: * initial value is uncertain. these registers are 16-bit write-only buffers that se t accumulation gain of the digital filter. only a word access is valid. accumulation gain can be set to gain 1 value as maximum value. if a byte access is attempted, correct operation is not guaran teed. if a read is atte mpted, an undetermined value is read out. these registers are not initialized by a reset or in standby mode. be sure to write data in them before processing starts. in the digital filter, output gain and accumulation gain can be adjusted separately. take output gain into account when setting accumulation gain. coefficients (cap, cbp, cas, cbs, dap, dbp, das, dbs) * w 13 * w 14 * w 15 10 32 54 7 * w 6 * w 9 * w 8 * w 11 * w 10 * w * www ww ww 12 * * * * * * bit : initial value : r/w : note: * initial value is uncertain. these registers are 16-bit write-only buffers that determine the cutoff frequency f1 and f2. only a word access is valid. if a byte access is attempted, co rrect operation is not guaranteed. if a read is attempted, an undetermined value is read out. these registers are not initialized by a reset or in standby mode. be sure to write data in them before processing starts. in the digital filter, output gain and accumulation gain can be adjusted separately. take output gain into account when setting accumulation gain. section 26 servo circuits rev.2.00 jan. 15, 2007 page 666 of 1174 rej09b0329-0200 offset (cofp, cofs, dofp, dofs) * w 13 * w 14 * w 15 10 32 54 7 * w 6 * w 9 * w 8 * w 11 * w 10 * w * www ww ww 12 * * * * * * bit : initial value : r/w : note: * initial value is uncertain. these registers are 16-bit write-only buffers that set offset level of digital filter output. only a word access is valid. if a byte access is attempted, corr ect operation is not guaranteed. if a read is attempted, an undetermined value is read out. these registers are not initialized by a reset or in standby mode. be sure to write data in them before processing starts. in this digital filter, output gain adjustment ( 1, 2, 4, 8, 16, 32, 64) after offset adding is enabled. take output gain into account when setting accumulation gain. delay initialization register (czp, czs, dzp, dzs) 1 ? 13 1 ? 14 1 ? 15 10 32 54 7 0 w 6 0 w 9 0 w 8 0 w 11 0 w 10 0 w 1 ?ww ww ww 12 0 0 0 0 0 0 bit : initial value : r/w : the delay initialization register is a 16-bit write-only register. only a word access is valid. if a byte access is attempted, correct operation is no t guaranteed. if a read is attempted, an undetermined value is read out. it is initialized to h'f000 by a reset, or in sta nd-by or module stop mode. the msb of 12-bit data (bit 11) is a sign bit. loading to z -1 is performed automatically by bits 4 and 3 of cfic and dfic (czpon, czson, dzpon, dzson). writing in register is always available, but loading in z -1 is not possible when the digital filter is performing computation in relation to such register. in such a case, loading to z -1 will be done the next time computation begins. section 26 servo circuits rev.2.00 jan. 15, 2007 page 667 of 1174 rej09b0329-0200 drum system digital filt er control register (dfic) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 5 0 6 0 7 ? ? r/w r/w r/(w) dpha r/(w) * drov dzpon dzson dsg2 dsg1 dsg0 1 note: * only 0 can be written bit : initial value : r/w : dfic is an 8-bit read/write register that controls the status of the drum digital filter and operating mode. only a byte access is valid. if a word acce ss is attempted, correct operation is not guaranteed. dfic is initialized to h'80 by a rese t, and in standby mode and module stop mode. bit 7 ? reserved: cannot be modified and is always read as 1. bit 6 ? drum system range over flag (drov): this flag is set to 1 when the result of a filter computation exceeds 12 bits in width. to clear this flag, write 0 after reading 1. bit 6 drov description 0 indicates that the filter computation result did not exceed 12 bits (initial value) 1 indicates that the filter computation result exceeded 12 bits bit 5 ? drum phase system filter computation start bit (dpha): starts or stops filter processing for drum phase system. bit 5 dpha description 0 phase system filter computations are disabled phase computation result (y) is not added to es (see figure 26.39) (initial value) 1 phase system filter computations are enabled section 26 servo circuits rev.2.00 jan. 15, 2007 page 668 of 1174 rej09b0329-0200 bit 4 ? drum phase system z -1 initialization bit (dzpon): reflects the dzp value on z -1 of the phase system when computation processing of the drum phase system begins. if 1 is written, it is reflected on the computation, and then cleared to 0. set this bit after writing data to dzp. bit 4 dzpon description 0 dzp value is not reflected on z -1 of the phase system (initial value) 1 dzp value is reflected on z -1 of the phase system bit 3 ? drum speed system z -1 initialization bit (dzson): reflects the dzs value on z -1 of the speed system when computation processing of the drum speed system begins. if 1 is written, it is reflected on the computation, and then cleared to 0. set this bit after writing data to dzs. bit 3 dzson description 0 dzs value is not reflected on z -1 of the speed system (initial value) 1 dzs value is reflected on z -1 of the speed system bits 2 to 0 ? drum system output gain control bits (dsg2 to dsg0): control the gain output to drmpwm. bit 2 bit 1 bit 0 dsg2 dsg1 dsg0 description 0 1 (initial value) 0 1 2 0 4 0 1 1 8 1 0 16 0 1 ( 32) * 1 0 ( 64) * 1 invalid (do not use this setting) note: * setting optional. section 26 servo circuits rev.2.00 jan. 15, 2007 page 669 of 1174 rej09b0329-0200 capstan system digital filt er control register (cfic) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 5 0 6 0 7 ? ? r/w r/w r/(w) dpha r/(w) * drov dzpon dzson dsg2 dsg1 dsg0 1 note: * only 0 can be written bit : initial value : r/w : cfic is an 8-bit read/write register that controls the status of the capstan digital filter and operating mode. only a byte access is valid. if a wo rd access is attempted, correct operation is not guaranteed. cfic is initialized to h'80 by a re set, and in standby mode and module stop mode. bit 7 ? reserved: cannot be modified and is always read as 1. bit 6 ? capstan system range over flag (crov): this flag is set to 1 when the result of a filter computation exceeds 12 bits in width. to clear this flag, write 0 after reading 1. bit 6 drov description 0 indicates that the filter computation result did not exceed 12 bits. (initial value) 1 indicates that the filter computation result exceeded 12 bits. bit 5 ? capstan phase system filter start (cpha): starts or stops filter processing for capstan phase system. bit 5 cpha description 0 phase filter computations are disabled. phase computation result (y) is not added to es (see figure 26.39). (initial value) 1 phase filter computations are enabled. bit 4 ? capstan phase system z -1 initialization bit (czpon): reflects the czp value on z -1 of the capstan phase system when computation processing of the phase system begins. if 1 is written, it is reflected on the computation, and then cleared to 0. set this bit after writing data to czp. bit 4 czpon description 0 czp value is not reflected on z -1 of the phase system (initial value) 1 czp value is reflected on z -1 of the phase system section 26 servo circuits rev.2.00 jan. 15, 2007 page 670 of 1174 rej09b0329-0200 bit 3 ? capstan speed system z -1 initialization bit (czson): reflects the czs value on z -1 of the capstan speed system when computation processing of the speed system begins. if 1 is written, it is reflected on the computation, and then cleared to 0. set this bit after writing data to czs. bit 3 czson description 0 czs value is not reflected on z -1 of the speed system (initial value) 1 czs value is reflected on z -1 of the speed system bits 2 to 0 ? capstan system gain control bits (csg2 to csg0): control the gain output to cappwm. bit 1 bit 2 bit 0 csg2 csg1 csg0 description 0 1 (initial value) 0 1 2 0 4 0 1 1 8 1 0 16 0 1 ( 32) * 1 0 ( 64) * 1 invalid (do not use this setting) note: * setting optional section 26 servo circuits rev.2.00 jan. 15, 2007 page 671 of 1174 rej09b0329-0200 digital filter control register (dfucr) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 5 0 6 7 ? ? ? ? r/w r/w r/w pton cp/dp cfeps dfeps cfess dfess 11 bit : initial value : r/w : dfucr is an 8-bit read/write register which controls the operation of the digital filter. only a byte access is valid. if a word access is attempted, correct operation is not guaranteed. it is initialized to h'00 by a reset, or in stand-by or module stop mode. bits 7 and 6 ? reserved: cannot be modified and are always read as 1. bit 5 ? phase system computation result pwm output bit (pton): outputs the computation results of only the phase system to pwm. (the computation results of the drum phase system is output to cappwm pin, and that of the capstan phase system is output to drmpwm pin.) bit 5 pton description 0 outputs the results of ordinary computation of the filter to pwm pin (initial value) 1 outputs the computation results of only the phase system to pwm pin bit 4 ? pwm output selection bit (cp/ dp ): selects whether the phase system computation results when pton was set to 1 is output to the drum or capstan. the pwm of the selected side outputs ordinary filter computation results (speed system of mix). bit 4 cp/ dp description 0 outputs the drum phase system computat ion results (drmpwm) (initial value) 1 outputs the capstan phase system computation results (cappwm) section 26 servo circuits rev.2.00 jan. 15, 2007 page 672 of 1174 rej09b0329-0200 bit 3 ? capstan phase system error data transfer bit (cfeps): transfers the capstan phase system error data to the digital filter when the data write is enforced. bit 3 cfeps description 0 error data is transferred by dvcfg2 signal latching. (initial value) 1 error data is transferred when the data is written. bit 2 ? drum phase system error data transfer bit (dfeps): transfers the drum phase system error data to the digital filter when the data write is enforced. bit 2 dfeps description 0 error data is transferred by hsw (nhsw) signal latching. (initial value) 1 error data is transferred when the data is written. bit 1 ? capstan speed system error data transfer bit (cfess): transfers the capstan phase system error data to the digital filter when the data write is enforced. bit 1 cfess description 0 error data is transferred by dvcfg signal latching. (initial value) 1 error data is transferred when the data is written. bit 0 ? drum speed system error data transfer bit (dfess): transfers the drum speed system error data to the digital filter when the data write is enforced. bit 0 dfess description 0 error data is transferred by ncdfg signal latching. (initial value) 1 error data is transferred when the data is written. section 26 servo circuits rev.2.00 jan. 15, 2007 page 673 of 1174 rej09b0329-0200 26.11.6 filter characteristics ? lag-lead filter a filter required for a servo loop is built in the hardware. this filter uses iir (infinite impulse response) type digital filter (another type of the di gital filter is fir, i.e. finite impulse response type). this digital filter circuit implements a lag-lead filter, as shown in figure 26.40. r1 r2 c + input output figure 26.40 lag-lead filter the transfer function is expressed by the following equation: s 1 + 2f 2 transfer function g (s) = s 1 + 2 f 1 f 1 = 1/2 c (r1 + r2) f 2 = 1/2 cr2 section 26 servo circuits rev.2.00 jan. 15, 2007 page 674 of 1174 rej09b0329-0200 ? frequency characteristics the computation circuit repeats computation of the function, which is obtained by s-z conversion according to bi-linear approximation of the transfer function on the s-plane. figure 26.41 shows the frequency characteristics of the lag-lead filter. f1 0 f2 frequency (hz) 20log(f1/f2) gain(db) phase(deg) figure 26.41 frequency characteristics of the lag-lead filter the pulse transfer function g (z) is obtained by the bi-linear approximation of the transfer g (s). in the transfer g (s), s = 2 ts 1 ? z ?1 1 + z ?1 where, assumed that z -1 = e -j ts , g (z) = g 2 ts 1 + az ?1 1 + bz ?1 g (z) = ts + 1 f 2 ts + 1 f 1 a = ts ? 1 f 2 ts + 1 f 2 b = ts ? 1 f 1 ts + 1 f 1 ts: sampling cycle (sec) section 26 servo circuits rev.2.00 jan. 15, 2007 page 675 of 1174 rej09b0329-0200 26.11.7 operations in case of transient response in case of transient response when the motor is activated, the digital f ilter computation circuit must prevent computation due to a large error. the convergence of the computations becomes slow and servo retraction deteriorates if a large error is input to the filter circuit when it is performing repeated computations. to prevent them from occurring, operate the filter (set constants a and b) after pulling in the speed and phase within a certain range of error, initialize the z -1 (set initial values in czp, czs, dzp, dzs)(see section 26.11.8, initialization of z -1 ), or use the error data limit function (see section 26.6, drum speed error detector, and section 26.8, capstan speed error detector). 26.11.8 initialization of z -1 z -1 can be initialized by its delay initialization register (czp, czs, dzp, dzs). loading to z -1 is performed automatically by bits 4 and 3 of cfic and dfic (czpon, czson, dzpon, dzson). writing in register is always available, but loading in z -1 is not possible when the digital filter is performing computation in relation to such register. in such a case, loading to z -1 will be done when the next time computation begins. fi gure 26.42 shows the initialization circuit of z -1 . the delay initialization register sets 12-bit data. the msb (bit 11) is a sign bit. z -1 has 24 bits for integrals and 8 bits for decimals. accordingly, the same value as the sign bit should be set in the 13 bits on the msb side of z -1 , and 0 in the entire decimal section. example: value set for the delay initialization register value set for z -1 msb 0 msb set here the value in the sign bit fixed 1 0000000000 1111111111111 0 0 0 0 0 0 0 0 0 0 0 00000000 section 26 servo circuits rev.2.00 jan. 15, 2007 page 676 of 1174 rej09b0329-0200 w w internal bus z -1 initiali- zation bit dzson dzpon czson czson w 16 16 12 24 8 w delay initialization register z -1 usn -+ res note: msb of 12-bit data to be written in the delay initialization register is a sign bit. usn-1 + + xn vn dbs15 to 0 dbp15 to 0 cbs15 to 0 cbp15 to 0 dzs11 to 0 dzp11 to 0 czs11 to 0 czp11 to 0 das15 to 0 dap15 to 0 cas15 to 0 cap15 to 0 ab figure 26.42 z -1 initialization circuit section 26 servo circuits rev.2.00 jan. 15, 2007 page 677 of 1174 rej09b0329-0200 26.12 additional v signal generator 26.12.1 overview the additional v signal generator outputs an additional vertical sync signal to take the place of vsync in special playback. it is activated at both edges of the hsw signal output by the head- switch timing generator. the head-switch timing generator also outputs a v pulse signal containing the additional vertical sync pulse itself, and an m level signal that defines the width of the additional vertical sync signal including the equalizing pulses. the additional v signal is output at a three-level output pin (v pulse). figure 26.43 shows the additional v signal control circuit. csync additional v pulse osch vpulse signal mlevel signal sync signal detector hsw timing generator additional v pulse generator figure 26.43 additional v pulse control circuit hsw timing generator: this circuit generates signals that are synchronized with head switching. it should be programmed to generate th e mlevel and vpulse signals at edges of the hsw signal (videoff). for details, see section 26.4, hsw (head-switch) timing generator. sync signal detector: this circuit detects pulses of the width specified by vtr or htr from the signal input at the csync pin and generates an internal horizontal sync signal (osch). the sync signal detector has an interpolation function, so osch has a regular period even if there are horizontal sync dropouts in the signal received at the pin. for details, see section 26.15, sync signal detector. section 26 servo circuits rev.2.00 jan. 15, 2007 page 678 of 1174 rej09b0329-0200 26.12.2 pin configuration table 26.16 summarizes the pin configuration of the additional v signal. table 26.16 pin configuration name abbrev. i/o function additional v pulse pin vpulse output output of additional v signal synchronized to video ff 26.12.3 register configuration table 26.17 summarizes the register that controls the additional v signal. table 26.17 register configuration name abbrev. r/w size initial value address additional v control register addvr r/w byte h'e0 h'd06f 26.12.4 register description additional v control register (addvr) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 5 1 6 7 ? ? ? ? ? ? r/w r/w hmsk hi-z cut vpon pol 11 bit : initial value : r/w : addvr is an 8-bit read/write regi ster. it is initialized to h'e0 by a reset, and in standby mode. bits 7 to 5 ? reserved: cannot be modified and are always read as 1. bit 4 ? osch mask (hmsk): masks the osch signal in the additional v signal. bit 4 hmsk description 0 osch is added in (initial value) 1 osch is not added in section 26 servo circuits rev.2.00 jan. 15, 2007 page 679 of 1174 rej09b0329-0200 bit 3 ? high impedance (hi-z): set to 1 when the intermediate level is generated by an external circuit. bit 3 hi-z description 0 vpulse is a three-level output pin (initial value) 1 vpulse is a three-state output pin (high, low, or high-impedance) bits 2 to 0 ? additional v output control (cut, vpon, pol): these bits control the output at the additional v pin. bit 2 bit 1 bit 0 cut vpon pol description 0 * low level (initial value) 0 negative polarity (see figure 26.46) 0 1 1 positive polarity (see figure 26.45) 1 * 0 intermediate level (high impedance if hi-z bit = 1) 1 high level legend: * don?t care. section 26 servo circuits rev.2.00 jan. 15, 2007 page 680 of 1174 rej09b0329-0200 26.12.5 additional v pulse signal figure 26.44 shows the additional v pulse signal. the m level and v pulse signals are generated by the head-switch timing generator. the osch signal is combined with these to produce equalizing pulses. the polarity can be selected by the pol bit in the additional v control register (addvr). v pulse pin outputs a low level by a reset, and in standby mode and module stop mode. r/w r/w ?addvr ?addvr r/w internal bus r/w r/w cut vpon hmsk pol hi-z stby v cc v cc v ss v ss rs rs v pulse pin osch v pulse m level note: stby : power-down mode signal v pulse, m level : signal from the hsw timing generator rs : voltage division resistance (20 k : reference value) figure 26.44 additional v pulse pin section 26 servo circuits rev.2.00 jan. 15, 2007 page 681 of 1174 rej09b0329-0200 additional v pulses when sync signal is not detected: with additional v pulses, the pulse signal (osch) detected by the sync signal detector is superimposed on the v pulse and mlevel signals generated by the head-switch timing generator. if there is a lot of noise in the input sync signal (csync), or a pulse is missing, osch will be a complementary pulse, and therefore an h pulse of the period set in hrtr and hpwr will be superimposed. in this case, there may be slight timing drift compared with the normal sync signal, depending on the hrtr and hpwr setting, with resultant discontinuity. if no sync signal is input, the additional v pulse is generated as a complementary pulse. set the sync signal detector registers and activate the sync signal detector by manipulating the syct bit in the sync signal control register (syncr). see section 26.15.7, activation of the sync signal detector. figures 26.45 and 26.46 show the additional v pulse timing charts. hsw signal edge osch notes: vpon = 1 cut = 0 pol = 1 additional v pulse vpulse signal mlevel signal figure 26.45 additional v pulse when positive polarity is specified section 26 servo circuits rev.2.00 jan. 15, 2007 page 682 of 1174 rej09b0329-0200 hsw signal edge osch notes: vpon = 1 cut = 0 pol = 0 additional v pulse v pulse signal m level signal figure 26.46 additional v pulse when negative polarity is specified section 26 servo circuits rev.2.00 jan. 15, 2007 page 683 of 1174 rej09b0329-0200 26.13 ctl circuit 26.13.1 overview the ctl circuit includes a schmitt amplifier that amplifies and reshapes the ctl input, then outputs it as the pb-ctl signal to the servo, linear time counter, and other circuits. the pb-ctl signal is also sent to a duty discriminator in the ctl circuit that detects and records viss, asm, and vass marks. a rec-ctl amplifier is included in the record circuits. detection and recording whether the ctl pulse pattern is long or short can also be enabled to correspond to the wide-aspect. the following operating modes can be selected by settings in the ctl mode register: ? duty discrimination viss detect, asm detect, vass detect, l/s bit pattern detect ? ctl record viss record, asm record, vass r ecord, l/s bit pattern record ? rewrite trapezoid waveform generator section 26 servo circuits rev.2.00 jan. 15, 2007 page 684 of 1174 rej09b0329-0200 26.13.2 block diagram figure 26.47 shows a block diagram of the ctl circuit. + - pb-ctl fw/rv ctl(-) ctl(+) schmitt amplifier ctl mode ctl detector duty dis- criminator bit pattern register viss detect viss control circuit viss write duty i/o flag write control circuit rec- ctl amplifier internal bus ref30x irrctl figure 26.47 block diagram of ctl circuit section 26 servo circuits rev.2.00 jan. 15, 2007 page 685 of 1174 rej09b0329-0200 26.13.3 pin configuration table 26.18 summarizes the pin configuration of the ctl circuit. table 26.18 pin configuration name abbrev. i/o function ctl (+) i/o pin ctl (+) i/o ctl signal input/output ctl (?) i/o pin ctl (?) i/o ctl signal input/output ctl bias input pin ctl bias input ctl primary amplifier bias supply ctl amp (o) output pin ctlamp (o) output ctl amplifier output ctl smt (i) input pin ctlsmt (i) input ctl schmitt amplifier input ctl fb input pin ctl fb input ctl amplifier high-range characteristics control ctl ref output pin ctl ref output ctl amplifier reference voltage output 26.13.4 register configuration table 26.19 shows the register configuration of the ctl circuit. table 26.19 register configuration name abbrev. r/w size initial value address ctl control register ctcr r/w byte h'30 h'd080 ctl mode register ctlm r/w byte h'00 h'd081 rec-ctl duty data register 1 rcdr1 w word h'f000 h'd082 rec-ctl duty data register 2 rcdr2 w word h'f000 h'd084 rec-ctl duty data register 3 rcdr3 w word h'f000 h'd086 rec-ctl duty data register 4 rcdr4 w word h'f000 h'd088 rec-ctl duty data register 5 rcdr5 w word h'f000 h'd08a duty i/o register di/o r/w byte h'f1 h'd08c bit pattern register btpr r/w byte h'ff h'd08d section 26 servo circuits rev.2.00 jan. 15, 2007 page 686 of 1174 rej09b0329-0200 26.13.5 register description ctl control register (ctcr) 0 0 1 0 r 2 0 w 3 0 4 1 w 5 1 6 0 7 w w w fslb w fslc 0 w nt/pl fsla ccs lctl unctl slwm bit : initial value : r/w : ctcr is an 8-bit read/write register that cont rols pb-ctl rewrite and sets the slow mode. when ctl pulse cannot be detected with the input amplifier gain set at the ctl gain control register (ctlgr) in pb-ctl circuit, bit 1 (unctl) of ctcr is set to 1. it is automatically cleared to 0 when ctl pulse is detected. bit 1 is read-only, and the rest are write-only. if a read is attempted to a write-only bit, an undetermined value is read out. ctcr is initialized to h'30 by a reset, and in standby and module stop mode. bit 7 ? ntsc/pal select (nt/pl): selects the period of the rewrite circuit. bit 7 nt/pl description 0 ntsc mode (frame rate: 30 hz) (initial value) 1 pal mode (frame rate: 25 hz) bits 6 to 4 ? frequency select (fsla, fslb, fslc); these bits select the operating frequency of the ctl write circuit. they should be set according to f osc . bit 6 bit 5 bit 3 fslc fslb fsla description 0 reserved (do not use this setting) 0 1 reserved (do not use this setting) 0 fosc = 8 mhz 0 1 1 fosc = 10 mhz (initial value) 1 * * reserved (do not use this setting) legend: * don?t care. section 26 servo circuits rev.2.00 jan. 15, 2007 page 687 of 1174 rej09b0329-0200 bits 3 ? clock source select bit (ccs): selects clock source of ctl. bit 3 ccs description 0 s (initial value) 1 s/2 bit 2 ? long ctl bit (lctl): sets the long ctl detection mode. bit 2 lctl description 0 clock source (ccs) operates at the setting value (initial value) 1 clock source (ccs) operates for further 8-division after operating at the setting value bit 1 ? ctl undetected bit (unctl): indicates the ctl pulse det ection status at the ctl input amplifier sensitivity set at the ctl gain control register. bit 1 unctl description 0 detected (initial value) 1 undetected bit 0 ? mode select bit (slwm): selects ctl mode. bit 0 slwm description 0 normal mode (initial value) 1 slow mode section 26 servo circuits rev.2.00 jan. 15, 2007 page 688 of 1174 rej09b0329-0200 ctl mode register (ctlm) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 5 0 6 0 7 r/w r/w r/w fw/rv r/w rec/pb 0 r/w asm md4 md3 md2 md1 md0 bit : initial value : r/w : ctlm is an 8-bit read/write register that controls the operating state of the ctl circuit. if 1 is written in bits md3 and md2, they will be cleared to 0 one cycle ( ) later. ctlm is initialized to h'00 by a reset, and in standby mode and module stop mode. when ctl is being stopped, only bits 7, 6 and 5 operate. note: do not set any value other than the setting value for each mode (see table 26.20, ctl mode functions). bits 7 and 6 ? record/playback mode bits (asm, rec/ pb ): these bits switch between record and playback. combined with bits 4 to 0 (md4 to md0), they support the viss, vass, and asm mark functions. bit 7 bit 6 asm rec/ pb description 0 playback mode (initial value) 0 1 record mode 1 0 assemble mode 1 invalid (do not set) bit 5 ? direction (fw/rv): selects the direction in playback. clear this bit to 0 during record. figure 26.48 shows the pb-ctl signal. bit 5 fw/rv description 0 forward (initial value) 1 reverse section 26 servo circuits rev.2.00 jan. 15, 2007 page 689 of 1174 rej09b0329-0200 ctl input pb-ctl fwd rev figure 26.48 internal pb-ctl signal in forward and reverse bits 4 to 0 ? ctl mode select (md4 to md0): these bits select the detect, record, and rewrite modes for viss, vass, and asm marks. if 1 is written in bits md3 and md2, they will be cleared to 0 one cycle ( ) later. the 5 bits from md4 to md0 are used in combination with bits 7 and 6 (asm and rec/ pb ). table 26.20 describes the modes. table 26.20 ctl mode functions bit asm r/ p f/r md4 md3 md2 md1 md0 mode description 0 0 0/1 0 0 0 0 0 vass detect (duty detect) pb-ctl duty discrimination (initial value) ? duty i/o flag is set to 1 if duty 44% is detected ? duty i/o flag is cleared to 0 if duty < 44% is detected ? interrupt request is generated when one ctl pulse has been detected 0 1 0 0 0 0 0 0 vass record ? if 0 is written in the duty i/o flag, rec-ctl is generated and recorded with the duty cycle set by register rcdr2 or rcdr3 ? if 1 is written in the duty i/o flag, rec-ctl is generated and recorded with the duty cycle set by register rcdr4 or rcdr5 0 0 0 1 0 0 1 0 vass rewrite same as above (vass record); trapezoid waveform circuit operation section 26 servo circuits rev.2.00 jan. 15, 2007 page 690 of 1174 rej09b0329-0200 bit asm r/ p f/r md4 md3 md2 md1 md0 mode description 0 0 0/1 0 1 0 0 1 viss detect (index detect) ? the duty i/o flag is set to 1 at the point of write access to register ctlm ? the 1 pulses recognized by the duty discrimination circuit are counted in the viss control circuit ? the duty i/o flag is cleared to 0, indicating viss detection, when the value set at vctr register is repeatedly detected ? an interrupt request is generated when viss is detected 0 1 0 0 0 1 0 1 viss record (index record) ? 64 pulse data with 0 pulse data at both edge are written (index record) ? the index bit string is written through the duty i/o flag ? an interrupt request is generated at the end of viss recording 0 0 0 0 0 1 0 1 viss rewrite same as above (viss record; trapezoid waveform circuit operation) 0 0 0 1 0 0 0 0 viss initialize viss write is forcibly aborted 1 0 0/1 0 0 0 0 0 asm mark detect asm mark detection ? the duty i/o flag is cleared to 0 when pb-ctl duty 66% is detected ? an interrupt request is generated when an asm mark is detected 0 1 0 1 0 0 0 0 asm mark record ? an asm mark is recorded by writing 0 in the duty i/o flag ? an interrupts is requested for every one ctl pulse ? rec-ctl is generated and recorded with the duty cycle set by register rcdr3 section 26 servo circuits rev.2.00 jan. 15, 2007 page 691 of 1174 rej09b0329-0200 rec-ctl duty data register 1 (rcdr1) 13 14 15 10 32 54 76 98 11 10 cmt11 w 12 1 1 11 ? ? ?? ? ? ?? 0 cmt10 w 0 cmt13 w 0 cmt12 w 0 cmt15 w 0 cmt14 w 0 cmt17 w 0 cmt16 w 0 cmt19 w 0 cmt18 w 0 cmt1b w 0 cmt1a w 0 bit : initial value : r/w : rcdr1 is a 12-bit write-only register that sets the rec-ctl rising timing. this setting is valid only for recording and rewriting, and is not used in detection. only a word access is valid. if a byte access is atte mpted, correct operation is not guaranteed. if a read is attempted, an undetermined value is read out. bits 15 to 12 are reserved and are not affected by write access. rcdr1 is initialized to h'f000 by a reset, and in standby mode, module stop mode and ctl stop mode. the value to set in rcdr1 can be calculated from the transition timing t1 and the servo clock frequency s by the equation given below. see figure 26.60. any transition timing can be set. the timing should be selected with attention to playback tracking compensation and the latch timing for phase control. rcdr1 = t1 s/64 s is the servo clock frequency (= f osc /2) in hz, and t1 is the set timing (s). note: 0 cannot be set to rcdr1. set a value 1 or above. section 26 servo circuits rev.2.00 jan. 15, 2007 page 692 of 1174 rej09b0329-0200 rec-ctl duty data register 2 (rcdr2) 1111 13 14 15 10 32 54 76 98 11 10 cmt21 w 12 ? ? ?? ? ? ?? 0 cmt20 w 0 cmt23 w 0 cmt22 w 0 cmt25 w 0 cmt24 w 0 cmt27 w 0 cmt26 w 0 cmt29 w 0 cmt28 w 0 cmt2b w 0 cmt2a w 0 bit : initial value : r/w : rcdr2 is a 12-bit write-only register that sets 1 pulse (short) falling timing of rec-ctl at recording and rewriting, and detects long/short pulses at detecting. only a word access is valid. if a byte access is atte mpted, correct operation is not guaranteed. if a read is attempted, an undetermined value is read out. bits 15 to 12 are reserved and are not affected by write access. rcdr2 is initialized to h'f000 by a reset, and in standby mode, module stop mode, and ctl stop mode. at recording, the value to set in rcdr2 can be calculated from the transition timing t2 and the servo clock frequency s by the equation given below, and the set value should be 25% of the duty obtained by the equation. see figure 26.60. rcdr2 = t2 s/64 s is the servo clock frequency (= f osc /2) in hz, and t2 is the set timing (s). at bit pattern detection, set the 1 pulse long/short threshold value at fwd. see figure 26.56. rcdr2 = t2' s/64 s is the servo clock frequency (= f osc /2) in hz, and t2' is the 1 pulse long/short threshold value at fwd (s). section 26 servo circuits rev.2.00 jan. 15, 2007 page 693 of 1174 rej09b0329-0200 rec-ctl duty data register 3 (rcdr3) 1111 13 14 15 10 32 54 76 98 11 10 cmt31 w 12 ? ? ?? ? ? ?? 0 cmt30 w 0 cmt33 w 0 cmt32 w 0 cmt35 w 0 cmt34 w 0 cmt37 w 0 cmt36 w 0 cmt39 w 0 cmt38 w 0 cmt3b w 0 cmt3a w 0 bit : initial value : r/w : rcdr3 is a 12-bit write-only register that sets 1 pulse (long) and assemble mark falling timing of rec-ctl at recording and rewriting, and detects long/short pulses at detecting. only a word access is valid. if a byte access is atte mpted, correct operation is not guaranteed. if a read is attempted, an undetermined value is read out. bits 15 to 12 are reserved and are not affected by write access. rcdr3 is initialized to h'f000 by a reset, and in standby mode, module stop mode, and ctl stop mode. at recording, the value to set in rcdr3 can be calculated from the transition timing t3 and the servo clock frequency s by the equation given below. the set value should be 30 percent of the duty when the rcdr3 is used for rec-ctl 1 pulse, and 67 to 70 percent when used for assemble mark. the set value must not exceed the frequency of ref30x. see figure 26.60. rcdr3 = t3 s/64 s is the servo clock frequency (= f osc /2) in hz, and t3 is the set timing (s). at bit pattern detection, set the 0 pulse long/short threshold value at fwd. see figure 26.56. rcdr3 = t3' s/64 s is the servo clock frequency (= f osc /2) in hz, and t3' is the 0 pulse long/short threshold value at fwd (s). section 26 servo circuits rev.2.00 jan. 15, 2007 page 694 of 1174 rej09b0329-0200 rec-ctl duty data register 4 (rcdr4) 1111 13 14 15 10 32 54 76 98 11 10 cmt41 w 12 ? ? ?? ? ? ?? 0 cmt40 w 0 cmt43 w 0 cmt42 w 0 cmt45 w 0 cmt44 w 0 cmt47 w 0 cmt46 w 0 cmt49 w 0 cmt48 w 0 cmt4b w 0 cmt4a w 0 bit : initial value : r/w : rcdr4 is a 12-bit write-only register that sets the timing of falling edge of the 0 pulse (short) of rec-ctl in record or rewrite mode. in detection mode, it is used to detect the long/short pulse. only a word access is valid. if a byte access is atte mpted, correct operation is not guaranteed. if a read is attempted, an undetermined value is read out. bits 15 to 12 are reserved, and no write in them is valid. it is initialized to h'f000 by a reset, stand-by or module stop. in record mode, set a value with the 57.5 percent duty cycle obtained from the set time t4 corresponding to the frequency s according to the following e quation. see figure 26.60. rcdr4 = t4 s/64 is the servo clock frequency (= f osc /2) in hz, and t4 is the set timing (s). at bit pattern detection, set the 0 pulse long/short threshold value at rev. see figure 26.56. rcdr4 = h'fff ? (t4' s/80) s is the servo clock frequency (= f osc /2) in hz, and t4' is the 0 pulse long/short threshold value at rev (s). section 26 servo circuits rev.2.00 jan. 15, 2007 page 695 of 1174 rej09b0329-0200 rec-ctl duty data register 5 (rcdr5) 1111 13 14 15 10 32 54 76 98 11 10 cmt51 w 12 ? ? ?? ? ? ?? 0 cmt50 w 0 cmt53 w 0 cmt52 w 0 cmt55 w 0 cmt54 w 0 cmt57 w 0 cmt56 w 0 cmt59 w 0 cmt58 w 0 cmt5b w 0 cmt5a w 0 bit : initial value : r/w : rcdr5 is a 12-bit write-only register that sets the timing of falling edge of the 0 pulse (short) of rec-ctl in record or rewrite mode. in detection mode, it is used to detect the long/short pulse. only a word access is valid. if a byte access is atte mpted, correct operation is not guaranteed. if a read is attempted, an undetermined value is read out. bits 15 to 12 are reserved, and no write in them is valid. it is initialized to h'f000 by a reset, stand-by or module stop. in record mode, set a value with the 62.5 percent duty cycle obtained from the set time t5 corresponding to the frequency s according to the following e quation. see figure 26.60. rcdr5 = t5 s/64 is the servo clock frequency (= f osc /2) in hz, and t5 is the set timing (s). at bit pattern detection, set the 1 pulse long/short threshold value at rev. see figure 26.56. rcdr5 = h'fff ? (t5' s/80) s is the servo clock frequency (= f osc /2) in hz, and t5' is the 1 pulse long/short threshold value at rev (s). section 26 servo circuits rev.2.00 jan. 15, 2007 page 696 of 1174 rej09b0329-0200 duty i/o register (di/o) 0 1 1 0 r/(w) * 2 0 w 3 0 4 ? ? 5 1 6 7 r/w w w vctr0 1 w vctr1 1 w vctr2 bpon bps bpf di/o 1 note: * only 0 can be written bit : initial value : r/w : di/o is an 8-bit register that confirms and dete rmines the operating status of the ctl circuit. it is initialized to h'f1 by a reset, and in standby mode, module stop mode, and ctl stop mode. bits 7 to 5 ? viss interrupt setting bit (vctr2 to vctr0): combination of vctr2, vctr1 and vctr0 sets number of 1 pulse detection in viss detection mode. detecting the set number of pulse detection is considered as viss detecti on, and an interrupt request is generated. note: when changing the detection pulse number during viss detection, initialize viss first, then resume the viss detection setting. bit 7 bit 6 bit 5 vctr2 vctr1 vctr0 number of 1-pulse for detection 0 2 0 1 4 (sync mark) 0 6 0 1 1 8 (mark a, short) 1 0 12 (mark a, long) 0 1 16 1 0 24 (mark b) 1 32 bit 4 ? reserved: cannot be modified and is always read as 1. section 26 servo circuits rev.2.00 jan. 15, 2007 page 697 of 1174 rej09b0329-0200 bit 3 ? bit pattern detection on/off bit (bpon): determines on or off of bit pattern detection. note: when writing 1 to bpon bit, be sure to set appropriate data to rcdr 2 to 5 beforehand. bit 3 bpon description 0 bit pattern detection off (initial value) 1 bit pattern detection on bit 2 ? bit pattern detection start bit (bps): starts 8-bit bit pattern detection. when 1 is written to this bit, it returns to 0 after one cycle. writing 0 to this bit does not affect operation. bit 2 bps description 0 normal status (initial value) 1 starts 8-bit bit pattern detection bit 1 ? bit pattern detection flag (bpf): sets flag every time 8-bit pb -ctl is detected in pb or asm mode. to clear flag, write 0 after reading 1. bit 1 bpf description 0 bit pattern (8-bit) is not detected (initial value) 1 bit pattern (8-bit) is detected bit 0 ? duty i/o register (di/o): this flag has different functions for record and playback. in viss detect mode, vass detect mode, and asm mark detect mode, this flag indicates the detection result. in viss record or rewrite mode, this flag controls the write control circuit so as to write an index code, operating according to a control signal from the viss control circuit. in vass record or rewrite mode and asm mark record mode, this flag is used for write control, one ctl pulse at a time. this bit can always be written to, but this does not affect the write control circuit in modes other than viss record, rewr ite, and asm record. section 26 servo circuits rev.2.00 jan. 15, 2007 page 698 of 1174 rej09b0329-0200 ? viss detect mode and vass detect mode: the duty i/o flag indicates the result of duty discrimination. the duty i/o flag is 1 when the duty cycle of the pb-ctl signal is above 44% (a 0 pulse in the ctl signal). the duty i/o flag is 0 when the duty cycle of the pb-ctl signal is below 43% (a 1 pulse in the ctl signal). ? asm mark detect mode: the duty i/o flag indicates the result of duty discrimination. the duty i/o flag is 0 when the duty cycle of the pb-ctl signal is above 66% (when an asm mark is detected). the duty i/o flag is 1 when the duty cycle of the pb-ctl signal is below 65% (when an asm mark is not detected). ? viss record mode and viss rewr ite mode: the duty i/o flag operates according to a control signal from the viss control circuit, and controls the write control circuit so as to write an index code. the write timing is set in the rec-ctl duty data registers (rcdr1 to rcdr5). for viss recording, registers rcdr1 to rcdr5 are set with reference to ref30x. for viss rewrite, rcdr2 to rcdr5 are set with reference to the low-to-high transition of the previously recorded ctl signal, and the write is carried out through the trapezoid waveform generator. set the duty timing for a 1 pulse (short) in rcdr2, for a 1 pulse (long) in rcdr3, for a 0 pulse (short) in rcdr4, and for a 0 pulse (long) in rcdr5. while an index code is being written, the value of the bit being written can be read by reading the duty i/o flag. if the ctl signal currently being written is a 0 pulse, the duty i/o flag will read 1. if the ctl signal currently being written is a 1 pulse, the duty i/o flag will read 0. ? vass record mode and vass rewrite mode: the duty i/o flag is used for write control, one ctl pulse at a time. the write timing is set in the rec-ctl duty data registers (rcdr1 to rcdr5). for vass recording, registers rcdr1 to rcdr5 are set with reference to ref30x. for vass rewrite, rcdr2 to rcdr5 are set with reference to the low-to-high transition of the previously recorded ctl signal, and the write is carried out through the trapezoid waveform generator. set the duty timing for a 1 pulse (short) in rcdr2, for a 1 pulse (long) in rcdr3, for a 0 pulse (short) in rcdr4, and for 0 pulse (long) in rcdr5. if 0 is written in the duty i/o flag, a ctl pulse will be written with a duty cycle set in rcdr2 and rcdr3, referenced to the immediately following ref30x. if 1 is written in the duty i/o flag, a ctl pulse will be written with a duty cycle set in rcdr4 and rcdr5, referenced to the immediately following ref30x. ? asm record mode: the duty i/o flag is used for write control, one ctl pulse at a time. the write timing is set in the rec-ctl duty data registers (rcdr1 and rcdr3). if 0 is written in the duty i/o flag, a ctl pulse will be written with a duty cycle of 67% to 70% as set in rcdr3, referenced to the immediately following ref30x. section 26 servo circuits rev.2.00 jan. 15, 2007 page 699 of 1174 rej09b0329-0200 bit pattern register (btpr) 0 1 1 1 r/w * 2 1 r/w * 3 1 4 5 1 6 7 r/w * r/w * r/w * lsp5 1 r/w * lsp4 1 r/w * lsp6 1 r/w * lsp7 lsp3 lsp2 lsp1 lsp0 note: * write is prohibited when bit pattern detection is selected. bit : initial value : r/w : btpr is an 8-bit shift register which detects and records the bit pattern of the ctl pulses. if a ctl pulse is detected in pb or asm mode, the register is shifted leftward at the rising edge of pb-ctl, and reflects the determined result of long/short on the bit 0 (long pulse = 1, short pulse = 0). if bpon bit is set to 1 in pb mode, the register starts detection of bit pattern immediately after the ctl pulse. to exit the bit pattern detection, set the bpon bit at 0. if 1 was written in the bps bit when the bit pattern is being detected, the bpf bit is set at 1 when an 8-bit bit pattern was detected. if continuous detection of 8-bits is required, write 0 in the bpf bit, and then write 1 in bps bit. at the time of viss detection, the bit pattern detection is disabled. set the bpon bit to 0 at the time of viss detection. in rec mode, the register record the long/shorts in the bit pattern set in btpr. the pulse in record mode is determined always by bit 7 (lsp7) of btpr. btpr records one pulse, shifts leftward, and stores the data of bit 7 to bit 0. btpr is initialized to h'ff by a reset, in stand-by, module stop, or ctl stop mode. section 26 servo circuits rev.2.00 jan. 15, 2007 page 700 of 1174 rej09b0329-0200 26.13.6 operation ctl circuit operation: as shown in figure 26.49, the ctl discrimination/record circuit is composed of a 16-bit up/down counter and 12-bit registers ( 5). in playback (pb) mode, the 16-bit up/down counter counts on a s/4 clock when the pb-ctl pulse is high, and on a s/5 clock when low. in record or slow mode, this counter increments the count on a s/4 clock. in asm mode, this counter increments the count on a s/8 clock when the pulse is high, and on a s/4 clock when low. this counter always counts up in record and slow modes. in playback or slow mode, it is cleared on the rise of pb-ctl signal. in record mode, it is cleared on the rise of ref30x signal. s/4 ( s/8) s/5 ( s/4) rec-ctl (l0) rcdr5 rec-ctl (s0) rcdr4 rec-ctl (l1and asm) rcdr3 rec-ctl (s1) rcdr2 rec-ctl match detection match detection match detection match detection match detection rcdr1 12-bit register legend: udf: underflows when pb-ctl duty is 43% or less down udf upper 12 bits up up/down counter (16 bits) duty detection counter clear signal ref30x (rec) pb-ctl (pb, asm) up/down control signal rec: up pb, asm: up when pb-ctl is high down when pb-ctl is low figure 26.49 ctl discri mination/record circuit ctl mode register (ctlm) switchover timing: ctlm is enabled immediately after data is written to the register. care must be taken with changes in the operating state. capstan phase control is performed by the vd sync ref30x (x-value + tracking value) and pb- ctl in asm mode, and by the ref30p or cref and cfg division signal (dvcfg2) in rec mode. if capref30 signal to be used for capstan phase control is always generated by xdr, the section 26 servo circuits rev.2.00 jan. 15, 2007 page 701 of 1174 rej09b0329-0200 value of xdr must be overwritten when switching between pb and rec modes. figures 26.50 and 26.51 show examples of switch timing of ctlm and xdr. vd dvcfg2 ref30x 16bit up/down counter hsw ctl tx latch preset the x-value is updated by ref30p. modification of xdr must be performed before ref30p in the cycle in which the x-value is changed. x-value x-value after change rcdr3 rcdr1 rcdr2 ref30p ta pb-ctl tb 1 pulse udf 0 pulse 0 pulse cdivr2 register write 1 pulse x-value (xdr) is rewritten in this cycle rcdr1 capstan phase control asm mode, pb mode : ref30x-pb-ctl rec mode : ref30p-dvcfg2 /4 /5 /4 rec-ctl notes: 1. ta is the interval calculated from rcdr3. 2. tb is the interval in which switchover is performed from asm mode to rec mode. 3. tx is the cycle in which the ref30x period is shortened due to the change of xdr. figure 26.50 example of ctlm switchover timing (when phase control is performed by ref30p and dvcfg2 in rec mode) section 26 servo circuits rev.2.00 jan. 15, 2007 page 702 of 1174 rej09b0329-0200 vd cref ref30x 16bit up/down counter hsw ctl tx latch preset the x-value is updated by ref30p. modification of xdr must be performed before ref30p in the cycle in which the x-value is changed. x value x-value after change rcdr3 rcdr1 rcdr2 ref30p ta pb-ctl tb 1 pulse 0 pulse 0 pulse asm-rec switchover notes: 1. ta is the interval calculated from rcdr3. 2. tb is the interval in which switchover is performed from asm mode to rec mode. 3. tx is the cycle in which the ref30x period is shortened due to the change of xdr. 4. with cref and dvcfg2 phase alignment, the frequency need not be 25 hz or 30 hz. 1 pulse x-value (xdr) is rewritten in this cycle dvcfg2 rcdr1 capstan phase control asm mode, pb mode: ref30x-pb-ctl capstan phase control rec mode : cref30p-dvcfg2 /4 /5 /4 rec-ctl cdivr2 register write udf figure 26.51 example of ctlm switchover timing (when phase control is performed by cref and dvcfg2 in rec mode) section 26 servo circuits rev.2.00 jan. 15, 2007 page 703 of 1174 rej09b0329-0200 26.13.7 ctl input section the ctl input section consists of an input amplifier of which gain can be controlled by the register setting and a schmitt amplifier. figure 26.52 shows a block diagram of the ctl input section. trivial ctl pulse signal is received from the ctl head, amplified by the input amplifier, reshaped into a square wave by the schmitt amplifier, and sent to the servo circuits, and the timer l as the pb-ctl signal. control the ctl input amplifier gain by bits 3 to 0 in ctl gain control register (ctlgr) of the servo port. ? + + ? ctlfb ctlsmt(i) ctlfb ctlref ctlbias ctlgr0 ctlgr3 to 1 ampshort (rec-ctl) pb-ctl(+) note : be sure to set a capacitor between ctlamp (o) and ctlsmt (i). note pb-ctl(-) ampon (pb-ctl) ? + ctlamp(o) ctl(+) ctl(-) figure 26.52 block diagram of ctl input amplifier section 26 servo circuits rev.2.00 jan. 15, 2007 page 704 of 1174 rej09b0329-0200 ctl detector: if the ctl detector fails to detect a c tl pulse, it sets the ctl control register (ctcr) bit 1 to 1 indicating that the pulse has not been detected. if a ctl pulse is detected after that, the bit is automatically cleared to 0. duration used for determining detection or non-detection of the pulse depends on magnitude of phase shift of the last detected pulse from the reference phase (phase difference between ref30 and ctl si gnal). typically, detection or non-detection is determined within 3 to 4 cycles of the reference period. if settings of the ctl gain control register are maintained in a table format, you can refer to it when the ctl detector failed to detect ctl pulses. from the table, you can control amplifier gain of the ctl according to state of unctl bit, ther eby selecting an optimum ctl amplifier gain depending on state of the pulse recorded. figure 26.53 illustrates concept of gain cont rol for detecting the ctl input pulse. * v+th (fixed) * v-th (fixed) note: * ctl input sensitivity is variable depending on ctl gain control register (ctlgr) setting. figure 26.53 ctl input pulse gain control section 26 servo circuits rev.2.00 jan. 15, 2007 page 705 of 1174 rej09b0329-0200 pb-ctl waveform shaper in slow mode operation: if bit 0 in ctl control register (ctcr) is set to slow mode, slow reset function is activated. in slow mode, if falling edge is not detected within the specified time from rising edge detection, pb-ctl is forcibly shut down (slow reset). the time t fs (s) until the signal falls is the following interval after the rising edge of the internal ctl signal is detected: t fs = 16384 4/ s ( s = f osc /2) when f osc = 10 mhz, t fs = 13.1 ms. figure 26.54 shows the pb-ctl waveform in slow mode. ctl waveform internal ctl signal 1 frame 1 frame 1 frame slow tracking delay slow tracking delay slow tracking delay accelera- tion accelera- tion accelera- tion decelera- tion decelera- tion slow reset stop stop ctlp ctlp ctlp figure 26.54 pb-ctl waveform in slow mode operation section 26 servo circuits rev.2.00 jan. 15, 2007 page 706 of 1174 rej09b0329-0200 26.13.8 duty discriminator the duty discriminator circuit measures the period of the control signal recorded on the tape (pb- ctl signal) and discriminates its duty cycle. in viss or vass detection, the duty i/o flag is set or cleared according to the result of duty discrimination. the duty i/o flag is set to 1 when the duty cycle of the pb-ctl signal is above 44%, and is cleared to 0 when the duty cycle is below 43%. in asm detection, an asm mark is recognized (and the duty i/o fl ag is cleared to 0) when the duty cycle is above 66%. when the duty cycle is below 65%, no asm mark is recognized and the duty i/o flag is set to 1. the detection direction can be switched between forward and reverse by bit 5 (fw/rv) in the ctl mode register. long or short pulse can be detected by comparing rec-ctl duty data register (rcdr2 to rcdr5) and up/down counter. long or short pul se is discriminated at pb-ctl signal falling. discrimination result is stored in bit 0 of bit pattern register (btpr). at the same time, btpr is shifted to the left. lsp0 indicates 0 when short pulse is detected, and 1 when long pulse is detected. set the threshold value of long/short pulse in rcdr2 to rcdr5. see the description on the detection of the long/short pulse. figure 26.55 shows the duty cycle of the pb-ctl signal. section 26 servo circuits rev.2.00 jan. 15, 2007 page 707 of 1174 rej09b0329-0200 input signal short 1 pulse 25 0.5% pb-ctl input signal long 1 pulse 30 0.5% pb-ctl input signal short 0 pulse 57.5 0.5% 62.5 0.5% pb-ctl input signal long 0 pulse pb-ctl input signal asm mark 67 to 70% pb-ctl figure 26.55 pb-ctl signal duty cycle figure 26.56 shows the duty discrimination circuit. a 44% duty cycle is discriminated by counting with the 16-bit up/down counter, using a s/4 clock for the up-count and a s/5 clock for the down-count. an up-count is performed when the pb-ctl signal is high, and a down-count when low. long or short pulse is discriminated by comparing with rcdr2 to rcdr5. section 26 servo circuits rev.2.00 jan. 15, 2007 page 708 of 1174 rej09b0329-0200 counter pb-ctl 1 pulse pb-ctl pb-ctl s/4 s/5 counter pb-ctl 0 pulse s/4 s/5 counter fwd pb-ctl short pulse (0 pulse) s/4 s/5 rcdr3 rcdr2 0 pulse l/s threshold value 1 pulse l/s threshold value counter rev pb-ctl long pulse (1 pulse) s/5 s/4 rcdr4 rcdr5 0 pulse l/s threshold value 1 pulse l/s threshold value up/down comparison of upper 12-bit up/down counter (16 bits) * rcdr2or4 (12-bit) * fwd : discriminated by rcdr2 and rcdr3 rev : discriminated by rcdr4 and rcdr5 * rcdr3or5 (12-bit) 0/1 discrimination udf clear r sq s/4 s/5 l/s discrimination figure 26.56 du ty discriminator section 26 servo circuits rev.2.00 jan. 15, 2007 page 709 of 1174 rej09b0329-0200 viss (index) detect mode: viss detection is carried out by the viss control circuit, which counts 1 pulses in the pb-ctl signal. if the pulse count detects any value set in the viss interrupt setting bits (bits 5, 6, or 7 in the duty i/o register), an interrupt request is generated and the duty i/o flag is cleared to 0. at viss record or rewrite, index code is automatically written. index code is composed of 0 continuous 62-bit data with 0 pulse data at both edge. examples of bit strings and the duty i/o flag at viss detection/record is illustrated in figure 26.57. 0 tape direction duty i/o flag (a) viss detection (index: thirty-two 1 pulse setting) 1111 61 3 bits thirty-two 1 pulses detected irrctl 63 3 bits start 11110 0 tape direction duty i/o flag (b) viss record 1111 62 bits irrctl 64 bits start 11110 1 2 3 62 63 64 figure 26.57 examples of viss bit strings and duty i/o flag section 26 servo circuits rev.2.00 jan. 15, 2007 page 710 of 1174 rej09b0329-0200 duty detection mode (vass): vass detection is carried out by the duty discriminator. software can detect index sequences by reading the duty i/o flag at each ctl pulse. at each ctl pulse, the duty discriminator sends th e result of duty discrimi nation to the duty i/o flag, and simultaneously generates an interrupt request. the duty i/o flag is cleared to 0 if the ctl pulse is a 1 (duty cycle below 43%), and is set to 1 if the ctl pulse is a 0 (duty cycle above 44%). the duty i/o flag is modified at each ctl pulse. it should be read by the interrupt-handling routine within the period of the pb-ctl signal. vass detection format is illustrated in figure 26.58. 1 tape direction written three times 1111111111 m s b l s b l s b m s b m s b l s b l s b m s b thousands header (11 bits) hundreds data (16 bits: 4 digits of 4-bit bcd) tens ones figure 26.58 vass (index) format assemble (asm) mark detect mode: asm mark detection is carried out by the duty discriminator. if the duty discriminator detects that the duty cycle of the pb-ctl signal is 66% or higher, it generates an interrupt request, and simultaneously clears the duty i/o flag to 0. the duty i/o flag is updated at every ctl pulse. it should be read by the interrupt-handling routine within the period of the pb-ctl signal. section 26 servo circuits rev.2.00 jan. 15, 2007 page 711 of 1174 rej09b0329-0200 detection of the lo ng/short pulse: the long/short pulse is detected in pb mode by the l/s determination based on the comparison of the rec-ctl duty register (rcdr2 to rcdr5) with the up/down counter and the results of the duty i/o flag. the results of the determination is stored in bit 0 (lsp0) of the bit pattern register (btpr) at the rising edge of pb-ctl, shifting at the same time btpr leftward. rcdr2-5 set the l/s thresholds for each of fwd/ rev. set to rcdr2 a threshold of 1 pulse l/s for fwd, to rcdr3 a threshold of 0 pulse l/s for fwd, to rcdr4 a threshold of 0 pulse l/s for rev, and to rcdr5 a threshold of 1 pulse l/s for rev. figure 26.59 shows the detection of long/short pulse. also, the bit pattern of 8-bit can be detected by btpr. check that an 8-bit detection has been done by bit 1 (bpf bit) of the duty i/o register, and then read btpr. bit patter register (8 bits) up/down counter (16 bits) rcdr2 (12 bits) high-order 12-bit data rcdr3 (12 bits) internal bus lsb fw/rv di/o shift left-ward btpr r r s q rcdr4 (12 bits) rcdr5 (12 bits) r sq s/4 note: l/s is determined at the rising edge of pb-ctl. after the determination, bit pattern register is shifted leftward, and the results of the determination is stored in the lsb. figure 26.59 detection of long/short pulse section 26 servo circuits rev.2.00 jan. 15, 2007 page 712 of 1174 rej09b0329-0200 26.13.9 ctl output section an on-chip control head amplifier is provided for writing the rec-ctl signal generated by the write control circuit onto the tape. the write control circuit controls the duty cycle of the rec-ctl signal in the writing of viss and vass sequences and asm marks and the rewriting of viss and vass sequences. the duty cycle of the rec-ctl signal is set in rec-ctl duty data registers 1 to 5 (rcdr1 to rcdr5). times calculated in terms of s (= f osc /2) should be converted to appropriate data to be set in these registers. in viss or vass mode, set rcdr2 for a duty cycle of 25% 0.5%, rcdr3 for a duty cycle of 30% 0.5%, rcdr4 for a duty cycle of 57.5 0.5%, and rcdr5 for a duty cycle of 62.5 0.5%. when 1 is written in the duty i/o flag, the rec-ctl signal will be written on the tape with a 25% 0.5% duty cycle when 0 is written in bit 7 (lsp7) in the bit pattern register (btpr) and with a 30 0.5% duty cycle when 1 is written. table 26.21 shows the relationship between the rec-ctl duty register and ctl outputs. in asm mark write mode, set rcdr3 for a duty cycle of 67% to 70%. an asm mark will be written when 0 is written in the duty i/o flag. an interrupt request is generated at the rise of the reference signal after one ctl pulse has been written. the reference signal is derived from the output signal (ref30x) of the x-value adjustment circuit, and has a period of one frame. figure 26.60 shows the timings that generate the rec-ctl signal. table 26.21 rec-ctl duty register and ctl outputs mode d/io lsp7 pulse rcdr duty 0 s1 rcdr2 25 0.5% 0 1 l1 rcdr3 30 0.5% 0 s0 rcdr4 57.5 0.5% viss, vass modes 1 1 l0 rcdr5 62.5 0.5% asm mode 0 * ? rcdr3 67 to 70% legend: * don?t care. section 26 servo circuits rev.2.00 jan. 15, 2007 page 713 of 1174 rej09b0329-0200 w internal bus rcdr2or4 (12 bits) w rcdr1 (12 bits) up/down counter (12 bits) counter ref30x rec-ctl counter reset match detection match detection end of writing of one ctl pulse (except viss) irrctl rcdr2 (viss/vass s1 pulse) rcdr3 (viss/vass l1 pulse, or asm) rcdr4 (viss/vass s0 pulse) rcdr5 (viss/vass l0 pulse) rcdr1 clear upper 12 bits rec-ctl 0 pulse fall timing rec-ctl rise timing rec-ctl1 pulse, asm fall timing reset ref30x w rcdr3or5 (12 bits) s/4 compare compare compare figure 26.60 rec-ctl signal generation timing section 26 servo circuits rev.2.00 jan. 15, 2007 page 714 of 1174 rej09b0329-0200 the 16-bit counter in the rec-ctl circuit continues counting on a clock derived by dividing the system clock s (= f osc /2) by 4. the counter is cleared on the rise of ref30x in record mode, and on the rise of pb-ctl in rewrite mode. rec-ctl match detection is carried out by comparing the counter value with each rcdr value. rcdr1 to rcdr5 can be written to by software at all times. if rcdr is changed before the respective match detection is performed, match de tection is performed using the new value. the value changed after match detection becomes valid on the rise of ref30x following the change. figure 26.61 shows examples of rcdr change timing. ref30x rec-ctl rcdr1 rcdr2 rcdr1 1 pulse (short) 0 pulse (short) rewritten 0 pulse (short) rcdr1 rcdr1 counter rcdr4 rcdr2 rcdr1 rcdr4 rcdr4 rcdr4 interval in which rcdr4 can be written to figure 26.61 example of rcdr change timing (example showing rcdr4) section 26 servo circuits rev.2.00 jan. 15, 2007 page 715 of 1174 rej09b0329-0200 26.13.10 trapezoid waveform circuit in rewriting, the trapezoid wavefo rm circuit leaves the rising e dge of the already-recorded pb- ctl signal intact, but changes the duty cycle. in rewriting, the ctl pulse is written with refere nce to the rise of pb-ctl. the ctl duty cycle for a rewrite is set in the rec-ctl duty data registers (rcdr2 to rcdr5). time values t2 to t5 are referenced to the rise of pb-ctl. figure 26.62 shows the rewrite waveform. w internal bus rcdr3or5 (12 bits) w not used when rewriting rcdr2or4 (12 bits) up/down counter (16 bits) clear upper 12 bits rec-ctl 0 pulse fall timing rec-ctl 1 pulse fall timing reset pb-ctl w t 2 to t 5 eliminated pulse high-impedance interval end of writing of one ctl pulse (except viss) irrctl rcdr1 (12 bits) s/4 compare compare rcdr2 (biss/vass s1 pulse) rcdr3 (viss/vass l1 pulse) rcdr4 (viss/vass s0 pulse) rcdr5 (viss/vass l0 pulse) pb-ctl rec-ctl when rewriting new pulse figure 26.62 relationship between re c-ctl and rcdr2 to rcdr5 when rewriting section 26 servo circuits rev.2.00 jan. 15, 2007 page 716 of 1174 rej09b0329-0200 26.13.11 note on ctl interrupt after a reset, the ctl circuit is in the viss discrimination input mode. depending on the ctl pin states, a false pb-ctl input pulse may be recognized and an interrupt request generated. if the interrupt request will be enabled, first clear the ctl interrupt request flag. 26.14 frequency dividers 26.14.1 overview on-chip frequency dividers are provided for the pulse signal picked up from the control track during playback (the pb-ctl signal), and the pulse signal received from the capstan motor (cfg signal). the ctl frequency divider generates a ctl divided control signal (dvctl) from the pb-ctl signal, for use in capstan phase control during high-speed search, for example. the cfg frequency divider generates two divided cfg signa ls (dvcfg for speed control and dvcfg2 for phase control) from the cfg signal. the dfg noise canceller is a circuit which considers signal less than 2 as noise and mask it. 26.14.2 ctl frequency divider block diagram: figure 26.63 shows a block diagram of the ctl frequency divider. exctl pb-ctl , dvctl udf r/w w (8 bits) r/w internal bus cex ctl division register down counter (8 bits) ceg edge detector ctvc ctlr ctvc figure 26.63 ctl frequency divider section 26 servo circuits rev.2.00 jan. 15, 2007 page 717 of 1174 rej09b0329-0200 register description register configuration table 26.22 shows the register configuration of the ctl frequency dividers. table 26.22 register configuration name abbrev. r/w size initial value address dvctl control register ctvc r/w byte undefined h'd098 ctl frequency division register ctlr w byte h'00 h'd099 dvctl control register (ctvc) 0 * 1 * r 2 * r 3 4 5 ? ? ? ? ? ? 6 7 r cfg hsw 0 w 0 w cex ceg ctl 1 11 bit : initial value : r/w : note: * undefined ctvc consists of the external input signal selection bits and the flags which show the cfg, hsw, and ctl levels. note: it has an undetermined value by a reset or in stand-by mode. bit 7 ? dvctl signal generation selection bit (cex): selects which of the pb-ctl signal or the external input signal is used to generate the dvctl signal. bit 7 cex description 0 generates dvctl signal with pb-ctl signal (initial value) 1 generates dvctl signal with external input signal section 26 servo circuits rev.2.00 jan. 15, 2007 page 718 of 1174 rej09b0329-0200 bit 6 ? external sync signal edge selection bit (ceg): selects the edge of the external signal at which the frequency division is made when the external signal was selected to generate dvctl signal. bit 6 ceg description 0 rising edge (initial value) 1 falling edge bits 5 to 3 ? reserved: cannot be modified and are always read as 1. bit 2 ? cfg flag (cfg): shows the cfg level. bit 2 cfg description 0 cfg is at low level (initial value) 1 cfg is at high level bit 1 ? hsw flag (hsw): shows the level of the hsw signal selected by the vff/nff bit of the hsw mode register 2 (hsm2). bit 1 hsw description 0 hsw is at low level (initial value) 1 hsw is at high level bit 0 ? ctl flag (ctl): shows the ctl level. bit 0 ctl description 0 rec or pb-ctl is at low level (initial value) 1 rec or pb-ctl is at high level section 26 servo circuits rev.2.00 jan. 15, 2007 page 719 of 1174 rej09b0329-0200 ctl frequency division register (ctlr) 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 ctl4 ctl3 ctl2 ctl1 ctl0 0 w ctl7 w w w ctl6 ctl5 bit : initial value : r/w : ctlr is an 8-bit write-only register to set the frequency dividing value (n-1 if divided by n) for pb-ctl. if a read is attempted, an undetermined value is read out. pb-ctl is divided by n at its rising edge. if the register value is 0, no division operation is performed, and the dvctl signal with the same cycle with pb-ctl is output. it is initialized by a reset or in stand-by mode. operation: during playback, control puls es recorded on the tape are picked up by the control head and input to the ctl pin. the control pu lse signal is amplified by a schmitt amplifier, reshaped, then input to the ctl frequency divider as the pb-ctl signal. this circuit is employed when the control pulse (pb-ctl signal) is used for phase control of the capstan motor. the divided signal is sent as the dvctl signal to the capstan phase system in the servo circuits and timer r. the ctl frequency divider is an 8-bit reload timer consisting of a reload register and a down- counter. frequency division is obtained by setting freque ncy-division data in bits 7 to 0 in the ctl frequency division register (ctlr), which is the reload register. when a frequency division value is written in this reload regist er, it is also written into the down-counter. the down-counter is decremented on rising edges of the pb-ctl signal. figure 26.64 shows examples of the pb-ctl and dvctl waveforms. section 26 servo circuits rev.2.00 jan. 15, 2007 page 720 of 1174 rej09b0329-0200 ctl input signal legend: ctlr: ctl frequency division register pb-ctl or external sync signal ctlr=00 ctlr=01 ctlr=02 figure 26.64 ctl frequency division waveforms section 26 servo circuits rev.2.00 jan. 15, 2007 page 721 of 1174 rej09b0329-0200 26.14.3 cfg frequency divider block diagram: figure 26.65 shows a block diagram of the 7-bit cfg frequency divider and its mask timer. w r/w w w w wwr w internal bus cmn crf udf udf udf cfg dvcfg dvcfg2 , mcgin internal bus cps1, cps0 ctmr(6 bits) cdivr2(7 bits) dvtrg pb(asm) rec s = fosc/2 s/1024 s/512 s/256 s/128 down counter (6 bits) cdivr(7 bits) cmk s r edge select ?cdvc ?cdvc ?cdvc ?cdvc ?cdvc down counter (7 bits) down counter (7 bits) figure 26.65 cfg frequency divider section 26 servo circuits rev.2.00 jan. 15, 2007 page 722 of 1174 rej09b0329-0200 register description: register configuration table 26.23 shows the register configuration of the cfg frequency division circuit. table 26.23 register configuration name abbrev. r/w size initial value address dvcfg control register cdvc r/w byte h'60 h'd09a cfg frequency division register 1 cdivr1 w byte h'80 h'd09b cfg frequency division register 2 cdivr2 w byte h'80 h'd09c dvcfg mask period register ctmr w byte h'ff h'd09d dvcfg control register (cdvc) 0 0 1 0 w 2 0 w 3 4 0 w 5 1 6 ? ? 1 7 w r cmk cmn w dvtrg 0 r/w * mcgin crf cps1 cps0 0 note: * only 0 can be written. bit : initial value : r/w : cdvc is an 8-bit register to control the capstan frequency division circuit. it is initialized to h'60 by a reset, or in stand-by or module stop mode. bit 7 ? mask cfg flag (mcgin): mcgin is a flag to indicate occurrence of a frequency division signal during the mask timer's mask period. to clear it by software, write 0 after reading 1. also, setting has the highest priority in this flag. if a condition setting the flag and 0 write occur simultaneously, the latter is invalid. bit 7 mcgin description 0 cfg is in normal operation (initial value) 1 shows that dvcfg was detected during masking (runaway detected) bit 6 ? reserved: cannot be modified and is always read as 1. section 26 servo circuits rev.2.00 jan. 15, 2007 page 723 of 1174 rej09b0329-0200 bit 5 ? cfg mask status bit (cmk): indicates the status of the mask. it is initialized to 1 by a reset, or in stand-by or module stop mode. bit 5 cmk description 0 indicates that the capstan mask timer has released masking 1 indicates that the capstan mask timer is currently masking (initial value) bit 4 ? cfg mask selection bit (cmn): selects the turning on/off of the mask function. bit 4 cmn description 0 capstan mask timer function on. (initial value) 1 capstan mask timer function off. bit 3 ? pb (asm) rec transition timing sync on/off selection bit (dvtrg): selects the on/off of the timing sync of the transition from pb (asm) to rec when the dvcfg2 signal is generated. bit 3 dvtrg description 0 pb (asm) rec transition timing sync on. (initial value) 1 pb (asm) rec transition timing sync off. bit 2 ? cfg frequency division edge selection bit (crf): selects the edge of the cfg signal to be divided. bit 2 crf description 0 performs frequency division at the rising edge of cfg. (initial value) 1 performs frequency division at both edges of cfg. section 26 servo circuits rev.2.00 jan. 15, 2007 page 724 of 1174 rej09b0329-0200 bits 1 and 0 ? cfg mask timer clock selection bits (cps1, cps0): select the clock source for the cfg mask timer. ( s = fosc/2) bit 1 bit 0 cps1 cps0 description 0 s/1024 (initial value) 0 1 s/512 1 0 s/256 1 s/128 cfg frequency division register 1 (cdivr1) 0 0 1 0 w 2 0 w 3 4 0 w 5 0 6 7 ? ? w w cdv15 cdv14 0 w cdv16 0 w cdv13 cdv12 cdv11 cdv10 1 bit : initial value : r/w : cdivr1 is an 8-bit write-only register to set the division value. if a read is attempted, an undetermined value is read out. bit 7 is reserved. the frequency division value is written in the reload register and the down counter at the same time. cfg's frequency is divided by n at its rising edge or both edges if the register value is 0, no division operation is performed, and the dvcfg signal with the same input cycle with cfg signal is output. the dvcfg signal is sent to the cap stan speed error detector. it is initialized to h'80 by a reset or in stand-by mode together with the capstan frequency division register and the down counter. cfg frequency division register 2 (cdivr2) 0 0 1 0 w 2 0 w 3 4 0 w 5 0 6 7 ? ? w w cdv25 cdv24 0 w cdv26 0 w cdv23 cdv22 cdv21 cdv20 1 bit : initial value : r/w : cdivr2 is an 8-bit write-only register to set the division value. if a read is attempted, an undetermined value is read out. bit 7 is reserved. the frequency division value is written in the reload register and the down counter at the same time. section 26 servo circuits rev.2.00 jan. 15, 2007 page 725 of 1174 rej09b0329-0200 cfg's frequency is divided by n at its rising edge or both edges if the register value was 0, no division operation is performed, and the dvcfg signal with the same input cycle with cfg is output. the dvcfg2 signal is sent to the capstan speed error detector and the timer l. the dvcfg2 circuit has no mask timer function. the frequency division counter starts its division operation at the point data was written in cdivr2. if synchronization is required for phase matching, for example, do it by writing in cdivr2. if the dvtrg bit of the cdvc register is 0, the register synchronizes with the switching timing from pb (asm) to rec. it is initialized to h'80 by a reset or in stand-by mode together with the capstan frequency division register and the down counter. dvcfg mask period register (ctmr) 0 1 1 1 w 2 1 w 3 4 1 w 5 1 6 7 ? ? ? ? w w cpm5 cpm4 1 w cpm3 cpm2 cpm1 cpm0 11 bit : initial value : r/w : ctmr is an 8-bit write-only register. if a read is attempted, an undetermined value is read out. ctmr is a reload register for the mask timer (down counter). set in it the mask period of cfg. the mask period is determined by the clock specified by the bits 1 and 0 of cdvc and the set value (n - 1). if data is written in ctmr, it is written also in the mask timer at the same time. it is initialized to h'ff by a reset, or in stand-by or module stop mode. mask period = n clock cycle section 26 servo circuits rev.2.00 jan. 15, 2007 page 726 of 1174 rej09b0329-0200 operation: ? frequency divider the cfg pulses output from the capstan motor are sent to internal circuitry as the cfg signal via the zero-cross type comparator. the cfg signa l, shaped into a rectangular waveform by a reshaping circuit, is divided by the cfg frequency dividers, and used in servo control. the rising edge or both edges of the cfg signal can be selected for the frequency divider. the cfg frequency divider consists of a 7-bit frequency divider with a mask timer for capstan speed control (dvcfg signal generator) and a 7-bit frequency divider for capstan phase control (dvcfg2 signal generator). the dvcfg signal generator consists of a 7- bit reload register (cfg frequency division register1: cdivr1), a 7-bit down-counter, and a 6-bit mask timer (with settable mask interval). frequency division is performed by setting the frequency-division value in 7-bit cdivr1. when the frequency-division value is written in cdivr1, it is also written in the down-counter. after frequency-division of a cfg signal for which the edge has been selected, the signal is sent via the mask timer to the cap stan speed error detector as the dvcfg signal. the dvcfg2 signal generator consists of a 7- bit reload register (cfg frequency division register 2: cdivr2) and a 7-bit down-counter. the 7-bit frequency divider does not have a mask timer. frequency division is performed by setting the frequency-division value in cdivr2. when the frequency-division value is written in cdvir2, it is also written in the down-counter. after frequency division of a cfg signal for which the edge has been selected, the signal is sent to the capst an speed error detector and timer l as the dvcfg2 signal. frequency division starts when the frequency-division value is written. when dvtrg bit in cdvc register is set to 0, reloading is executed with the switch over timing from pb (asm) mode to rec mode. to switch from ref30 to cref, change the settings of bit 4 (cr/rf bit) in the capstan phase error detection control register (cpgcr). if synchronization is necessary for phase control, this can be provided by writing the frequency- division value in cdivr2. the down-counters are decremented on rising ed ges of the cfg signal when the crf bit is 0 in the dvcfg control register (cdvc), and on both edges when the crf bit is 1. figure 26.66 shows examples of cfg frequency division waveforms. section 26 servo circuits rev.2.00 jan. 15, 2007 page 727 of 1174 rej09b0329-0200 cfg crf bit = 1 cdivr = 00 crf bit = 0 cdivr = 00 crf bit = 0 cdivr = 01 crf bit = 0 cdivr = 02 figure 26.66 cfg frequency division waveforms section 26 servo circuits rev.2.00 jan. 15, 2007 page 728 of 1174 rej09b0329-0200 ? mask timer the capstan mask timer is a 6-b it reload timer that uses a prescaled clock as a clock source. the mask timer is used for masking dvcfg signal intended for controlling the capstan speed. the capstan mask timer prevents edge detection to be carried out for an unnecessarily long duration by masking the edge detection for a certain period. the above trouble can result from abnormal revolution (runout) of the capstan moto r because its revolution has to cover a wide range speeds from the low/still up to the high speed search. the capstan mask timer is started by a pulse edge in the divided cfg signal (dvcfg). while the timer is running, a mask signal disables the output of further dvcfg pulses. the mask signal is shown in figure 26.67. the mask timer status can be monitored by reading the cmk flag in the dvcfg control register (cdvc). mask dvcfg mask timer underflow figure 26.67 mask signal section 26 servo circuits rev.2.00 jan. 15, 2007 page 729 of 1174 rej09b0329-0200 figures 26.68 and 26.69 show examples of cfg mask timer operations. cfg (racing) edge detect cleared by wiring 0 after reading 1 capstan motor mask timer mask interval mask interval dvcfg mcgin flag figure 26.68 cfg mask timer opera tion (when capstan motor is racing) cfg edge detect capstan motor mask timer mask interval mask interval figure 26.69 cfg mask ti mer operation (when capstan motor is operati ng normally) section 26 servo circuits rev.2.00 jan. 15, 2007 page 730 of 1174 rej09b0329-0200 26.14.4 dfg noise removal circuit block diagram: figure 26.70 shows the block diagram of the dfg noise removal circuit. rising edge detection delay circuit dfg sq r ncdfg delay = 2 falling edge detection figure 26.70 dfg noise removal circuit register description: table 26.24 shows the register configuration of the dfg mask circuit. table 26.24 register configuration name abbrev. r/w size initial value address fg control register fgcr w byte h'fe h'd09e fg control register (fgcr) 0 0 1 1 2 1 3 1 4 1 5 1 6 1 7 ? ? ? ? ? ? ? ? ? ? ? ? ? ? w drf 1 bit : initial value : r/w : fgcr selects the edge of the dfg noise removal signal (ncdfg) to be sent to the drum speed error detector. if a read is attempted, an undetermined value is read out. it is initialized to h'fe by a reset, or in stand-by or module stop mode. the edge selection circuit is located in the dr um speed error detector, and outputs the register output to the drum speed error detector. bits 7 to 1 ? reserved: cannot be modified and are always read as 1. section 26 servo circuits rev.2.00 jan. 15, 2007 page 731 of 1174 rej09b0329-0200 bit 0 ? dfg edge selection bit (drf): selects the edge of the ncdf g signal used in the drum speed error detector. bit 0 drf description 0 selects the rising edge of ncdfg signal (initial value) 1 selects the falling edge of ncdfg signal operation the dfg noise removal circuit generates a signal (ncdfg signal) as a result of removing noise (signal fluctuation smaller than 2 ) from the dfg signal. the resulted ncdfg signal is behind the time when the dfg si gnal was detected by 2 . figure 26.71 shows the ncdfg signal. dfg ncdfg noise 2 2 2 = fosc figure 26.71 ncdfg signal section 26 servo circuits rev.2.00 jan. 15, 2007 page 732 of 1174 rej09b0329-0200 26.15 sync signal detector 26.15.1 overview this block performs detection of the horizontal sync signal (hsync) and vertical sync signal (vsync) from the composite sync signal (csync), noise counting, and field detection. it detects the horizontal and vertical sync signals by setting threshold in the register and based on the servo clock ( s = fosc/2). noise masking is possible during the detection of the horizontal sync signals, and if any hsync pulse is missing, it can be supplemented. also, if total volume of the noise detected in one frame of csync amounted over a specified volume, the detector generates a noise detection interrupt. note: this circuit detects a pulse with a specific width set by the threshold register. it does not classify or restore the sync signal to a formal one. section 26 servo circuits rev.2.00 jan. 15, 2007 page 733 of 1174 rej09b0329-0200 26.15.2 block diagram figure 26.72 shows the block diagram of the sync signal detector. w h threshold register w v threshold register (6 bits) (4 bits) ? htr ? vtr w w h complement start time register complementary h pulse width register (8 bits) (4 bits) ? hpwr ? hrtr w w (6 bits) (8 bits) ? ndr r/w r/w r/(w) r nois h counter (8 bits) noise detector complement control & nozzle mask control circuit up/down counter (6 bits) seph selection of polarity noise detection window noise detection interrupt vd interrupt csync sync signal detector h reload counter (8 bits) field detector noise counter (10 bits) toggle circuit clear fld syct vd(sepv) field noise irrsnc osch nis/vd ? syncr ? nwr internal bus s = fosc/2 s/2 noise detection window register noise detection register figure 26.72 block diagram of the sync signal detector section 26 servo circuits rev.2.00 jan. 15, 2007 page 734 of 1174 rej09b0329-0200 26.15.3 pin configuration table 26.25 shows the pin configuration of the sync signal detector. table 26.25 pin configuration name abbrev. i/o function composite sync signal input pin csync input composite sync signal input 26.15.4 register configuration table 26.26 shows the register configuration of the sync signal detector. table 26.26 register configuration name abbrev. r/w size initial value address vertical sync signal threshold register vtr w byte h'c0 h'd0b0 horizontal sync signal threshold register htr w byte h'f0 h'd0b1 h complement start time setting register hrtr w byte h'00 h'd0b2 complement h pulse width setting register hpwr w byte h'f0 h'd0b3 noise detection window setting register nwr w byte h'c0 h'd0b4 noise detector ndr w byte h'00 h'd0b5 sync signal control register syncr r/w byte h'f8 h'd0b6 26.15.5 register description vertical sync signal threshold register (vtr) 0 0 1 0 w 2 0 w 3 0 4 0 w 5 0 6 1 7 ? ? ? ? w w w vtr5 vtr4 vtr3 vtr2 vtr1 vtr0 1 bit : initial value : r/ w : vtr is an 8-bit write-only register that sets the threshold for the vertical sync signal when the signal is detected from the composite sync signal. the threshold is set by bits 5 to 0 (vtr5 to vtr0). bits 7 and 6 are reserved. if a read is attempted, an undetermined value is read out. it is initialized to h'c0 by a reset, or in stand-by or module stop mode. section 26 servo circuits rev.2.00 jan. 15, 2007 page 735 of 1174 rej09b0329-0200 horizontal sync signal threshold register (htr) 0 0 1 0 w 2 0 w 3 0 4 5 6 1 7 ? ? ? ? ? ? ? ? w w htr3 htr2 htr1 htr0 11 1 bit : initial value : r/w : htr is an 8-bit write-only register that sets the threshold for the horizontal sync signal when the signal is detected from the composite sync signal. the threshold is set by bits 3 to 0 (htr3 to htr0). bits 7 and 4 are reserved. if a read is attempted, an undetermined value is read out. it is initialized to h'f0 by a reset, or in stand-by or module stop mode. figure 26.73 shows the threshold values and separated sync signals. legend: th hpulse t h sepv hpulse : period of the horizontal sync signal (ntsc: 63.6, pal: 64 [ s]) : pulse width of the horizontal sync signal (ntsc, pal: 4.7 [ s]) vvth hvth : value set as the threshold of the vertical sync signal : value set as the threshold of the horizontal sync signal sepv seph : detected vertical sync signal : detected horizontal sync signal (before complement) t h seph csync h'00 counter value 1/2 hpulse vd interrupt hpulse vvth hvth figure 26.73 threshold values and separated sync signals section 26 servo circuits rev.2.00 jan. 15, 2007 page 736 of 1174 rej09b0329-0200 example the values set to detect the vertical and horizontal sync signals (sepv, seph) from csync are required to meet the following conditions. assumed that the set values in vthr register were vvth and hvth, (vvth - 1) 2/ s > hpulse (hvth - 2) 2/ s hpulse/2 < (hvth - 1) 2/ s where, hpulse is pulse width ( s) of the horizontal sync signal, and s is servo clock (fosc/2). thus, if s = 5 mhz, ntsc system is used, (vvth - 1) 0.4 s > 4.7 s vvth h'd (hvth - 2) 0.4 s 2.35 s < (hvth - 1) 0.4 s hvth h'7 note: this circuit detects the pulse with the width set in vthr. if a noise pulse with the width greater than the set value is input, the circuit regards it as a sync signal. h complement start time setting register (hrtr) 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 hrtr4 hrtr3 hrtr2 hrtr1 hrtr0 0 w hrtr7 w w w hrtr6 hrtr5 bit : initial value : r/w : hrtr is an 8-bit write-only register that sets the timing to generate a complementary pulse if a pulse of the horizontal sync signal is missing. if a read is attempted, an undetermin ed value is read out. it is in itialized to h'00 by a reset, or in stand-by or module stop mode. ((value of hrtr7 - 0) + 1) 2/ s = th where, th is the period of the horizontal sync signal ( s), and s is the servo clock (fosc/2). whether the horizontal sync signal exists or not is determined one clock before the complementary pulse is generated. accordingly, set to hrtr7 to hrtr0 a value obtained from the equation shown above plus one. also, hrtr7-hrtr0 sets the noise mask period. if the horizontal sync signal has the normal pulses, it is masked in the mask period. the start and the end of the mask period are computed frm the rising edge of osch and seph, respectively. see figure 26.75. section 26 servo circuits rev.2.00 jan. 15, 2007 page 737 of 1174 rej09b0329-0200 complementary h pulse width setting register (hpwr) 0 0 1 0 w 2 0 w 3 0 4 5 6 1 7 ? ? ? ? ? ? ? ? w w hpwr3 hpwr2 hpwr1 hpwr0 11 1 bit : initial value : r/w : hrwr is an 8-bit write-only register that sets the pulse width of the complementary pulse which is generated if a pulse of the horizontal sync signal is missing. bits 7 to 4 are reserved. if a read is attempted, an undetermin ed value is read out. it is in itialized to h'f0 by a reset or in stand-by mode. ((value of hpwr3 - 0) + 1) 2/ s = hpulse where, hpulse is the pulse width of the horizontal sync signal ( s), and s is the servo clock (fosc/2). noise detection window setting register (nwr) 0 0 1 0 w 2 0 w 3 0 4 0 w 5 0 6 1 7 ? ? ? ? w w w nwr5 nwr4 nwr3 nwr2 nwr1 nwr0 1 bit : initial value : r/w : nwr is an 8-bit write-only register that sets the period (window) when the drop-out of the horizontal sync signal pulse is detected and the noise is counted. set the timing of the noise detection window in bits 5 to 0. bits 7 and 6 are reserved. if a read is attempted, an undetermin ed value is read out. it is initia lized to h'c0 by a reset, or in stand-by or module stop mode. set the value of the noise detection window timing according to the following equation. ((value of nwr5-0) + 1) 2/ s = 1/4 th where, th is the pulse width of the horizontal sync signal ( s), and s is the servo clock (fosc/2). it is recommended that this timing value is set at about 1/4 of the cycle of the horizontal sync signal. section 26 servo circuits rev.2.00 jan. 15, 2007 page 738 of 1174 rej09b0329-0200 noise detection register (ndr) 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 ndr4 ndr3 ndr2 ndr1 ndr0 0 w ndr7 w w w ndr6 ndr5 bit : initial value : r/w : ndr is an 8-bit write-only register that sets the noise detection level when the noise of the horizontal sync signal is detected (when nwr is set). set the noise detection level in bits 7 to 0. no read is valid. if a read is attempted, an undete rmined value is read out. it is initialized to h'00 by a reset, or in stand-by or module stop mode. the noise detector takes counts of the drop-outs of the horizontal sync signal pulses and the noise within the pulses, and if they amount to a count greater than four times of the value set in ndr7- ndr0, the detector sets the nois flag in the sync signal control register (syncr). set the noise detection level at 1/4 of the noise counts in one frame. the noise counter is cleared when ever vsync is detected twice. see section 26.15.6, noise detection for the details of the noise detection window and the noise detection level. sync signal control register (syncr) 0 0 1 0 r 2 0 r/(w) * 3 1 4 5 6 1 7 ? ? ? ? ? ? ? ? r/w r/w nis/vd nois fld syct 11 1 note: * only 0 can be written bit : initial value : r/w : syncr is an 8-bit register that controls the noise detection, field detection, polarity of the sync signal input, etc. it is initialized to h'f8 by a reset, or in stand-by mode. bits 7 to 4 are reserved. no write is valid. bit 1 is read-only. bits 7 to 4 ? reserved: cannot be modified and are always read as 1. section 26 servo circuits rev.2.00 jan. 15, 2007 page 739 of 1174 rej09b0329-0200 bit 3 ? interrupt selection bit (nis/vd): selects whether an interrupt request is generated by noise level detection or vd signal detection. bit 3 nis/vd description 0 interrupt at the noise level 1 interrupt at vd (initial value) bit 2 ? noise detection flag (nois): nois is a status flag indica ting that the noise counts reached at more than four times of the value set in ndr. the flag is cleared only by writing 0 after reading 1. care is required because it is not cleared automatically. bit 2 nois description 0 noise count is smaller than four times of the value set in ndr (initial value) 1 noise count is the same or greater than four times of the value set in ndr bit 1 ? field detection flag (fld): indicates whether the field curre ntly being scanned is even or odd. see figure 26.74. bit 1 fld description 0 odd field (initial value) 1 even field bit 0 ? sync signal polarity selection bit (syct): selects the polarity of the sync signal (csync) to be input. bit 0 syct description polarity 0 (initial value) positive 1 negative section 26 servo circuits rev.2.00 jan. 15, 2007 page 740 of 1174 rej09b0329-0200 field detection flag (fld) sepv noise detection window composite sync signal even field (a) even field field detection flag (fld) sepv noise detection window composite sync signal odd field (b) odd field figure 26.74 field detection section 26 servo circuits rev.2.00 jan. 15, 2007 page 741 of 1174 rej09b0329-0200 26.15.6 noise detection if a pulse of the horizontal sync signal is missing, a complementary pulse is set at the timing set in hpwr and with the set pulse width. set the noise detection window with hwr of about 1/4 of the horizontal sync signal, and the pulse with equal high and low periods will be obtained. example of setting: assumed that a complementary pulse is set when fosc = 10mhz under the conditions s = 5 mhz, ntsc:th = 63.6 ( s) and hpulse = 4.7 ( s), the set values of the complementary pulse timing (hrtr7-0), complementary pulse width (hpwr3-0), and noise detection window timing (nwr5-0) are expressed by the following equations. (value of hrtr7 ? 0) 2/ s = th ((value of hpwr3 ? 0) + 1) 2/ s = hpulse ((value of nwr5 ? 0) + 1) 2/ s = 1/4 th where, th is the cycle of the horizontal sync signal ( s), hpulse is the pulse width of the horizontal sync signal ( s) and s is the servo clock (hz) (fosc/2). accordingly, (value of hrtr7 ? 0) 0.4 ( s) = 63.6 ( s) hrtr7 ? 0 = h'9f ((value of hpwr3 ? 0) + 1) 0.4 ( s) = 4.7 ( s) hpwr3 ? 0 = h'b ((value of nwr5 ? 0) + 1) 0.4 ( s) = 16 ( s) nwr5 ? 0 = h'27 also, the noise mask period is computed as follows. ((value of hrtr7 ? 0) + 1) ? 24) 2/ s = 54 ( s) where, 24 is a constant required for a structural reason. figure 26.75 shows the set period for hrtr, hpwr, and nwr. section 26 servo circuits rev.2.00 jan. 15, 2007 page 742 of 1174 rej09b0329-0200 legend: seph noise detection window noise mask for osch osch noise mask for h counter h reload counter h counter seph c osch : horizontal sync signal after detection : horizontal sync signal after complement a b : value set for the noise detection window (nwr5 to nwr0) : value set for the pulse width of the horizontal sync signal (npwr3 to npwr0) c a , b , c : value set for complement timing (hrtr7 to hrtr0) : complements of 1 of a,b,c, respectively h ' e8 th : complement of 2 of multiplier 24 in the equation for the noise mask period (the noise mask period ends 24 counts before the overflow of h reload counter.) : cycle of the horizontal sync signal (ntsc:63.6 [ms], pal:64[ms]) tm : timing at which the noise mask period ends. a horizontal sync pulse is missing the pulse in the mask period is ignored th a b h'00 ovf h'e8 c a mask period period determined by nwr5 to nwr0 mask period tm mask period mask period mask period mask period mask period mask period th don ' t mask immediately after complement. period deter- mined by a and a period determined by hrtr7 to hrtr0 period determined by c and h ' e8 period determined by hpwr3 to hper0 period determined by b do mask also im- mediately after complement. figure 26.75 set period for hrtr, hpwr, and nwr section 26 servo circuits rev.2.00 jan. 15, 2007 page 743 of 1174 rej09b0329-0200 noise detection operation: the noise detector considers an irregular pulse of the composite sync signal (csync) and a chip of a horizontal sync signal pulse within a frame as noise. the noise counter takes counts of the irregular pulses during the high period of the noise detection window and the chips and drop-outs of the horizontal sync signal pulses during the low period. the noise detector counts more than one irregular pulses as one. the noise counter is cleared at every frame (vsync is detected twice). the equalizing pulse contained in 9h of the vertical sync signal is counted also as an irregular pulse. the noise detection flag (nois) in the sync signal control register (syncr) is set to 1 if the count of the irregular pulses + the count of the pulse chips and drop-outs of the horizontal sync signal > 4 (value of ndr7 to 0). see the description on the sync signal control register (syncr) is section 26.15.5, register description, for the nois bit. figure 26.76 shows the operation of the noise detection. csync noise detection window noise detection flag (nois) noise counter noise detection level noise detection flag is set. legend: nois : bit 3 of the sync signal control register (syncr) noise figure 26.76 operation of the noise detection section 26 servo circuits rev.2.00 jan. 15, 2007 page 744 of 1174 rej09b0329-0200 26.15.7 activation of the sync signal detector after release of reset or transition from the power down mode to the active mode, the sync signal detector starts operation by a sync signal input after release of module stop. the pulse of the polarity specified by the syct bit of the sync signal control register (syncr) is input to the detector. the detector starts operation even if this pulse is a noise pulse with a width smaller than the regular width. the minimum pulse width which can activate the detector is not constant depending on the internal operation of the input circuit. accordingly, if the assured activation of the detector is required, input a pulse with a width greater than 4/ s ( s = fosc/2 (hz)). in such a case, care is required to noise, because ev en a pulse with a width smaller than 4 /s may cause activation. 26.16 servo interrupt 26.16.1 overview the interrupt exception processing of the servo module is started by one of ten factors, i.e. the drum speed error detector ( 2), drum phase error detector, capstan speed error detector ( 2), capstan phase error detector, hsw timing generator ( 2), sync detector, and ctl circuit. for these interrupt factors, see each of th eir circuit sections of this manual. for details of exception processing, see section 5, exception handling. 26.16.2 register configuration table 26.27 shows the list of the registers which control the interrupt of the servo section. table 26.27 registers which control the interrupt of the servo section name abbrev. r/w size initial value address servo interrupt enable register 1 sienr1 r/w byte h'00 h'd0b8 servo interrupt enable register 2 sienr2 r/w byte h'fc h'd0b9 servo interrupt request register 1 sirqr1 r/w byte h'00 h'd0ba servo interrupt request register 2 sirqr2 r/w byte h'fc h'd0bb section 26 servo circuits rev.2.00 jan. 15, 2007 page 745 of 1174 rej09b0329-0200 26.16.3 register description servo interrupt enable register 1 (sienr1) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 6 0 7 iecap3 iecap2 iecap1 iehsw2 iehsw1 0 r/w iedrm3 r/w r/w r/w iedrm2 iedrm1 bit : initial value : r/w : sienr1 is an 8-bit read/write register that enables or disables interrupts in the servo section. it is initialized to h'00 by a reset, or in stand-by or module stop mode. bit 7 ? drum phase error detection interrupt enable bit (iedrm3) bit 7 iedrm3 description 0 disables the request of the interrupt by irrdrm3 (initial value) 1 enables the request of the interrupt by irrdrm3 bit 6 ? drum speed error detection (lock detect ion) interrupt enable bit (iedrm2) bit 6 iedrm2 description 0 disables the request of the interrupt by irrdrm2 (initial value) 1 enables the request of the interrupt by irrdrm2 bit 5 ? drum speed error detection (ovf, latc h) interrupt enable bit (iedrm1) bit 5 iedrm1 description 0 disables the request of the interrupt by irrdrm1 (initial value) 1 enables the request of the interrupt by irrdrm1 section 26 servo circuits rev.2.00 jan. 15, 2007 page 746 of 1174 rej09b0329-0200 bit 4 ? capstan phase error de tection interrupt enable bit (iecap3) bit 4 iecap3 description 0 disables the request of the interrupt by irrcap3 (initial value) 1 enables the request of the interrupt by irrcap3 bit 3 ? capstan speed error detection (lock det ection) interrupt enable bit (iecap2) bit 3 iecap2 description 0 disables the request of the interrupt by irrcap2 (initial value) 1 enables the request of the interrupt by irrcap2 bit 2 ? capstan speed error detection (ovf, latch) interrupt enable bit (iecap1) bit 2 iecap1 description 0 disables the request of the interrupt by irrcap1 (initial value) 1 enables the request of the interrupt by irrcap1 bit 1 ? hsw timing generation (counter clear, ca pture) interrupt enable bit (iehsw2) bit 1 iehsw2 description 0 disables the request of the interrupt by irrhsw2 (initial value) 1 enables the request of the interrupt by irrhsw2 section 26 servo circuits rev.2.00 jan. 15, 2007 page 747 of 1174 rej09b0329-0200 bit 0 ? hsw timing generation (ovw, matching, strig) interrupt enable bit (iehsw1) bit 0 iehsw1 description 0 disables the request of the interrupt by irrhsw1 (initial value) 1 enables the request of the interrupt by irrhsw1 servo interrupt enable register 2 (sienr2) 0 0 1 0 r/w 2 3 4 5 6 1 7 ? ? ? ? ? ? ? ? ? ? ? ? r/w iesnc iectl 11 11 1 bit : initial value : r/w : sienr2 is an 8-bit read/write register that enables or disables interrupts in the servo section. it is initialized to h'fc by a reset, stand-by or module stop. bits 7 to 2 ? reserved: cannot be modified and are always read as 1. bit 1 ? vertical sync signal interrupt enable bit (iesnc) bit 1 iesnc description 0 disables the request of the interrupt (interrupt to the vertical sync signal) by irrsnc (initial value) 1 enables the request of the interrupt by irrsnc bit 0 ? ctl interrupt enable bit (iectl) bit 0 iectl description 0 disables the request of the interrupt by irrctl (initial value) 1 enables the request of the interrupt by irrctl section 26 servo circuits rev.2.00 jan. 15, 2007 page 748 of 1174 rej09b0329-0200 servo interrupt request register 1 (sirqr1) 0 0 1 0 r/(w) * 2 0 r/(w) * 3 0 4 0 r/(w) * 0 r/(w) * 5 6 0 7 irrcap3 irrcap2 irrcap1 irrhsw2 irrhsw1 0 r/(w) * irrdrm3 r/(w) * r/(w) * r/(w) * irrdrm2 irrdrm1 note: * only 0 can be written to clear the flag. bit : initial value : r/w : sirqr1 is an 8-bit read/write register that indicates interrupt request in the servo section. if the interrupt request has occurred, the corresponding bit is set to 1. only 0 can be written to clear the fl ag. it is initialized to h'00 by a reset, or in stand-by or module stop mode. bit 7 ? drum phase error detector interrupt request bit (irrdrm3) bit 7 irrdrm3 description 0 no interrupt request from the drum phase error detector. (initial value) 1 interrupt requested from the drum phase error detector. bit 6 ? drum speed error detector (lock det ection) interrupt request bit (irrdrm2) bit 6 irrdrm2 description 0 no interrupt request from the drum speed error detector (lock detection). (initial value) 1 interrupt requested from the drum speed error detector (lock detection). bit 5 ? drum speed error detector (ovf, la tch) interrupt request bit (irrdrm1) bit 5 irrdrm1 description 0 no interrupt request from the drum speed error detector (ovf, latch). (initial value) 1 interrupt requested from the drum speed error detector (ovf, latch). section 26 servo circuits rev.2.00 jan. 15, 2007 page 749 of 1174 rej09b0329-0200 bit 4 ? capstan phase error detector interrupt request bit (irrcap3) bit 4 irrcap3 description 0 no interrupt request from the capstan phase error detector. (initial value) 1 interrupt requested from the capstan phase error detector. bit 3 ? capstan speed error detector (lock detection) interrupt request bit (irrcap2) bit 3 irrcap2 description 0 no interrupt request from the capstan speed error detector (lock detection). (initial value) 1 interrupt requested from the drum speed error detector (lock detection). bit 2 ? drum speed error detector (ovf, la tch) interrupt request bit (irrcap1) bit 2 irrcap1 description 0 no interrupt request from the capstan speed error detector (ovf, latch). (initial value) 1 interrupt requested from the capstan speed error detector (ovf, latch). bit 1 ? hsw timing generator (counter clear, capture) interrupt permission bit (irrhsw2) bit 1 irrhsw2 description 0 no interrupt request from the hsw timing generator (counter clear, capture). (initial value) 1 interrupt requested from the hsw timing generator (counter clear, capture). section 26 servo circuits rev.2.00 jan. 15, 2007 page 750 of 1174 rej09b0329-0200 bit 0 ? hsw timing generator (ovw, matching, strig) interrupt permission bit (irrhsw1) bit 0 irrhsw1 description 0 no interrupt request from the hsw timing generator (ovw, matching, strig). (initial value) 1 interrupt requested from the hsw timing generator (ovw, matching, strig). servo interrupt request register 2 (sirqr2) 0 0 1 0 r/(w) * 2 3 4 5 6 1 7 ? ? ? ? ? ? ? ? ? ? ? ? r/(w) * irrsnc irrctl 11 11 1 note: * only 0 can be written to clear the flag. bit : initial value : r/w : sirqr2 is an 8-bit read/write register that indicates interrupt request in the servo section. if the interrupt request has occurred, the corresponding bit is set to 1. writing 0 after reading 1 is allowed; no other writing is allowed. it is initialized to h'fc by a reset, or in stand-by or module stop mode. bits 7 to 2 ? reserved: cannot be modified and are always read as 1. bit 1 ? vertical sync signal interrupt request bit (irrsnc) bit 1 irrsnc description 0 no interrupt request from the sync signal detector (vd, noise) (initial value) 1 interrupt requested from the sync signal detector (vd, noise) bit 0 ? ctl signal interrupt request bit (irrctl) bit 0 irrctl description 0 no interrupt request from ctl (initial value) 1 interrupt requested from ctl section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 751 of 1174 rej09b0329-0200 section 27 sync separator for osd and data slicer 27.1 overview the sync separator separates the horizontal s ync signal and vertical sync signal from the composite video signal input from the cvin2 terminal and sends the sync signals to the on screen display (osd) module and data slicer. the sync separator has an automatic frequency controller (afc), which generates a reference clock at 576 or 448 times the horizontal sync signal frequency. this reference clock is used to separate the horizontal sync signal from the com posite video signal. the afc receives the hsync signal processed by the h complement and mask counter. the h complement and mask counter removes noise and equalizing pulses from the hsync signal and interpolates necessary pulses for the hsync signal. the sync separator separates the vertical sync signal from the composite video signal through the counting operation of the v complement and mask counter. the v complement and mask counter increments the count at double the frequency of the horizontal sync signal to mask the vsync noise and to generate complementary pulses for the vsync signal according to the register settings. through the above functions, the sync signals can be separated correctly against noise input to the cvin2 terminal, motor skew due to vcr tape playback or special-function playback, and abnormal noise in a weak field. in addition, the sync separator provides the field detection function necessary for the data slicer, and the noise detection function necessary for t uner detection (detecting the tuning status). as the afc reference clock is also used as the dot clock of the osd, switching the reference clock can change the dot width of the display. when the text display mode of the osd is used, refer to section 27.3.6, automatic frequency controller (afc). in addition to the cvin2 video signal, the following signals can be selected as sources of sync separation through the external circuit and register settings: the csync composite sync signal input from the csync/hsync terminal, and the separate vsync and hsync signals input from the vlpf/vsync and csync/hsync terminals, respectively. section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 752 of 1174 rej09b0329-0200 27.1.1 features ? horizontal sync signal separation: stable sepa ration is provided by the afc, and complement and mask functions are available. ? afc reference clock frequency: 576 or 448 times th e frequency of the horizontal sync signal can be selected. ? vertical sync signal separation: the masking and complement functions are available through the v complement and mask counter. ? the source for sync separation can be selected from three signals (five methods). 1. composite video signal input from the cvin2 terminal 2. csync signal input from the csync/hsync terminal 3. vsync and hsync signals that are input from the vlpf/vsync and csync/hsync terminals, respectively ? csync separation comparator: the slice level can be selected by register settings. ? polarity of the csync/hsync terminal input: the signal detection polarity can be selected. ? polarity of the vlpf/vsync terminal input: the signal detection polarity can be selected. ? noise detection: noise during one frame is counted and a noise detection interrupt is generated when the count reaches the specified value. ? noise detection counter: the count is readable and is reset every other vertical sync signal input. ? field detection: the odd or even field for interlace scanning is distinguished. ? reference hsync signal for the afc: the reference hsync signal can be selected. ? v complement and mask counter: the source for the counter clock (twice the frequency of the horizontal sync signal) can be selected. ? internal csync generator: the clock source for the internal csync generator can be selected. 27.1.2 block diagram figure 27.1 shows the block diagram of the sync separator. section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 753 of 1174 rej09b0329-0200 slicin g volta g e control separation method di g ital h separation counter vvth re g ister selectin g 576 or 448 as the division ratio di g ital lpf on switchin g switchin g reference hsync internally g enerated hsync external hsync switchin g switchin g frequency-dividin g counter complement and mask settin g re g ister switchin g switchin g reset for v reset for h tv format in h (self- runnin g ) internal csync g enerator afc error output circuit (comparator) when the data slicer is used and the text display mode is selected in the osd, the afc clock is selected; the clock is also used as the dot clock. when the data slicer is not used and the text display mode is selected in the osd, the self-runnin g si g nal is selected. switchin g switchin g switchin g switchin g switchin g reference clock 4/2fsc maskin g complement and mask complement enable bit (self-runnin g ) field detection window field detection field detection window re g ister hvth re g ister noise detection noise detection window noise counter noise detection interrupt : re g ister v complement enabled: complemented and masked v v complement disabled: masked v external vsync (data slicer) external vsync interrupt field si g nal (data slicer) external hsync (data slicer) detection window si g nals for data slicer (data slicer) internally g enerated sync si g nal (osd) clock run-in period and start bit period afch dot clock (osd) noise detection level re g ister csync separation comparator i/o switchin g polarity switchin g polarity switchin g cvin2 hsync vsync si/text hcksel (te) (0) (1) (si) seph 1/2 u/d inv hhk c h complement and mask counter (complement and mask functions) r osch afcv si/text sepv osc2h c r c c r di g ital v separation counter u/d c /2 /2 /2 csync/hsync vsync/vlpf (1) (0) (te) osdfld osdv (osd) si = afcv text = inv osdh (osd) field si g nal (osd) si = afcfld text = infld (te) (0) (1) (0) (1) infld afcfld (si) (si) si/text hcksel switchin g dotcksl vcksl afc2h 2 fh 4/2fsc si/text afcosc afcpc afclpf afc (si) afch afc oscillator hsel (te) v complement and mask counter (complement and mask functions) r c figure 27.1 sync separator block diagram section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 754 of 1174 rej09b0329-0200 27.1.3 pin configuration table 27.1 shows the pin configuration of the sync separator. table 27.1 sync separator pin configuration name abbrev. i/o function csync/hsync input/output composite sync signal input/output or horizontal sync signal input sync signal input/output vlpf/vsync input pin for connecting external lpf for vertical sync signal or input pin for vertical sync signal afcosc input/output afc oscillation signal afc oscillation signals afcpc input/output afc by-pass capacitor connecting pin lpf for afc afclpf input/output external lpf connecting pin for afc composite video signal cvin2 input composite video signal input (2 vpp, with a sync tip clamp circuit) 27.1.4 register configuration table 27.2 shows the sync separator registers. table 27.2 sync separator registers name abbrev. r/w size initial value address * 1 sync separation input mode register sepimr r/w byte h'00 h'd240 sync separation control register sepcr r/(w) * 2 byte h'00 h'd241 sync separation afc control register sepacr r/(w) * 2 byte h'10 h'd242 horizontal sync signal threshold register hvthr w byte h'e0 h'd243 vertical sync signal threshold register vvthr w byte h'00 h'd244 field detection window register fwidr w byte h'f0 h'd245 h complement and mask register hcmmr w word h'0000 h'd246 noise detection counter ndetc r byte h'00 h'd248 noise detection level register ndetr w byte h'00 h'd248 data slicer detection window register ddetwr w byte h'00 h'd249 internal sync signal frequency register infrqr w byte h'10 h'd24a notes: 1. lower 16 bits of the address. 2. only 0 can be written to clear the flag. section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 755 of 1174 rej09b0329-0200 27.2 register description 27.2.1 sync separation input mode register (sepimr) 0 0 0 0 0 0 0 0 7 r/w frqsel 0 r/w ccmpv1 6 r/w ccmpv0 5 r/w compsl 4 r/w synct 3 r/w vsel 2 r/w dlpfon 1 ? ? bit : initial value : r/w : the sepimr is an 8-bit read/write register for selecting the source signals for sync separation. in addition to the internal switches controlled by this register setting, the external circuits are used to select the sources of the hsync and vsync signals to be supplied to the digital h separation counter and the digital v separation counter, respectively. figure 27.2 and table 27.3 show the source signal selection. the sepimr also specifies the slicing voltage of the csync separation comparator, switches the polarity of the signals input from the csync/hsync and vlpf/vsync terminals, turns on or off the digital lpf, and switches the reference clock frequency for the afc. for details on the source signals for sync separation, refer to section 27.3.1, selecting source signals for sync separation. when reset, the sepimr is initialized to h'00. bits other than bit 5 (ccmpsl) ar e cleared to 0 in module stop, sleep, standby, watch, subactive, and subsleep modes. section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 756 of 1174 rej09b0329-0200 cvin csync a 1 1 0 0 b a b hsync vsync vlpf vlpf/vsync csync/hsync hsync vsync dlpfon external sw3 internal sw5 internal sw6 external sw2 external sw1 reference volta g e switch re g ister control i/o switch i/o switch polarity switch sync tip clamp di g ital v separation counter csync polarity schmitt circuit vsync polarity schmitt circuit external circuit inside lsi csync separation comparator external sw4 cvin2 ? + ccmpsl ccmpv0, 1 synct vsel sepv seph di g ital h separation counter polarity switch figure 27.2 diagram of the circuit for selecting the so urce signals for sync separation table 27.3 source signals for sync separation input source vsync detector external sw1 external sw2 external sw3 external sw4 ccmpsl (internal sw5) vsel (internal sw6) csync/ hsync terminal cvin2 input vsync schmitt off on a a 0 0 output csync schmitt off off open input fixed to ovss 0 1 output csync input vsync schmitt on on a a 1 0 input csync schmitt on off a input fixed to ovss 1 1 input hsync/ vsync input vsync schmitt off off b b 1 0 input section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 757 of 1174 rej09b0329-0200 bits 7 and 6 ? csync separation comparator slicing voltage select (ccmpv1 and ccmpv0): select the slicing voltage for the csync separation comparator. the value set by these bits is the slicing level against th e sync tip level (?40 ire). note that this slicing level is used only for reference. bit 7 bit 6 ccmpv1 ccmpv0 description 0 0 the csync slicing level is 10 ire (initial value) 1 the csync slicing level is 5 ire 1 0 the csync slicing level is 15 ire 1 the csync slicing level is 20 ire bit 5 ? csync separation comparator input select (ccmpsl): controls internal switch sw5 to select whether to use the csync separation comparator input or csync schmitt input. writing 0 to this bit selects the csync separation comparator input, and writing 1 selects the csync schmitt input. this bit also controls the input/output status of the csync/h sync terminal. writing 0 to this bit makes the csync/hsync an output terminal, and writing 1 makes it an input terminal. this bit is cleared to 0 only at reset. note that the csync/hsync terminal enters a high-impedance state at reset and in sleep, subactive, subsleep, watch, standby, and module stop modes*. bit 5 ccmpsl description 0 the csync separation comparator input is selected the csync/hsync terminal operates as an output terminal (initial value) 1 the csync schmitt input is selected the csync/hsync terminal operates as an input terminal note: * when this bit is set to 1, it must be set to 1 by the instruction following the module stop release instruction in the interrupt-prohibited state. orc #b'10000000, ccr interrupt prohibited bclr.b #1, @mstpcrh module stop release bset.b #5, @sepimr sets ccmpsl bit to 1 andc #b'01111111, ccr interrupt permitted section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 758 of 1174 rej09b0329-0200 bit 4 ? sync signal polarity select (synct): this bit selects the polarity of the csync/hsync and vlpf/vsync input signals. when using the cvin2 input signal, be sure to write 0 to this bit to select the positive polarity. bit 4 synct description 0 (initial value) 1 bit 3 ? vsync input signal select (vsel): controls internal switch sw6 to select the vsync input signal. writing 0 to this bit selects the vsync schmitt input, and writing 0 selects the csync schmitt input. bit 3 vsel description 0 vsync schmitt input (initial value) 1 csync schmitt input bit 2 ? digital lpf control (dlpfon): specifies the digital lpf function, which masks noise components of the vsync signal in a weak field. the digital lpf logically ors the csync signal (vsync signal) and the seph signal that is separated by the digital h separation counter, then inputs the ored result to the digital v separation counter. this function prevents vsync detection delay and vsync detection miss in a weak field. for the timing, refer to section 27.2.5, vertical sync signal threshold register (vvthr). bit 2 dlpfon description 0 the digital lpf does not operate (initial value) 1 the digital lpf operates bit 1 ? reserved: cannot be modified and is always read as 0. when 1 is written to this bit, correct operation is not guaranteed. section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 759 of 1174 rej09b0329-0200 bit 0 ? reference clock frequency select (frqsel): selects the frequency of the reference clock for the afc: 576 times or 448 times the horizontal sync signal frequency. to obtain a desired reference clock frequency, connect an exte rnal circuit of a value suitable for the desired frequency to the afcosc and afcpc terminals, and select the division ratio of the frequency dividing counter with this bit. this afc reference clock is also used as the dot clock for the osd; change this frequency to adjust the dot width of the display characters. note that the data slicer will operate when 448 times the horizontal sync fre quency is selected. for details, refer to section 27.3.6, automatic frequency controller (afc). bit 0 frqsel description 0 576 times the horizontal sync frequency (initial value) 1 448 times the horizontal sync frequency section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 760 of 1174 rej09b0329-0200 27.2.2 sync separation control register (sepcr) 0 0 0 0 0 0 0 0 7 r fld 0 r/w afcvie 6 r/(w) * afcvif 5 r/w vcksl 4 r/w vcmpon 3 r/w hcksel 2 r/w hhkon 1 r/w hhkon2 bit : initial value : r/w : note: * only 0 can be written to clear the fla g . the sepcr is an 8-bit read/write register for controlling the external vsync interrupt, enabling or disabling the v complement function, selecting the clock source for the v complement and mask counter, selecting the clock source for the internal csync generator, and indicating the field detected by the afc. the sepcr is initialized to h'00 by a reset, in module stop mode, in sleep mode, in standby mode, in watch mode, in subactive mode, or in subsleep mode. bit 7 ? external vsync interrupt enable (afcvie): enables or disables the external vsync interrupt to be requested when the afcvif is set to 1. bit 7 afcvie description 0 the external vsync interrupt is disabled (initial value) 1 the external vsync interrupt is enabled bit 6 ? external vsync interrupt flag (afcvif): this flag is set to 1 when the v complement and mask counter detects the external vsync signal (the afcv signal). for the vsync interrupt generated in the osd, refer to section 29, on-screen display (osd). bit 6 afcvif description 0 [clearing condition] 1 is read, then 0 is written (initial value) 1 [setting condition] the v complement and mask counter detects the external vsync signal (afcv signal) bit 5 ? v complement and mask counter clock source select (vcksl): selects the clock source for the v complement and mask counter: double the frequency of the horizontal sync signal for the afc (afch signal) or that for the h complement and mask counter (osch signal). when the text display mode is selected for the osd and internally generated hsync signal is selected as the reference hsync signal for the afc by setting the hsel bit (bit 5) of the sepacr, setting this section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 761 of 1174 rej09b0329-0200 vcksl bit to 1 enables the external vsync signal to be detected irrespectively of the text display mode operation. bit 5 vcksl description 0 double the frequency of the horizontal sync signal (afch signal) for the afc (initial value) 1 double the frequency of the horizontal sync signal (osch signal) for the h complement and mask counter bit 4 ? v complement function control (vcmpon): enables or disables the v complement function of the v complement and mask counter. the v complement function prevents the vsync detection being delayed and missed in a weak field. for the timing, refer to section 27.2.5, vertical sync signal threshold register (vvthr). bit 4 vcmpon description 0 the v complement function is disabled (initial value) 1 the v complement function is enabled bit 3 ? internal csync generator cl ock source select (hcksel): selects the clock source for the internal csync generator: the 4/2 fsc clock or the afc reference clock. when the text display mode is selected for the osd a nd the external hsync signal is se lected as the reference hsync signal for the afc, set this hcksel bit to 1 to generate the internal csync signal from the afc reference clock. in this case, however, the hsync and vsync signals must be dedicated separation inputs, with both signals having equal cycles and pulse widths. this bit must be cleared to 0 when bit 1 (dotcksl) of sepacr is set to 1. bit 3 hcksel description 0 4/2 fsc clock (initial value) 1 afc reference clock bit 2 ? hhk forcibly turned on (hhkon): forcibly operates the half hsync killer (hhk)* function when the h complement and mask counter interpolates complementary pulses three successive times. when the hvthr is set within the range from 2.35 s to 4.7 s to remove equalizing pulses by using the digital h separation counter, the hhk function prevents hsync- section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 762 of 1174 rej09b0329-0200 vsync phase-difference errors during the v blanking period. for the timing, refer to section 27.2.4, horizontal sync signal threshold register (hvthr). note: * hhk: half hsync killer bit 2 hhkon description 0 the hhk is not operated when complementary pulses are interpolated three successive times (initial value) 1 the hhk is forcibly operated when complementary pulses are interpolated three successive times bit 1 ? hhk forcibly turned on 2 (hhkon2): forcibly operates the half hsync killer (hhk) during the v blanking period. thus the hhk function can be forcibly operated after an interpolation operation even when the hsync signal is not input. when the hvthr is set within the range from 2.35 s to 4.7 s to remove equalizing pulses by using the digital h separation counter, this is an effective countermeasure against erroneous field or line detection that occurs when there is no hsync signal input in the case of a weak electric field, etc., or when noise is superimposed. for the timing, refer to section 27.2.4, horizontal sync signal threshold register (hvthr). bit 1 hhkon2 description 0 the hhk is not forcibly operated during the v blanking period (initial value) 1 the hhk is forcibly operated during the v blanking period bit 0 ? field detection flag (fld): indicates the field status determin ed by the status of the field detection window signal generated by the afc when the external vsync signal (afcv signal) rises. this flag is invalid when the internally generated hsync signal is selected as the afc reference hsync signal. for the timing, refer to section 27.2.6, field detection window register (fwidr). bit 0 fld description 0 even field (initial value) 1 odd field section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 763 of 1174 rej09b0329-0200 27.2.3 sync separation afc control register (sepacr) 0 0 0 0 0 1 0 0 7 r/w dsl32b 0 r/w ndetie 6 r/(w) * ndetif 5 r/w hsel 4 ? ? 3 ? ? 2 r/w arst 1 r/w dotcksl bit : initial value : r/w : note: * only 0 can be written to clear the fla g . the sepacr is an 8-bit read/write register for controlling the afc. the afc generates a reference clock of 576 or 448 times the frequency of the horizontal sync signal. from this reference clock, several signals such as the hor izontal sync signal (afch signal), clock run-in detection window signal, or start bit detection wind ow signal are generated. the reference clock is also used as the dot clock for the osd. the afc reference hsync signal can be switched between the external hsync signal and the internally generated hsync signal. in addition, the sepacr has a function for controlling the noise detection interrupt and enabling or disabling the afc reset function. the sepacr is initialized to h'10 by a reset, in module stop mode, in sleep mode, in standby mode, in watch mode, in subactive mode or in subsleep mode. bit 7 ? noise detection interrupt enable (ndetie): enables or disables the noise detection interrupt to be requested when the ndetif is set to 1. bit 7 ndetif description 0 the noise detection interrupt is disabled (initial value) 1 the noise detection interrupt is enabled bit 6 ? noise detection int errupt flag (ndetif): this flag is set to 1 when the noise detection counter value matches the noise detection level register value. bit 6 ndetif description 0 [clearing condition] 1 is read, then 0 is written (initial value) 1 [setting condition] the noise detection counter value matches the noise detection level register value section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 764 of 1174 rej09b0329-0200 bit 5 ? reference hsync signal select (hsel): selects the reference hsync signal for the afc: the external hsync signal or the internally generated hsync signal. when using the data slicer, select the external hsync signal. when not using the data slicer but using the text display mode for the osd, select the internally generated hsync si gnal. before this bit setting is modified, the osd display should be turned off. bit 5 hsel description 0 the external hsync signal is selected (initial value) 1 the internally generated hsync signal is selected bit 4 ? blank bit: cannot be read or modified. bit 3 ? reserved: cannot be modified and is always read as 0. when 1 is written to this bit, correct operation is not guaranteed. bit 2 ? afc reset control (arst): enables or disables the afc reset function. when a vcr motor skew occurs or the channel is switched, and if the hsync signal (afch signal) output from the afc differs in phase from the reference hsync signal input to the afc, the afc is reset to eliminate the phase difference and to lock the afch signal phase to that of the reference signal. bit 2 arst description 0 the reset function is disabled (initial value) 1 the reset function is enabled bit 1 ? dotcksl bit (dotcksl): selects the dot-clock source of the osd. when this bit is reset to 0, the reference clock of the afc circuit is selected. when this bit is set to 1, the 4/2fsc clock that is input from 4/2fsc in pin is selected. when this bit is set to 1, use the osd in text display mode. when this bit is set to 1 in superimposed mode or when hcksel in sepcr is set to 1, characters will flicker. when a 4fsc clock is input while this bit is set to 1, the osd display becomes smaller in the horizontal derection; be sure to input a 2fsc clock. to operate the data slicer in text display mode, set this bit to 1. bit 1 dotcksl description 0 the reference clock of the afc circuit is selected for the dot clock (initial value) 1 the 4/2fsc clock is selected for the dot clock section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 765 of 1174 rej09b0329-0200 bit 0 ? dsl32b bit (dsl32b): sets 16-bit or 32-bit mode slice operation of the data slicer. for details, see section 28.4, 32-bit slice operation. bit 0 dsl32b description 0 16-bit mode is set for the slice operation (initial value) 1 32-bit mode is set for the slice operation 27.2.4 horizontal sync signal threshold register (hvthr) 0 0 0 0 0 0 1 1 7 w hvth0 1 ? ? 6 ? ? 5 ? ? 4 w hvth4 3 w hvth3 2 w hvth2 1 w hvth1 bit : initial value : r/w : the hvthr is a 5-bit write-only register for specifying the threshold value for the digital h separation counter; this value is used to generate the seph signal from the csync signal. the seph signal is set to 1 when the digital h separation counter value matches the hvthr value while the csync is high, and is reset to 0 when the digital h separation counter value becomes 00 while the csync is low. the hvthr is initialized to h'e0 by a reset, in module stop mode, in sleep mode, in standby mode, in watch mode, in subactive mode or in subsleep mode. figures 27.3 and 27.4 show the hvth value and the seph signal generation timing. csync hvth seph di g ital h separation counter about 1.6 s to 2.0 s figure 27.3 hvth value and seph generation timing when equalizing pulses are detected section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 766 of 1174 rej09b0329-0200 csync hvth seph di g ital h separation counter about 3.2 s to 3.6 s figure 27.4 hvth value and seph generation timing when equalizing pulses are not detected the following shows examples of hvthr settings. condition: (hvthr ? 1) (2/osc) > 1.6 s or 3.2 s system clock osc = 10 mhz 2/osc (5 mhz = 0.2 s) example 1: to detect equalizing pulses hsync detection threshold value: 1.6 s 1.6 s / 0.2 s = 8 hvthr value = h'8 (8) example 2: to not detect equalizing pulses hsync detection threshold value: 3.2 s 3.2 s / 0.2 s = 16 hvthr value = h'10 (16) in general, to detect hsync pulses continuously, set the hvth value so that 2.35- s equalizing pulses can be detected. however, if an equalizing pulse at an hsync pulse position is lost in a weak field, a hsync-vsync phase-difference error will occur, and the field will not be detected correctly. in such a weak field, this er ror can be prevented by eliminating 2.35- s equalizing pulses. figure 27.5 shows the timing when a phase-difference error occurs. section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 767 of 1174 rej09b0329-0200 csync hvth seph hhk osch hc di g ital h separation counter hsync-vsync phase-difference error pulse lost h complement and mask counter comple- ment comple- ment figure 27.5 timing of hsyn c-vsync phase-difference error when equalizing pulse lost at hsync pulse position note: when 2.35- s equalizing pulses are eliminated, the complement function operates for the eliminated period. accordingly, the rising edge of the vsync signal for the even field is detected as an hsync pulse. therefore, to not generate an hsync pulse at this position, set the hhkon bit (bit 2) of the sepcr to 1 so that the hhk function is forcibly operated when complementary pulses are inserted th ree successive times. figures 27.6 and 27.7 show this timing. csync hvth seph hhk osch hc di g ital h separation counter comple- ment comple- ment comple- ment comple- ment phase-difference error h complement and mask counter comple- ment comple- ment comple- ment figure 27.6 timing of hsyn c-vsync phase-difference error when equalizing pulse not detected section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 768 of 1174 rej09b0329-0200 csync hvth seph hhk osch hc di g ital h separation counter h complement and mask counter forcible hhk operation forcible hhk operation comple- ment comple- ment comple- ment comple- ment comple- ment comple- ment figure 27.7 timing of hhk operation when complementary pulses inserted three successive times while hhkon = 1 note: when 2.35-s equalizing pulses are eliminat ed, the complement function operates for the eliminated period. accordingly, when there is no hsync signal input in the case of a weak electric field, etc., an d noise is superimposed, the noise is detected as an hsync pulse. therefore, in order not to generate an hsync pulse in this case, set the hhkon2 bit (bit 1) of the sepcr register to 1. figures 27.8 and 27.9 show this timing. csync hvth seph hhk osch di g ital h separation counter h complement and mask counter comple- ment comple- ment comple- ment comple- ment comple- ment comple- ment hsync-vsync phase-difference error pulse lost, noise figure 27.8 timing of hsyn c-vsync phase-difference error due to noise occurrence after equalizing pulse is lost at hsync pulse position section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 769 of 1174 rej09b0329-0200 csync hvth seph hhk osch di g ital h separation counter h complement and mask counter comple- ment comple- ment comple- ment comple- ment comple- ment comple- ment forcible hhk operation pulse lost, noise figure 27.9 timing of forcible hhk operation in v blanking period when equalizing pulse is not detected 27.2.5 vertical sync signal threshold register (vvthr) 0 0 0 0 0 0 0 0 7 w vvth0 0 w vvth7 6 w vvth6 5 w vvth5 4 w vvth4 3 w vvth3 2 w vvth2 1 w vvth1 bit : initial value : r/w : the vvthr is an 8-bit write-only register for specifying the threshold value for the digital v separation counter; this value is used to generate the sepv signal from the csync signal. the sepv signal is set to 1 when the digital v separation counter value matches the vvthr value while the csync is high, and reset to 0 when the digital v separation counter value becomes 00 while the csync is low. set the vvthr value so that the sepv signal goes high 1/2h or more after the vsync start point. the vvthr is initialized to h'00 by a reset, in module stop mode, in sleep mode, in standby mode, in watch mode, in subactive mode or in subsleep mode. figure 27.10 shows the vvthr value and the sepv signal generation timing. section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 770 of 1174 rej09b0329-0200 csync 1/2 h or more vvth h sepv di g ital v separation counter figure 27.10 vvth value and sepv generation timing the following shows an example of vvthr settings. condition: (vvthr ? 1) (2/osc) > (hsync period / 2 ? 4.7 s) 1.5 = 41 s system clock osc = 10 mhz 2/osc (5 mhz = 0.2 s) example 1: to detect 41- s pulses vsync detection threshold value: 41 s 41 s / 0.2 s = 205 hvthr value = h'ce (206) the noise component of the csync signal in a weak field is usually large, and will cause the vsync detection delay or miss. in such a case, set the dlpfon (bit 2) of the sepimr to 1; the seph signal detected by the digital h separation counter is logically ored with the csync signal (vsync), then the result is inpu t to the digital v separation count er. this will prevent the vsync detection delay or miss in a weak field. figure 27.11 shows this timing. section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 771 of 1174 rej09b0329-0200 csync + seph hvth seph sepv vvth di g ital h separation counter di g ital v separation counter figure 27.11 vvth value and sepv generation timing when digital lpf is enabled alternatively, set the vcmpon (bit 4) of the sepcr to 1 when the vsync detection delay or miss may occur in a weak field; the external vsync detection signal (afcv signal) will be generated by the v complement and mask counter. figure 27.12 shows this timing. csync vvth sepv 521 522 523 524 0 1 2 3 4 5 6 7 8 afcv 1/2 afch (v samplin g clock) di g ital h separation counter v complement and mask counter figure 27.12 afcv generation timing when v complement function is enabled (for ntsc) section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 772 of 1174 rej09b0329-0200 27.2.6 field detection window register (fwidr) 0 0 0 0 0 1 1 1 7 w fwid0 1 ? ? 6 ? ? 5 ? ? 4 ? ? 3 w fwid3 2 w fwid2 1 w fwid1 bit : initial value : r/w : the fwidr is a 4-bit write-only register for specifying the field detection window timing in units of 16 fh (fh: horizontal sync signal frequency). the field detection window signal is reset to 0 when the afc dividing counter value matches the fwidr value, and the signal is again set to 1 when 1/2 the hsync signal period has passed. at a rising edge of the afcv signal while the field detection window signal is 1, the field is determined as an odd one, and the field detection flag (fld) is set to 1. at a rising edge of the afcv signal while the field detection window signal is 0, the field is determined as an ev en one, and the fld is cleared to 0. the value set to the fwidr depends on the setting of the v complement function control (vcmpon) bit (bit 4) of the sepcr. when the vcmpon is clear ed to 0, that is, when the v complement function is not operating, the fwidr must be set so that the rising edge of the sepv signal, which is generated when the v separation counter valu e reaches the specified threshold value, comes to the center of the field detection window period. when the vcmpon is set to 1, that is, when the v complement function is operating, the fwidr must be set so that the dividing counter overflow timing comes to the center of the field detection window period. the fwidr is initialized to h'f0 by a reset, in module stop mode, in sleep mode, in standby mode, in watch mode, in subactive mode or in subsleep mode. (1) bit 0 of sepcr register bit 0 ? field detection flag (fld): indicates the field determined by the status of the field detection window signal generated by the afc when the external vsync signal (afcv signal) rises. this flag is invalid when the internally generated hsync signal is selected as the afc reference hsync signal. for the timing, refer to figure 27.13 field detection timing. bit 0 fld description 0 even field (initial value) 1 odd field section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 773 of 1174 rej09b0329-0200 csync sepv afcv fld afcv t f * t f * note: * t f : field detection window re g ister value fld di g ital v separation counter v complement and mask counter clock when v complement function is not operatin g : afc frequency- dividin g counter h/2 s field detection window si g nal field detection window si g nal odd field odd field timin g even field timin g when v complement function is operatin g : even field figure 27.13 field detection timing section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 774 of 1174 rej09b0329-0200 27.2.7 h complement and mask timing register (hcmmr) 15 0 hc8 hc7 hc6 hc5 hc4 hc3 hc2 hc1 hc0 hm6 hm5 hm4 hm3 hm2 hm1 hm0 w 14 0 w 13 12 0 w 0 w 11 0 w 10 0 w 9 0 w 8 0 w 7 0 w 6 0 w 5 0 w 4 0 w 3 0 w 2 0 w 1 0 w 0 0 w bit : initial value : r/w : the hcmmr is a 16-bit write-only register for specifying the timing (th: hsync frequency) for generating a complementary pulse when a pulse in the hsync signal is lost, and the timing (tm and tm2) for clearing the hhk (masking period). the hc8 to hc0 bits specify the timing for generating a complementary pulse; if no hsync pulse is input within this specified time, a complementary pulse is generated from the h complement and mask counter. when a supplementary pulse is generated, the hhk function, provided for resetting the h supplement mask counter, remains cleared, and the h supplement mask counter is synchronized with the hsync signal at the next hsync pulse input. the hhk2 operation for generating the hsync signal (osch) for the afc circuit is performed when a supplementary pulse is generated. the hm6 to hm0 bits specify the timing for clearing the hhk function. set the hhk clearing timing to about 85% of the hsync period starting from the seph rising edge to eliminate equalizing pulses and copy-guard signals. figure 27.14 shows the complement and mask timing. the hhk signal is set to 1 about 5 s after the seph rising edge, and the hhk2 signal is set to 1 immediately after the h complement and mask counter is reset. the hhk signal is also us ed for the noise detection window. for details on the noise detection, refer to section 27.2.8, no ise detection counter (ndetc) and section 27.2.9, noise detection level register (ndetr). the hcmmr is initialized to h'0000 by a reset, in module stop mode, in sleep mode, in standby mode, in watch mode, in subactive mode or in subsleep mode. section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 775 of 1174 rej09b0329-0200 csync hvth seph osch tm2 tm th 5 s hc hm di g ital h separation counter noise killer killer killer killer killer killer killer killer pulse lost comple- mentary pulse h complement and mask counter hhk (for counter reset) hhk2 (for osch g eneration) figure 27.14 complement and mask timing of the h complement and mask counter bits 15 to 7 ? h complementary pulse setting (hc8 to hc0): specify the timing for generating a complementary pulse when an hsync pulse is lost. if no hsync pulse is input within the specified time, a complementary pulse is generated from the h complement and mask counter and interpolated to the osch signal. the following shows examples of hc8 to hc0 settings. condition: (hc + 1) (2/osc) > 63.5 s (pal: 64 s) system clock osc = 10 mhz 2/osc (5 mhz = 0.2 s ) example 1: to set the timing for ntsc ntsc: 63.5 s 63.5 s / 0.2 s = 317.5 hc8 to hc0 value = h'13e (318) example 2: to set the timing for pal pal: 64 s 64 s / 0.2 s = 320 hc8 to hc0 value = h'141 (321) section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 776 of 1174 rej09b0329-0200 bits 6 to 0 ? hhk period setting (hm6 to hm0): specify the timing fo r clearing the hhk (masking period) for the hsync signal. the h complement and mask counter starts counting at a rising edge of the seph signal; the hhk period specified by these bits starts at this timing. this value is also used as the timing for resetting the noise detection window signal. note that the setting precision is the upper six bits of the h complement and mask counter: the lower two bits of the counter are ignored. the following shows an example of hm6 to hm0 settings. condition: (hm + 1) (8/osc) > 54 s (about 85% of the hsync period ) system clock osc = 10 mhz 8/osc: 1.25 mhz (0.8 s ) example: to set the timing to 54 s 54 s / 0.8 s = 67.5 hm6 to hm0 value = h'44 (67) 27.2.8 noise detection counter (ndetc) 0 0 0 0 0 0 0 0 7 r nc0 0 r nc7 6 r nc6 5 r nc5 4 r nc4 3 r nc3 2 r nc2 1 r nc1 bit : initial value : r/w : the ndetc is a 10-bit read-only counter of which the upper eight bits can be read. this counter counts the number of hsync cycles in which an hsync pulse (noise h) is input while the noise detection window signal is 1, and counts the number of hsync cycles in which no hsync pulse is input while the noise detection window signal is 0. when this counter value matches the noise detection level, the noise detection interrupt request flag is set. the counter is reset at every other vertical sync signal (afcv signal) input; that is, the noise status for one field can be monitored. the ndetc value can be read by the cpu; the noise status can be monitored by the read value. the ndetc is initialized to h'00 by a reset, in module stop mode, in sleep mode, in standby mode, in watch mode, in subactive mode or in subsleep mode. the ndetc is assigned to the same address as the ndetr. figure 27.15 shows the timing for noise detection. section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 777 of 1174 rej09b0329-0200 27.2.9 noise detection level register (ndetr) 0 0 0 0 0 0 0 0 7 w nr0 0 w nr7 6 w nr6 5 w nr5 4 w nr4 3 w nr3 2 w nr2 1 w nr1 bit : initial value : r/w : the ndetr is an 8-bit write-only register for specifying the noise detection level. the set value must be 1/4 of the actual noise detection level. the noise detection window signal is set to 1 at a falling edge of the osch signal, and reset to 0 after the time specified by the hhk period setting bits has passed. the osch signal falls about 5 s after a rising edge of the seph signal. when the noise detection counter value matches the specified noise detection level, the noise detection interrupt request flag is set to 1. th e ndetr is initialized to h'00 by a reset, in module stop mode, in sleep mode, in standby mode, in watch mode, in subactive mode or in subsleep mode. the ndetr is assigned to the same address as the ndetc. figure 27.15 shows the timing for noise detection. csync afcv ndetc ndetr seph osch ndetif hm h complement and mask counter cleared to 0 by cpu noise detection window noise noise noise noise noise counter cleared noise comple- ment comple- ment noise pulse lost pulse lost figure 27.15 noise detection window setting and noise counting timing section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 778 of 1174 rej09b0329-0200 27.2.10 data slicer detectio n window register (ddetwr) 0 0 0 0 0 0 0 0 7 w crwds0 0 w srwde1 6 w srwde0 5 w srwds1 4 w srwds0 3 w crwde1 2 w crwde0 1 w crwds1 bit : initial value : r/w : the ddetwr is an 8-bit write-only register for specifying the timing of the clock run-in detection window signal and start bit detection window signal supplied to the data slicer. figure 27.16 shows the timing of the signals. the ddetwr is initialized to h'00 by a reset, in module stop mode, in sleep mode, in standby mode, in watch mode, in subactive mode or in subsleep mode. these detection window signals can be monitored through terminals. for details, refer to section 29.7.3, digital output specification register (dout). c.video 32 fh = 2 s 32 fh = 2 s 10.5 s 0.5 s 0.5 s 0.5 s 0.5 s 23.5 s 23.5 s 29.5 s clock run-in detection window si g nal start bit detection window si g nal figure 27.16 timing for generating clock run-in detection window signal and start bit detection window signal section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 779 of 1174 rej09b0329-0200 bits 7 and 6 ? start bit detection window signal falling timing setting (srwde1, srwde0): specify the falling timing (end timing) of the start bit detection window signal. bit 7 bit 6 srwde1 srwde0 description 0 0 the detection ends about 29.5 s after the slicer start point (initial value) 1 the detection ends about 29.0 s after the slicer start point 1 0 the detection ends about 30.0 s after the slicer start point 1 this setting must not be used bits 5 and 4 ? start bit detection window signal rising timing setting (srwds1, srwds0): specify the rising timing (start timing) of the start bit detection window signal. bit 5 bit 4 srwds1 srwds0 description 0 0 the detection starts about 23.5 s after the slicer start point (initial value) 1 the detection starts about 23.0 s after the slicer start point 1 0 the detection starts about 24.0 s after the slicer start point 1 this setting must not be used bits 3 and 2 ? clock run-in detection window signal falling timing setting (crwde1, crwde0): specify the falling timing (end timing) of the clock run-in detection window signal. bit 3 bit 2 crwde1 crwde0 description 0 0 the detection ends about 23.5 s after the slicer start point (initial value) 1 the detection ends about 23.0 s after the slicer start point 1 0 the detection ends about 24.0 s after the slicer start point 1 this setting must not be used section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 780 of 1174 rej09b0329-0200 bits 1 and 0 ? clock run-in detection window signal rising timing setting (crwds1, crwds0): specify the rising timing (start timing) of the clock run-in detection window signal. bit 1 bit 0 crwds1 crwds0 description 0 0 the detection starts about 10.5 s after the slicer start point (initial value) 1 the detection starts about 10.0 s after the slicer start point 1 0 the detection starts about 11.0 s after the slicer start point 1 this setting must not be used 27.2.11 internal sync frequency register (infrqr) 0 0 0 0 0 1 0 0 7 ? ? 0 w vfs2 6 w vfs1 5 w hfs 4 ? ? 3 ? ? 2 ? ? 1 ? ? bit : initial value : r/w : the infrqr is an 8-bit write-only register for modifying the internally generated hsync and vsync frequency to reduce the color-bleeding or jitter of osd in pal, mpal, or npal mode or when the non-interlaced text display mode is selected in the osd. the infrqr is initialized to h'10 by a reset, in module stop mode, in sleep mode, in standby mode, in watch mode, in subactive mode or in subsleep mode. bits 7 and 6 ? vsync frequency selection (vfs2, vfs1): select the vsync frequency. here, fh indicates the hsync frequency in each tv format. bit 7 bit 6 description vfs2 vfs1 pal mpal npal 0 0 fh/313 (initial value) fh/263 (initial value) fh/313 (initial value) 1 fh/314 fh/266 fh/314 1 0 fh/310 fh/262 fh/310 1 fh/312 fh/264 fh/312 section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 781 of 1174 rej09b0329-0200 bit 5 ? hsync frequency selection (hfs): selects the hsync frequency. here, fsc indicates the color subcarrier signal frequency in each tv form at. note that this setti ng is ignored when the hcksel bit (bit 3) of the sepcr is set to 1 to select the afc clock as the internal csync generator clock source and when the fscin bit (bit 12) of the dform in the osd is set to 1 to select the 2fsc clock. bit 5 description hfs pal mpal npal 0 fsc/283.75 (initial value) fsc/227.25 (initial value) fsc/229.25 (initial value) 1 fsc/283.5 fsc/227.5 fsc/229.5 bit 4 ? blank bit: cannot be read or modified. bits 3 to 0 ? reserved: cannot be modified and are always read as 0. when 1 is written to these bits, correct operation is not guaranteed. 27.3 operation 27.3.1 selecting source signal s for sync separation the source for sync separation can be selected from three signals (five methods): 1. composite video signal input from the cvin2 terminal (two methods) 2. csync signal input from the csync/hsync terminal (two methods) 3. vsync and hsync signals that are input from the vlpf/vsync and csync/hsync terminals, respectively (one method) for the composite video signal and the csync signal, two methods are available for processing the vsync component. (1) inputting the composite video signal as the source when the composite video signal is selected as the source, the vsync component can be processed in two methods: using the vsync schmitt circuit or using the csync schmitt circuit. (a) using the vsync schmitt circuit the composite video signal input to the cvin2 te rminal is selected as the source, and the csync separation comparator separates the composite sync signal from the source signal. of the composite sync signal, the hsync component is input to the digital h separation counter, and the vsync component is output from the csync/hsync terminal, goes through the external lpf circuit, then is input again through the vsync/vlpf terminal and the section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 782 of 1174 rej09b0329-0200 vsync schmitt circuit to the digital v separation counter. the initial value of the sepimr specifies this method. figure 27.17 shows this method. cvin2 csync a 1 1 0 0 b a b hsync vsync vlpf vsync/vlpf csync/hsync hsync vsync external sw3 internal sw5 internal sw6 external sw2 external sw1 reference volta g e switch re g ister control i/o switch i/o switch polarity switch polarity switch di g ital h separation counter dlpfon di g ital v separation counter csync polarity schmitt circuit vsync polarity schmitt circuit external circuit inside lsi csync separation comparator external sw4 cvin2 ccmpsl ccmpv0, 1 synct vsel sepv seph ? + sync tip clamp figure 27.17 sync source selection when using the cvin2 signal and the vsync schmitt circuit source signal vsync detection external sw1 external sw2 external sw3 external sw4 ccmpsl (internal sw5) vsel (internal sw6) csync/ hsync terminal i/o cvin2 input vsync schmitt off on a a 0 0 output section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 783 of 1174 rej09b0329-0200 (b) using the csync schmitt circuit the hsync component is processed in the same way as described in (a), but the vsync component is processed differently; the csync/hsync terminal is left open and the separated vsync component is input through the csync schm itt circuit to the digital v separation counter. figure 27.18 shows this method. cvin2 csync a 1 1 0 0 b a b hsync vsync vlpf vsync/vlpf csync/hsync hsync vsync external sw3 internal sw5 internal sw6 external sw2 external sw1 reference volta g e switch re g ister control i/o switch i/o switch polarity switch polarity switch di g ital h separation counter di g ital v separation counter dlpfon csync polarity schmitt circuit vsync polarity schmitt circuit external circuit inside lsi csync separation comparator external sw4 cvin2 ? + ccmpsl ccmpv0, 1 synct vsel sepv seph sync tip clamp figure 27.18 sync source selection when using the cvin2 signal and the csync schmitt circuit source signal vsync detection external sw1 external sw2 external sw3 external sw4 ccmpsl (internal sw5) vsel (internal sw6) csync/ hsync terminal i/o cvin2 input csync schmitt off off open fixed to 0 or 1 0 1 output section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 784 of 1174 rej09b0329-0200 (2) inputting the csync signal as the source when the csync signal is selected as the source, the vsync component can be processed in two methods: using the vsync schmitt circuit or using the csync schmitt circuit. (a) using the vsync schmitt circuit the csync signal having the polarity selected by the synct bit (bit 4) of the sepimr is input to the csync/hsync terminal. the hsync component is input through the csync schmitt circuit to the digital h separation counter; the vsync component goes through the external lpf circuit, then is input through the vsync/vlpf terminal and the vsync schmitt circuit to the digital v separation counter. figure 27.19 shows this method. cvin2 csync a 1 1 0 0 b a b hsync vsync vlpf vsync/vlpf csync/hsync hsync vsync external sw3 internal sw5 external sw2 external sw1 reference volta g e switch re g ister control i/o switch i/o switch polarity switch polarity switch di g ital h separation counter di g ital v separation counter dlpfon csync polarity schmitt circuit vsync polarity schmitt circuit external circuit inside lsi csync separation comparator external sw4 cvin2 ? + ccmpsl ccmpv0, 1 synct vsel sepv seph sync tip clamp internal sw6 figure 27.19 sync source selection when using the cs ync signal and the vsync schmitt circuit source signal vsync detection external sw1 external sw2 external sw3 external sw4 ccmpsl (internal sw5) vsel (internal sw6) csync/ hsync terminal i/o csync input vsync schmitt on on a a 1 0 input section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 785 of 1174 rej09b0329-0200 (b) using the csync schmitt circuit the hsync component is processed in the same way as described in (a), but the vsync component is processed differently; the vsync component is input through the csync schmitt circuit to the digital v separation counter. figure 27.20 shows this method. cvin2 csync a 1 1 0 0 b a b hsync vsync vlpf vsync/vlpf csync/hsync hsync vsync external sw3 internal sw5 internal sw6 external sw2 external sw1 reference volta g e switch re g ister control i/o switch i/o switch polarity switch polarity switch di g ital h separation counter di g ital v separation counter dlpfon csync polarity schmitt circuit vsync polarity schmitt circuit external circuit inside lsi csync separation comparator external sw4 cvin2 ? + ccmpsl ccmpv0, 1 synct vsel sepv seph sync tip clamp figure 27.20 sync source selection when using the cs ync signal and the csync schmitt circuit source signal vsync detection external sw1 external sw2 external sw3 external sw4 ccmpsl (internal sw5) vsel (internal sw6) csync/ hsync terminal i/o csync input csync schmitt on off a fixed to 0 or 1 1 1 input section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 786 of 1174 rej09b0329-0200 (3) inputting the hsync and vsync signals separately as sources the hsync signal having the polarity selected by the synct bit (bit 4) of the sepimr is input to the csync/hsync terminal, and is inpu t through the csync schmitt circuit to the digital h separation counter; the vsync signal having the polarity selected by the synct bit is input to the vsync/vlpf terminal, and is sent through the vsync schmitt circuit to the digital v separation counter. figure 27.21 shows this method. cvin2 csync a 1 1 0 0 b a b hsync vsync vlpf vsync/vlpf csync/hsync hsync vsync external sw3 internal sw5 internal sw6 external sw2 external sw1 reference volta g e switch re g ister control i/o switch i/o switch polarity switch polarity switch di g ital h separation counter di g ital v separation counter dlpfon csync polarity schmitt circuit vsync polarity schmitt circuit external circuit inside lsi csync separation comparator external sw4 cvin2 ? + ccmpsl ccmpv0, 1 synct vsel sepv seph sync tip clamp figure 27.21 sync source selection when us ing the hsync and vsync signals separately source signal vsync detection external sw1 external sw2 external sw3 external sw4 ccmpsl (internal sw5) vsel (internal sw6) csync/ hsync termina l i/o hsync and vsync input vsync schmitt off off b b 1 0 input section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 787 of 1174 rej09b0329-0200 27.3.2 vsync separation the hsync separator separates the vsync signal from the csync signal by using the digital v separation counter, which is an 8-bit up-/down-counter, and the vvthr register, which holds the threshold value. the digital v separation counter increments the count when the csync signal is high, and decrements the count when the csync is low. when the count reaches the vvthr value while the count is incremented, the sepv signal is set to 1 and the counter stops until the csync signal goes low. when the csync signal goes low, th e counter starts to decr ement the count. when the count reaches h'00, the sepv signal is reset to 0 and the counter stops until the csync signal goes high. set the vvthr value so that the sepv signal goes high 1/2 or more after the vsync start position to correctly separate the vsync signal against the signal disturbance in a weak field or the motor skew during video tape playback. refer to figure 27.10. the obtained sepv signal is sent to the v complement and mask counter. the v complement and mask counter is reset to 0 when the sepv signal is input, and increments the count at twice the frequency (2 fh) of the horizontal sync signal for the vsync signal (sepv signal) cycle period. this counter masks the reset signal (sepv) for about 85% (ntsc) or 72% (pal) of the period from a reset to the next reset; even if a sepv signal generated by noise is input to the counter during this period, the counter is not reset. if no sepv signal is input after the mask period ends, the mask is left cleared; the next sepv signal input resets the counter, and the counter is synchronized with the sepv signal. when the counter is reset by the sepv signal, the external vsync detection signal (afcv) is generated and the external vsync interrupt flag is set to 1. the vsync separation function includes the dig ital lpf function and the vsync complement function, which reduce the chance of the vsync detection being delayed or missed due to the vsync disturbance in a weak field. (1) digital lpf function this function logically ors the csync (vsync) signal and the seph signal separated by the digital h counter to mask the noise component due to loss of a vsync pulse. the digital v separation counter increment the count when the resultant signal is input. loss of a vsync pulse in a weak field causes sepv signal detection to be delayed or missed, which will result in incorrect detection of fields or lines. to enable this function, set the dlpfon bit (bit 2) of the sepimr to 1. for the timing, refer to figure 27.11. (2) vsync complement function this function makes the v complement and mask counter increment the count at a clock having twice the frequency (2 fh) of the horizontal sync signal (afch), and generates the afcv signal (vsync signal) from the count if a vsync pulse is lost. the count value is decoded in different ways depending on the tv format. the source of the clock for the v complement and mask counter can be switched between the afc or the h complement and mask counter. this function can reduce the chance of the sepv signal section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 788 of 1174 rej09b0329-0200 detection being delayed and missed in a weak field. to enable this function, set the vcmpon bit (bit 4) of the sepcr to 1. for the timing, refer to figure 27.12. 27.3.3 hsync separation the hsync separator separates the hsync signal from the csync signal by using the digital h separation counter, which is a 5-bit up-/down-counter, and the hvthr register, which holds the threshold value. the digital h separation counter increments the count when the csync signal is high, and decrements the count when the csync is low. when the count reaches the hvthr value while the count is incremented, the seph signal is set to 1 and the counter stops until the csync signal goes low. when the csync signal goes low, th e counter starts to decr ement the count. when the count reaches h'00, the seph signal is reset to 0 and the counter stops until the csync signal goes high. set the hvthr value so that 2.35- s equalizing pulses* can be detected; that is, that the hsync pulses can be continuously detected. refer to figure 27.3. the obtained seph signal is sent to the h complement and mask counter. the h complement and mask counter is reset to 0 when the seph signal is input, and increments the count at a frequency of /2 for the seph signal cycle period to generate the osch signal, hhk signal, and noise detection window signal. the hhk period is specified by the hm6 to hm0 bits of the hcmmr. even if a seph signal is input to the counter du ring this hhk period, the seph signal is masked and the counter is not reset; noise pulses and equalizing pulses during the v blanking period are eliminated by this function. the h complement and mask counter has the complement function. if no seph signal is input during the period specified by the hc8 to hc0 bits of the hcmmr, the complement function generates a complementary pulse and inserts the pulse into the osch signal. in this case, the counter is reset by the complementary pulse, but no hhk signal is generated; the next seph signal input resets the counter, and the counter is synchronized with the seph signal. for the timing, refer to figure 27.14. note: * in a weak field, equalizing pulses are not detected in some cases because the pulses have a short duration of 2.35 s. if equalizing pulses, which are input at the same timing as the hsync pulses, are not detect ed, a phase-difference error between the hsync and vsync occurs at a rising edge of the vsync signal. such an error will cause incorrect field detection in the sync separator and incorrect line detection by the osd or data slicer. in such a weak field, adju st the hvthr value so that equalizing pulses are not detected. note that while equalizi ng pulses are not detected, complementary pulses are inserted repeatedly and an hsync -vsync phase-difference error occurs at a rising edge of the vsync signal, even in a field that is not weak. to avoid this, set the hhkon bit (bit 2) or hhkon2 bit (bit 1) of the sepcr to 1 to operate the hhk section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 789 of 1174 rej09b0329-0200 function when complementary pulses are ge nerated three successive times. for the timing, refer to figures 27.6, 27.7, 27.8, and 27.9. 27.3.4 field detection the sync separator detects whether the current field is an even fiel d or an odd field from the 1/2h phase difference between the hsync and vsync by using the afcv signal generated by the v complement and mask counter and the field det ection window signal generated by the afc. the timing of the field detection wi ndow signal can be adjusted by th e fwidr setting so that it is suitable for comparison with the afcv signal. when a rising edge of the afcv signal is detected while the field detection window signal is high, the current field is determined as an odd field; when a rising edge of the afcv signal is detected while the field detection window signal is low, the current field is determined as an even field. the field detec tion status can be monitored from the cpu by reading the fld bit (bit 0) of the sepacr. this function will not operate when the internally generated hsync signal is selected as the reference hsync signal for the afc, because the afc is not synchronized with the external hsync signal in this case. for the timing, refer to figure 27.13. 27.3.5 noise detection the noise detection function is necessary for tune d status detection. the sync separator detects noise by using the csync signal and the noise detection window signal generated by the h complement and mask counter. the noise detection window signal is set to 1 at a falling edge of the osch signal generated by the h complement and mask counter, and reset to 0 at the hhk clearing timing specified by bits hm6 to hm0 of the hcmmr. noise is detected by comparing the noise counter value with the noise detection level register value. the noise counter counts the number of hsync cycles in which an hsync signal is input (noise h) while the noise detection window signal is high and the number of hsync cycles in which no hsync signal is input while the noise detection window signal is low. when the counted value reaches the noise detection level, the noise detection interrupt request flag is set. the noise counter can be read from the cpu, and the noise detection status can be monitored. the noise detection counter is reset every other vsync signal input. accordingly, the noise input during one field can be detected. when the internally generated hsync signal is selected as the refere nce hsync signal for the afc and the text display mode is used in the osd, the noise counter re set operation can be enabled by setting the vcksl bit (bit 5) of the sepcr to 1. for the timing, refer to figure 27.15. section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 790 of 1174 rej09b0329-0200 27.3.6 automatic frequency controller (afc) the afc averages the hsync signal fluctuation of the video signal. figure 27.22 shows the afc configuration. the afc generates a reference cl ock having 576 or 448 times the frequency (576 fh or 448 fh) of the hsync signal. from this clock, several clocks are generated, such as the horizontal sync signal (afch signal), clock run-in detection window signal, start bit detection window signal, v complement and mask counter clock when the v complement function is selected, and the field detection window signal. the reference clock is also used as the dot clock for the osd; modifying the reference clock freque ncy can change the dot width of the character display. to change the frequency, connect a circuit having a value suitable for the desired frequency to the afcosc and afcpc terminals, and select the division ratio for the frequency- dividing counter through th e setting of the frqsel bit in sepi mr. note that the data slicer operates even when 448 fh is selected as the reference clock. afclpf r c vco afcpc afcosc hhk hsel hcksel maskin g h fsc afch afc error output circuit (comparator) internal csync g enerator h complement and mask counter external hsync error si g nal switchin g switchin g reference clock frqsel maskin g and complementin g h reference hsync si g nal internally g enerated hsync external hsync si g nals such as dot clock low pass filter frequency- dividin g counter (divided by 576 or 448) r figure 27.22 afc configuration section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 791 of 1174 rej09b0329-0200 (1) afc oscillator the afcosc terminal, which is the oscillation signal terminal of the voltage controlled oscillator (vco), oscillates at 576 times the frequency (576 fh) of the hsync signal when the hsync signal is input at a certain phase and frequency. the difference in phase or frequency is detected between the reference hsync signal and the hsync signal (afch signal) obtained by dividing the 576 fh signal, the error signal is converted to a voltage by a low pass filter through the afc error output circuit, and the voltage is used to control the vco. the vco control voltage (the afclpf terminal voltage) is within a range from about 1.0 v to 4.0 v. the oscillating capacitance should be se t so that the afcosc oscillating frequency becomes 576 fh at the center (about 2.5 v) of the control voltage range. to set the oscillating frequency to 448 fh, change the values of the external circuits connected to the afcpc and afcosc terminals and modify the frqsel bit in sepimr. (2) afclpf the afc error output circuit detects the difference in phase or frequency between the reference hsync signal and the hsync signa l (afch signal) obtained by dividing the 576 fh or 448 fh signal, and generates a pulse corresponding to the error. connect a low pass filter (lpf) to the afclpf terminal to average these error pulses. if the cut-off frequency is too low, the oscillation stabilizing time (the pull-in time) needed to reach 576 fh or 448 fh becomes long when a large error is detected or after the power is turned on; a high cut-off frequency will cause jitter or an unstable display. connect a suitable lpf by referring to the external circuit examples shown in figures 27.23 and 27.24. when the hsync signal includes a large disturbance, for example during special playback operation, the afc ci rcuit may operate incorrectly. (3) reference hsync signal for afc the afc reference clock is also used as the dot clock for the osd. a ccordingly, select the reference hsync signal depending on whether the osd operates in the super-imposed mode or text display mode. refer to table 27.4, reference hsync signal for afc. section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 792 of 1174 rej09b0329-0200 table 27.4 reference hs ync signal for afc afc reference hsync signal data slicer operation osd operation field detection v complement and mask counter hcksel hsel vcksl dotcksl external hsync signal operates/ stops super- imposed mode operates twice the frequency of the afch 0 0 0 0 internally generated hsync signal stops text display mode stops twice the frequency of the osch 0 1 1 0 external hsync signal operates text display mode operates twice the frequency of the afch 0 0 0 1 external hsync signal * operates text display mode operates twice the frequency of the afch 1 0 0 0 note: * in this case, the hsync and vsync signals must be dedicated separation inputs, with both signals having equal cycles and pulse widths. the frqsel bit in the sepimr register must be cleared to 0. section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 793 of 1174 rej09b0329-0200 (4) external circuit examples figures 27.23 and 27.24 show external circuit examples of the afc. 12 pf afcosc afcpc afclpf 8.2 h 0.01 f 1/2 ovcc vco 1000 pf 4.7 f + + 470 10 k note: reference values are shown. phase error signal reset, active, or sleep figure 27.23 circuit example for a 576 fh reference clock section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 794 of 1174 rej09b0329-0200 15 pf afcosc afcpc afclpf 15 h 0.01 f 1/2 ovcc vco 1000 pf 4.7 f + + 470 10 k note: reference values are shown. phase error signal reset, active, or sleep figure 27.24 circuit example for a 448 fh reference clock section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 795 of 1174 rej09b0329-0200 27.3.7 module stop control register (mstpcr) 7 1 r/w 6 1 r/w 54 1 r/w 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w bit : initial value : mstp15 mstp14 mstp13 mstp12 mstp11 mstp10 mstp9 mstp8 mstp7 mstp6 mstp5 mstp4 mstp3 mstp2 mstp1 mstp0 r/w : mstpcrh mstpcrl the mstpcr is a 16-bit read/write register for controlling the module stop mode. writing 0 to the mstp9 bit starts the sync separator; setting the mstp9 bit to 1 stops the sync separator at the end of a bus cycle and the module stop mode is entered. the afc oscillator operates in reset, active, and sleep modes. accordingly, after the reset state is cleared, the afc oscillator operates but the afc error output circuit (comparator) does not operate. clear the module stop mode of the sync separator and set the sync separator registers to the desired values. the afc erro r output circuit (comparator) w ill stop in standby, sleep, watch, subactive, subsleep, and module stop modes. when these modes are cleared, wait for the oscillation to stabilize, that is, for the afc frequency to reach 576 fh or 448 fh. the registers cannot be read or written to in modul e stop mode. for details, refer to section 4.5, module stop mode. bit 9 ? module stop (mstp9): specifies the module stop mode of the sync separator. bit 9 mstp9 description 0 clears the module stop mode of the sync separator 1 specifies the module stop mode of the sync separator (initial value) section 27 sync separator for osd and data slicer rev.2.00 jan. 15, 2007 page 796 of 1174 rej09b0329-0200 section 28 data slicer rev.2.00 jan. 15, 2007 page 797 of 1174 rej09b0329-0200 section 28 data slicer 28.1 overview the data slicer extracts signals for closed caption signal in the u.s. this function can be used to extract caption data superimposed on the vertical blanking interval of tv video signals. a high-performance internal sync separator enables reliable caption data extraction. the data slicer operates even when 448 times the horizontal sync frequency is selected for the afc reference clock frequency. for details, re fer to section 27.3.6, automatic frequency controller (afc). 28.1.1 features ? slice lines: 4 lines* (16-bit mode) / 1 line (32-bit mode) ? slice levels: 7 levels ? sampling clock: generated by afc ? slice interrupt: a slice completion interrupt is ge nerated at the end of all slices in a field ? error detection: clock run-in, start bit, and data end note: * the h8s/2197s and h8s/2196s: 2 lines. section 28 data slicer rev.2.00 jan. 15, 2007 page 798 of 1174 rej09b0329-0200 28.1.2 block diagram figure 28.1 shows the block diagram of the data slicer. sync separator sync si g nal g eneration field determination circuit slice volta g e g enerator clock run-in detector start bit detector data samplin g clock g enerator shift re g ister slice data re g ister data end fla g slice completion interrupt start bit detection fla g clock run-in detection fla g slice line specification circuit line countin g field line counter reference clock cvin2 + ? h complement and mask afc v h h osd v dot clock sync tip clamp figure 28.1 data slicer block diagram section 28 data slicer rev.2.00 jan. 15, 2007 page 799 of 1174 rej09b0329-0200 28.1.3 pin configuration table 28.1 shows the pin configuration for the data slicer. table 28.1 data sli cer pin configuration block name abbrev. i/o function csync/hsync input/output composite sync signal input/output or horizontal sync signal input sync signal input/output vlpf/vsync input pin for connecting external lpf for vertical sync signal or input pin for vertical sync signal afcosc input/output afc oscillation signal afc oscillation afcpc input/output afc by-pass capacitor connecting pin lpf for afc afclpf input/output external lpf connecting pin for afc 4fsc/2fscin input 4fsc or 2fsc input sync separator fsc oscillation 4fsc/2fscout output 4fsc or 2fsc output data slicer composite video signal cvin2 input composite video signal input (2 vpp, with a sync tip clamp circuit) section 28 data slicer rev.2.00 jan. 15, 2007 page 800 of 1174 rej09b0329-0200 28.1.4 register configuration table 28.2 shows the data slicer registers. table 28.2 register configuration name abbrev. r/w size initial value address * 3 slice even-field mode register sevfd r/(w) * 1 word/byte h'2000 h'd220 slice odd-field mode register sodfd r/(w) * 1 word/byte h'2000 h'd222 slice line setting register 1 sline1 r/w word/byte h'20 h'd224 slice line setting register 2 sline2 r/w word/byte h'20 h'd225 slice line setting register 3 * 4 sline3 r/w word/byte h'20 h'd226 slice line setting register 4 * 4 sline4 r/w word/byte h'20 h'd227 slice detection register 1 sdtct1 r/(w) * 2 word/byte h'10 h'd228 slice detection register 2 sdtct2 r/(w) * 2 word/byte h'10 h'd229 slice detection register 3 * 4 sdtct3 r/(w) * 2 word/byte h'10 h'd22a slice detection register 4 * 4 sdtct4 r/(w) * 2 word/byte h'10 h'd22b slice data register 1 sdata1 r word/byte undefined h'd22c slice data register 2 sdata2 r word/byte undefined h'd22e slice data register 3 * 4 sdata3 r word/byte undefined h'd230 slice data register 4 * 4 sdata4 r word/byte undefined h'd232 notes: 1. only 0 can be written to clear the flag (bit 14). 2. bits 7 to 0 are cleared when 1 is written to bit 7 of the corresponding slice line setting register. 3. lower 16 bits of the address. 4. not available for the h8s/2197s and h8s/2196s. 28.1.5 data slicer use conditions table 28.3 indicates the conditions of use of the data slicer. table 28.3 data slicer use conditions sync signal input for sync separation data slicer sync separation signal input from cvin2 usable sync separation signal input from csync usable hsync or vsync separation signals usable section 28 data slicer rev.2.00 jan. 15, 2007 page 801 of 1174 rej09b0329-0200 28.2 register description 28.2.1 slice even- (odd-) field mode register (sevfd, sodfd) the sevfd and sodfd control the start bit detection starting position, slice voltage level, data sampling delay time, and interrupts. the sevfd holds settings for even fields, and the sodfd holds settings for odd fields. when reset, when the module is stopped, in sleep mode, in standby mode, in watch mode, in subactive mode, or in subsleep mode, the sevfd and sodfd are both initialized to h'2000. the sevfd and sodfd are 16-bit read/write regi sters; however, rewriting of sevfd or sodfd should be performed after output of an even- (odd-) field slice completion interrupt. during data slice operations, if sevfd or sodfd is rewritten, a malfunction will result; do not perform rewriting during data slice operation. (1) slice even-fiel d mode register 8 0 9 stbe1 r/w 0 10 stbe2 r/w 0 11 stbe3 r/w 0 12 stbe4 r/w 0 1 13 ? ? 0 15 14 evnif r/(w) * r/w stbe0 0 r/w evnie bit: initial value: r/w: 0 0 1 dlye1 r/w 0 2 dlye2 r/w 0 3 dlye3 r/w 0 4 dlye4 r/w 0 0 5 slvle0 r/w 0 76 slvle1 r/w r/w dlye0 0 r/w slvle2 bit: initial value: r/w: (2) slice odd-field mode register 8 0 9 stbo1 r/w 0 10 stbo2 r/w 0 11 stbo3 r/w 0 12 stbo4 r/w 0 1 13 ? ? 0 15 14 oddif r/(w) * r/w stbo0 0 r/w oddie bit: initial value: r/w: 0 0 1 dlyo1 r/w 0 2 dlyo2 r/w 0 3 dlyo3 r/w 0 4 dlyo4 r/w 0 0 5 slvlo0 r/w 0 76 slvlo1 r/w r/w dlyo0 0 r/w slvlo2 bit: initial value: r/w: note: * only 0 can be written to clear the fla g . section 28 data slicer rev.2.00 jan. 15, 2007 page 802 of 1174 rej09b0329-0200 bit 15 ? even- (odd-) field slice completion interrupt enable flag (evnie, oddie): enables or disables the generation of even- (odd-) field slice completion interrupts. bit 15 evnie oddie description 0 disables even- (odd-) field slice completion interrupt (initial value) 1 enables even- (odd-) field slice completion interrupt bit 14 ? even- (odd-) field slice completion interrupt flag (evnif, oddif): set when data slicing for all specified lines of even (odd) field is completed. bit 14 evnif oddif description 0 [clearing condition] when 0 is written after reading 1 (initial value) 1 [setting condition] when data slicing is completed for all specified lines of even (odd) field bit 13 ? reserved: cannot be modified and is always read as 1. bits 12 to 8 ? start bit detection starting position bits (stbe4 to stbe0) (stbo4 to stbo0): set the starting position for start bit detection in even (odd) fields. the base point for the data slicer is the falling edge of the horizontal sync signal (slicer base point h) synchronized within the lsi; the starting position for start bit detection can be set using stbe4 to stbe 0 (stbo4 to stbo0) in 288* fh (where fh is the horizontal sync signal frequency) clock units from approximately 23.5 s after the data slicer base point. the start bit detection end position is at approximately 29.5 s after the data slicer base point. in start bit detection, the presence of the rising ed ge of start bits in the interval between these starting and ending positions is detected. further, the start bit detection window signal, which becomes the base point for the start bit detection starting position, can be adjusted by means of the data slicer detection window register of the sync separator. for details, refer to section 27.2.10, data slicer detection window register (ddetwr). figure 28.2 shows the data slicer base point and start bit detection starting position. section 28 data slicer rev.2.00 jan. 15, 2007 page 803 of 1174 rej09b0329-0200 note: 288 when bit 0 (frqsel) of sepimr in the sync separator is 0, and 224 when frqsel is 1. clock run-in data slicer base point clock run-in detection window si g nal start bit detection window si g nal note: * 288 when bit 0 (frqsel) of sepimr in the sync separator is 0, and 224 when frqsel is 1. data slicer base point base point for start bit detection startin g position approx. 23.5 s start bit detectable period ts te = approx. 29.5 s 1 288 * fh ts = 23.5 s + s (set by stb4 to stb0) c.video s1 s2 s3 start bit set by stb figure 28.2 data slicer base point and start bit detection starting position section 28 data slicer rev.2.00 jan. 15, 2007 page 804 of 1174 rej09b0329-0200 bits 7 to 5 ? slice level setting bits (slvle2 to slvle0) (slvlo2 to slvlo0): specify the even (odd) field data slice level. the data slice level is common to clock line detection, start bit detection, and 16-bit data slicing. bit 7 bit 6 bit 5 slvle2 slvlo2 slvle1 slvlo1 slvle0 slvlo0 description 0 slice level is 0 ire (initial value) 0 1 slice level is 5 ire 0 slice level is 15 ire 0 1 1 slice level is 20 ire 0 slice level is 25 ire 0 1 slice level is 35 ire 0 slice level is 40 ire 1 1 1 must not be specified note: all slice levels are with reference to the pedestal level (5 ire). slice level values are provided for reference. bits 4 to 0 ? data sampling delay time setting bits (dlye4 to dlye0) (dlyo4 to dlyo0): set the even (odd) field data sampling clock delay time. figure 28.3 explains the data sampling clock. the data sampling clock is a clock with period 32 fh * 2 , used for slicing 16-bit closed caption data. the data sampling clock is generated after the rising edge of the start bit is detected and the time set by the dly bit is passed. the delay time setting can be adjusted in units of 576 * 1 fh * 2 , so that sampling is possible at a phase optimal for the slice data. the data sampling delay time (td) should be set based on the calculation indicated below. eighteen pulses of data sampling clock are output in total for start bit detection, s lice data, and end data detection. in order to make the sampling phase even more op timal, the slice data (analog comparator output) and sampling clock can be output from the port. for details of monitor output, refer to section 28.2.6, monitor output setting register (dout). notes: 1. 576 when bit 0 (frqsel) of sepimr in the sync separator is 0, and 448 when frqsel is 1. 2. fh: horizontal sync signal frequency section 28 data slicer rev.2.00 jan. 15, 2007 page 805 of 1174 rej09b0329-0200 start bit slice data 1st character s1 s2 32 fh s3 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 lsb 2nd character detected start bit data samplin g clock note: * 576 when bit0 (frqsel) of sepimr in the sync separator is 0, and 448 when frqsel is 1. 32 fh td: data samplin g delay time specified by dlye4 to dlye0 (dlyo4 to dlyo0) td = ns [settin g in bits dly4 to dly0 + 2] msb 1 576 * fh figure 28.3 data sampling clock description 28.2.2 slice line setting registers 1 to 4 (sline1 to sline4) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 1 ? 5 6 0 7 slinen4 * slinen3 * slinen2 * slinen1 * slinen0 * 0 r/w senbln * r/w r/w r/w sfldn * ? bit: initial value: r/w: the slice line setting registers 1 to 4 (sline1 to sl ine4) specify slice fields and lines. up to four slice lines can be specified; these are specified in the s lice line setting registers 1 to 4 respectively. these are 8-bit read/write registers. rewrites of sline should be performed after an even (odd) field slice completion interrupt is output, or after module stop mode has been set, registers have been initialized, and module stop mode has been cleared again. if sline is rewritten during a data slice operation, a malfunction will result; do not perform rewriting during data slice operation. when reset, when the module is stopped, in sleep mode, in standby mode, in watch mode, in subactive mode, or in subsleep mode, the registers are initialized to h'20. note: * n = 1 and 2 in the h8s/2197s and h8s/2196s. section 28 data slicer rev.2.00 jan. 15, 2007 page 806 of 1174 rej09b0329-0200 bit 7 ? slice enable bit (senbln n = 1 to 4): enables or disables data slice operations for the line specified by sfldn and slinen4 to slinen1. when data slicing for a given line is completed, th is bit is reset to 0, and slicing is not again performed until it is set to 1. this bit is set at the rising edge of the vsync signal; hence data slicing settings become valid from the rising edge of the next vsync signal after this bit has been set. when 1 is written to this bit, the correspo nding slice detection register is cleared, and so caution should be exercised. bit 7 senbln description 0 when read: disables data slice operation for the specified lines [clearing condition] when the data slice operation for the line has been completed 1 enables data slice operation for the specified lines bit 6 ? field setting bit (sfldn n = 1 to 4): specifies the field of the slice line. for information on field discrimination, refer to section 27.2.6, field detection window register (fwidr). bit 6 sfldn description 0 even field (initial value) 1 odd field bit 5 ? reserved: cannot be modified and is always read as 1. bits 4 to 0 ? slice line setting bits (sline4 to sline0): specify the data sli ce line. slice lines up to h'1f (31) can be specified. figure 28.4 explains the line count. section 28 data slicer rev.2.00 jan. 15, 2007 page 807 of 1174 rej09b0329-0200 9-line vertical sync pulse period pre-equalizin g period sync separation base point 01 12345678910 192021 h'11 23 456 15161718 line count clear post-equalizin g period vertical synchro- nization period line count specified by slinen4 to slinen0 (n = 1 to 4) figure 28.4 line count 28.2.3 slice detection registers 1 to 4 (sdtct1 to sdtct4) 0 0 1 0 r 2 0 r 3 0 4 1 ? 0 r 5 6 0 7 ? cricn3 * cricn2 * cricn1 * cricn0 * 0 r crdfn * r r r sbdfn * endfn * bit: initial value: r/w: the slice detection registers 1 to 4 (sdtct1 to sdtct4) store information on data slice results. data slice result information includes the clock run-in detection flag, start bit detection flag, data end detection flag, and run-in pulse count for the clock run-in period. this information is useful for optimal positioning of the data slicer slice level, start bit detection timing, and sampling clock generation timing. there are four slice detection registers; data s lice information results are stored in them on completion of data slicing for each line specified by the slice line setting registers 1 to 4. data is stored not in slicing order, but in the corresponding registers. for information on the slice line sequence, refer to section 28.3.2, slice sequence. section 28 data slicer rev.2.00 jan. 15, 2007 page 808 of 1174 rej09b0329-0200 slice line settin g re g ister n line m slice detection re g ister n data slice result information for line m figure 28.5 relationship between slice line setting register and slice detection register sdtct is an 8-bit read-only register. sdtct read operations should be performed after an even (odd) field slice completion interrupt. if sdtct is read during a data slice operation, an indeterminate value may be read; the register should not be read during operation. if 1 is written to bit 7 (senbl) of slice line setting registers 1 to 4, the corresponding slice detection register is automatically cleared, so caution should be exercised. when reset, when the module is stopped, in sleep mode, in standby mode, in watch mode, in subactive mode, or in subsleep mode, the registers are initialized to h'10. note: * n = 1 and 2 in the h8s/2197s and h8s/2196s. bit 7 ? clock run-in detection flag (crdfn n = 1 to 4): set when, during the clock run-in period, the count is concluded in the range 3 to 7 pulses, and clock run-in is detected. when 16 or more pulses are counted, further input pulses are not counted in order to prevent erroneous detection, and an overflow state is maintained. further, the clock run-in detection window signal indicating the clock run-in period can be adjusted using the ddetwr register of the sync separator. for details, refer to section 27.2.10, data slicer detection window register (ddetwr). bit 7 crdfn description 0 clock run-in not detected for line for data slicing (initial value) 1 clock run-in detected for line for data slicing bit 6 ? start bit detection flag (sbdfn, n = 1 to 4): set when the start bit for a line for data slicing is detected. bit 6 sbdfn description 0 start bit not detected for line for data slicing (initial value) 1 start bit detected for line for data slicing section 28 data slicer rev.2.00 jan. 15, 2007 page 809 of 1174 rej09b0329-0200 when the start bit is not detected, the data sampling clock is generated after the time set as the data sampling delay time (dly4 to dly0) has elapsed from the phase of the start bit detection end position. data slicer base point data samplin g clock start bit detection startin g position start bit detection end position c.video delay start bit figure 28.6 data sampling clock when start bit is not detected bit 5 ? data end detection flag (endfn n = 1 to 4): shows whether or not slice data is input at the 18th sampling clock pulse. this flag is set when th e slice data is 0, that is, when data slicing is regarded as having been completed normally. bit 5 endfn description 0 data end not detected for line for data slicing (initial value) 1 data end detected for line for data slicing bit 4 ? reserved: cannot be modified and is always read as 1. bits 3 to 0 ? clock run-in count value (cricn3 to cricn0): count result for run-in pulses during the clock run-in period. when 16 or more pulses are input, further input pulses are not counted in order to prevent erroneous detection, and an overflow state is maintained. further, the clock run-in detection window signal indicating the clock run-in period can be adjusted using the ddetwr register of the sync separator. for details, refer to section 27.2.10, data slicer detection window register (ddetwr). section 28 data slicer rev.2.00 jan. 15, 2007 page 810 of 1174 rej09b0329-0200 28.2.4 slice data registers 1 to 4 (sdata1 to sdata4) 15 * r 14 * r 13 * r 12 * r 11 * r 10 * r 9 * r 8 * r 7 * r 6 * r 5 * r 4 * r 3 * r 2 * r 1 * r 0 * r bit: initial value: r/w: * : unefined the slice data registers 1 to 4 (sdata1 to sdat a4) are registers in whic h the slice results are stored. the data is stored in lsb-first fashion, in order from the lsb side near the start bit. figure 28.7 shows how to store the slice data. 15 b20 14 b21 13 b22 12 b23 11 b24 10 b25 9 b26 8 b27 7 b10 6 b11 5 b12 4 b13 3 b14 2 b15 1 b16 0 b17 b17 s3 s2 s1 b16 b15 b14 b13 b12 b11 b10 b27 b26 b25 b24 b23 b22 b21 b20 lsb msb bit slice data re g ister slice data figure 28.7 relationship between slice data and slice data register there are four slice data registers, in which are st ored slice results when data slicing is completed for each line specified by the slice line setting registers. at this time data is stored in the corresponding registers, rather than in the slicing order. slice line settin g re g ister n line m slice data re g ister n data slice result for line m figure 28.8 relationship between slice li ne setting register and slice data register section 28 data slicer rev.2.00 jan. 15, 2007 page 811 of 1174 rej09b0329-0200 these are 16-bit read-only registers. sdata read operations should be performed after an even (odd) field slice completion interrupt. if an sdata register is read during a data slice operation, an indeterminate value may be read; the register should not be read during operation. when reset, when the module is stopped, in sleep mode, in standby mode, in watch mode, in subactive mode, or in subsleep mode, the sdata register values are indeterminate. 28.2.5 module stop control register (mstpcr) 7 1 r/w mstp 15 mstp 14 mstp 13 mstp 12 mstp 11 mstp 10 mstp 9 mstp 8 mstp 7 mstp 6 mstp 5 mstp 4 mstp 3 mstp 2 mstp 1 mstp 0 6 1 r/w 54 1 r/w mstpcrh mstpcrl 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w bit: initial value: r/w: the mstpcr consists of two 8-bit read/write registers for controlling the module stop mode. writing 0 to the mstp3 bit starts the data slicer; se tting the mstp3 bit to 1 stops the data slicer at the end of a bus cycle and the module stop mode is entered. before writing 0 to this bit, set the mstp9 bit to 0, to operate the sync separator. the registers cannot be read or written to in modul e stop mode. for details, refer to section 4.5, module stop mode. bit 3 ? module stop (mstp3): specifies the module stop mode for the data slicer. bit 3 mstp3 description 0 clears the module stop mode for the data slicer 1 specifies the module stop mode for the data slicer (initial value) section 28 data slicer rev.2.00 jan. 15, 2007 page 812 of 1174 rej09b0329-0200 28.2.6 monitor output setting register (dout) 0 1 1 1 ? 2 0 r/w 3 0 4 1 r/w 0 r/w 5 6 0 7 dobc dsel crsel ? ? 0 ? ? ? r/w r/w rgbc ycoc bit: initial value: r/w: the internal signals used by the data slicer can be monitored through the r, g, b, yco, and ybo pins. for the bits other than bits 2 and 3, refer to section 29.7.3, digital output specification register (dout). bit 3 ? bit to select functions for r, g, b, yco, ybo pins (dsel): selects whether the digital output pins output r, g, b, yco, and ybo signals, or output data slicer internal monitor signals. bit 3 dsel description 0 r, g, b, yco, and ybo signals selected (initial value) 1 data slicer monitor signals selected pin r: signal selected by bit 2 (crsel) pin g: slice data signal analog-compared with cvin2 pin b: sampling clock generated within data slicer pin yco: external hsync signal (afch) synchronized in the lsi pin ybo: external vsync signal (afcv) synchronized in the lsi bit 2 ? monitor signal select bit (crsel): selects whether the clock run-in detection window signal is output, or the start bit detection window signal is output. this bit is valid when dsel is set to 1 to select data slicer internal monitor signal output. bit 2 crsel description 0 clock run-in detection window signal output selected (initial value) 1 start bit detection window signal output selected section 28 data slicer rev.2.00 jan. 15, 2007 page 813 of 1174 rej09b0329-0200 28.3 operation 28.3.1 slice line specification up to four slice lines can be specified using the slice line setting registers 1 to 4. for information on field discrimination, refer to section 27.2.6, field detection window register (fwidr). after completion of data slicing for all lines speci fied by registers, a slice completion interrupt is output; the slice results and slice information should then be read. slice information includes clock run-in detection, start bit detection, and data end detection to determine whether data sampling was performed normally; this information is stored in slice detection registers 1 to 4. after completion of slicing for specified lines, the slice enable bit for the slice line setting register is reset to 0. the next time the data slicer is ope rated, the slice enable bit of the slice line setting register should be set to 1. at this time, the corresponding slice detection register is cleared. the slice enable bit is sampled at the rising edge of the vsync signal. hence enabling of slice operation is valid until the next vsync signal after reset of the slice enable bit. figures 28.9 and 28.10 show examples of slice line specification and operation. for details, refer to section 28.2.2, slice line setting registers 1 to 4 (sline1 to sline4). section 28 data slicer rev.2.00 jan. 15, 2007 page 814 of 1174 rej09b0329-0200 the data slicer initialization and operation for one specification example are shown in figure 28.9. reset the slice enable bit reset the slice enable bit generate an even field slice completion interrupt contents of slice line settin g re g isters slice line settin g re g ister re g ister no. 1 2 3 4 1 1 1 0 even odd even d > c b > a odd enable field line start initialize the data slicer reset the slice enable bit generate an odd field slice completion interrupt even field odd field line c line b line d line a set the slice (even and odd) field mode re g isters set the slice line settin g re g isters 1 to 4 (except the enable bits) an external vsync interrupt occurs execute slicin g for line b an external vsync interrupt occurs execute slicin g for line d execute slicin g for line c an external vsync interrupt occurs set the enable bits of the slice line settin g re g isters 1 throu g h 3 to 1 note: data slice operation is not performed for line a, because the enable bit = 0. further, when the same line is specified within the same field, erroneous operation results; do not specify the same line in the same field. for details on the external vsync interrupt, refer to section 27.2.2, sync separation control re g ister (sepcr). figure 28.9 example of slice line specification and operation (1) section 28 data slicer rev.2.00 jan. 15, 2007 page 815 of 1174 rej09b0329-0200 operation for data slicer resetting for a second specification is shown in figure 28.10. a < b < c < d start respecification even field contents of slice line settin g re g isters slice line settin g re g ister re g ister no. 1 2 3 4 1 1 1 1 even even even even enable field line line a line b line d line c e < f < g < h contents of slice line settin g re g isters slice line settin g re g ister re g ister no. 1 2 3 4 1 1 1 1 odd odd odd odd enable field line line e line h line f line g an external vsync interrupt occurs execute slicin g for line a execute slicin g for line b reset the slice enable bit reset the slice enable bit execute slicin g for line c reset the slice enable bit execute slicin g for line d reset the slice enable bit generate an even field slice completion interrupt read each slice detection re g ister and slice data re g ister. respecify slice lines and set the slice enable bit. odd field an external vsync interrupt occurs execute slicin g for line e execute slicin g for line f reset the slice enable bit reset the slice enable bit execute slicin g for line g reset the slice enable bit execute slicin g for line h reset the slice enable bit generate an odd field slice completion interrupt read each slice detection re g ister and slice data re g ister. respecify slice lines and set the slice enable bit. an external vsync interrupt occurs figure 28.10 example of slice li ne specification and operation (2) section 28 data slicer rev.2.00 jan. 15, 2007 page 816 of 1174 rej09b0329-0200 28.3.2 slice sequence figure 28.11 shows the slice sequence. ye s no is it the last line in the field to be sliced? ? line detection the specified slice line and field match the line count and detected field ? clock run-in detection count the number of clock run-in pulses in clock run-in period ? start bit detection initiate start bit detection accordin g to the start bit detection startin g position specified by the re g ister ? data samplin g data is stored in the 16-bit shift re g ister at a data samplin g clock of 32xfh g enerated after the time specified by the re g ister from the start bit detection store data in the 16-bit shift re g ister to the slice data re g ister ? data end detection detect whether or not slice data is input at the 17th data samplin g clock pulse set the clock run-in count set the start bit detection fla g (enable the start bit detection) set clock run-in detection fla g (enable the clock run-in detection) set the slice completion interrupt fla g read the slice detection re g ister and slice data re g ister write the slice line settin g re g ister set the slice line enable bit set the data end detection fla g (data end: no data detected at the 17th data samplin g clock pulse) reset the slice enable bit figure 28.11 slice sequence section 28 data slicer rev.2.00 jan. 15, 2007 page 817 of 1174 rej09b0329-0200 28.4 32-bit sli ce operation the data slicer operates in 32-bit mode when the dsl32b bit (bit 0) in the synchronization separation afc control register (sepacr) of the synchronization separator is set to 1. synchronization separation afc control register (sepacr): 0 0 1 0 r/w 2 0 r/w 3 0 4 0 ? 0 r/w 5 6 0 7 ? ? arst dotcksl dsl32b 0 r/w ndetie r/w ? r/w * ndetif hsel bit: initial value: r/w: bit 0 ? dsl32b (dsl32b): specifies whether the data slicer performs slice operation in 32-bit mode or 16-bit mode. bit 0 dsl32b description 0 slice operation in 16-bit mode (initial value) 1 slice operation in 32-bit mode the dsl32b bit can select 32-bit slice operation for th e data slicer. when this bit is set to 1, the data slicer starts operation at the line specified by slice line setting registers 1 and 2. only one slice line can be selected for a field, so the same values must be set in slice line setting registers 1 and 2. operation is not guaranteed when different values are set in slice line setting registers 1 and 2. the start bit detection starting position is specified similar to as in 16-bit mode. however, the values set in bits stbe4 to stbe0 (stbo4 to st bo0) must be adjusted so that the detection starting position is not before rising edge 1. this is to prevent the rising edge 1 that is input during the start bit detection window signal from being acci dentally detected. for details on the detection start timing, see figure 28.12. after the rising edge of the start bit is detected, a sampling clock is generated at every 64 fh, starting from time td set in bits dlye4 to dlye 0 (dlyo4 to dlyo0). a total of 34 sampling clocks are output for start bit detection, slice data, and end data detection. for details on the generation timing of the sampling clocks, see figure 28.13. after slice operation has ended, the same values are stored in slice detection registers 1 and 2, and the 32-bit slice data is written to slice data registers 1 and 2 which are connected by cascade connection. 16 bits from the start bit are written to slice data register 1, and the remaining 16 bits to slice data register 2. for details on writing slice data to slice data registers, see figure 28.14. section 28 data slicer rev.2.00 jan. 15, 2007 page 818 of 1174 rej09b0329-0200 when this bit is set to 1, be sure to clear the slice enable bit (bit 7) in slice line setting registers 3 and 4 to 0. in 32-bit mode, slice line setting register 3 and 4, slice detection registers 3 and 4, and slice data registers 3 and 4 are disabled. slicer starting position clock run-in detection window start bit detection window data slicer starting position start bit detection starting position approx. 23.5 s start bit detection range ts tmin = approx. 25.5 s te = approx. 29.5 s c.video stb setting 288 * fh 1 tmin = 25.5 s < ts = 23.5 s + s (value set in stb4 to stb0) rising edge 1 rising edge 2 note: be sure to set the ts starting position after rising edge 1. note: * 288 when bit frqsel (bit 0) in sepimr (synchronization separator) is set to 0. 224 when bit frqsel (bit 0) in sepimr (synchronization separator) is set to 1. figure 28.12 start bit detection starting position when bit dsl32b is 1 section 28 data slicer rev.2.00 jan. 15, 2007 page 819 of 1174 rej09b0329-0200 slice data detected start bit sampling clock start bit 1st word 2nd word 3rd word 4th word 0110 b7 6 5 4 3 2 1 b0b 7 6 5 4 3 2 1 b0b 7 6 5 4 3 2 1 b0b 7 6 5 4 3 2 1 b0 lsb td: data sampling delay time (dyle4 to dyle0 (dlyo4 to dlyo0)) msb 64 fh 64 fh 576 * fh 1 td = ns [(value set in dly4 to dly0) + 2] note: * 576 when bit frqsel (bit 0) in sepimr (synchronization separator) is set to 0. 448 when bit frqsel (bit 0) in sepimr (synchronization separator) is set to 1. figure 28.13 sampling clock when bit dsl32b is 1 bit 15 14 s data 1 data byte 1 data byte 2 data byte 3 data byte 4 s data 2 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 b7 6 5 4 3 2 1 b0 b7 6 5 4 3 2 1 b0 b7 6 5 4 3 2 1 b0 b7 6 5 4 3 2 1 b0 slice data figure 28.14 slice data and slice data registers when bit dsl32b is 1 section 28 data slicer rev.2.00 jan. 15, 2007 page 820 of 1174 rej09b0329-0200 section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 821 of 1174 rej09b0329-0200 section 29 on-screen display (osd) 29.1 overview osd (on-screen display) is a function for superimposing arbitrary characters or display patterns on a tv image signal. the display screen consists of up to 32 characters 12 rows; a single character consists of 12 dots 18 lines. up to 384 different character types * 1 can be registered, and each character display can be connected to the top, bottom, right, and left of another character. hence in addition to alphanumerics and kanji characters, graphics can also be displayed. text display and superimposed display are supported, and there are composite video signal output and digital outputs. there are a wealth of ornamental features as we ll, including blinking display, borders, cursors, halftone display, buttons, and enlarged display. analog functions (video amp, analog switch) peri pheral to osd are also incorporated. the sync separator has an afc circuit built-in, for stable display. 29.1.1 features ? screen configuration: 32 characters 12 rows ? character size: 12 dots 18 lines ? character types: 384 types * 1 ? supports text display and superimposed display ? display enlargement: 1 1, 2 2 (line units, vertical horizontal) ? blinking: can be set in single character units blinking period can be set to either 32/fv or 64/fv (for the entire screen) (fv: vertical sync signal frequency) ? border function: single-dot borders in each of eight directions border color: in text mode, white or black, and brightness fixed in superimposed mode, black, and brightness fixed ? supported tv formats: ntsc, pal, secam ? display position: horizontal and vertical direction leading positions are set, and line intervals can be set section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 822 of 1174 rej09b0329-0200 ? digital outputs: r, g, b; output of yco (character data bit strings) and ybo (character display positions) ? background colors: eight hues * 2 background brightness, chroma saturation: f our brightness levels, two chroma levels ? character colors: text display: eight hues (character units) * 2 superimposed display: white character brightness, chroma saturation: four brightness levels, two chroma levels ? cursor: character background colored during text display (character units) ? cursor colors: eight hues (line units) * 2 cursor brightness, chroma saturation: two brightness levels, two chroma levels ? halftone display: feature for reducing the brightness/chroma saturation of the image signal in the text background during superimposed display to render it semi-transparent, so that characters appear to float above the background (character units) ? halftone gray shades: two levels (row units) ? button display: two types notes: 1. includes blank charact er as character code h'000. 512 character types for the h8s/2199r flash memory version, 384 character types for the h8s/2199r group mask-rom version, and 256 character types for the h8s/2197s and h8s/2196s. 2. background colors, character colors, cu rsor colors: the background, character, and cursor colors in text display include black and white. in secam, only black and white are supported. for details, refer to section 29.1.5, tv formats and display modes. section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 823 of 1174 rej09b0329-0200 29.1.2 block diagram a block diagram of the osd appears in figure 29.1. sync separator tv format 4/2fsc dot clock 4/2fsc in cvin1 4/2fsc out hv horizontal display position control display data ram vertical display position control button control shift re g ister border control 4/2fsc oscillator cvout halftone control sync tip clamp secam character control switch- in g color burst character, back- g round, and cursor color g eneration display control character, border, cursor, button, and back g round r g b yco ybo character data rom figure 29.1 osd block diagram section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 824 of 1174 rej09b0329-0200 29.1.3 pin configuration the osd pin configuration is shown in table 29.1. even when not using the data slicer, the composite video signal should be input to cvin2 in order to perform sync separation from the composite video signal. table 29.1 osd pin configuration block name abbrev. i/o function csync/hsync input/output composite sync signal input/output or horizontal sync signal input sync signal input/output vlpf/vsync input pin for connecting external lpf for vertical sync signal or input pin for vertical sync signal afcosc input/output afc oscillation signal afc oscillation afcpc input/output afc by-pass capacitor connecting pin sync separator lpf for afc afclpf input/output external lpf connecting pin for afc osd analog power ovcc input analog power for osd, data slicer, and sync separator osd analog ground ovss input analog ground for osd, data slicer, and sync separator composite video signal input cvin1 input composite video signal input (2 vpp, with a sync tip clamp circuit) composite video signal output cvout output composite video signal output (2 vpp) 4fsc/2fscin input 4fsc or 2fsc input fsc oscillation 4fsc/2fscout output 4fsc or 2fsc output r output color signal output (r) for character, border, cursor, background, and button, or a port g output color signal output (g) for character, border, cursor, background, and button, or a port color signal output b output color signal output (b) for character, border, cursor, background, and button, or a port yco output character data output (digital output), or a port osd character data output ybo output character display position output (digital output), or a port data slicer composite video signal cvin2 input composite video signal input (2 vpp, with a sync tip clamp circuit) section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 825 of 1174 rej09b0329-0200 29.1.4 register configuration table 29.2 shows the osd registers. table 29.2 register configuration name abbrev. r/w size initial value address * 1 character data rom osdrom ? 24576 bytes * 3 ? h'040000 display data ram (master) osdram r/w 768 bytes undefined h'd800 display data ram (slave) ? ? 768 bytes undefined ? row register 1 cline1 r/w byte h'00 h'd200 row register 2 cline2 r/w byte h'00 h'd201 row register 3 cline3 r/w byte h'00 h'd202 row register 4 cline4 r/w byte h'00 h'd203 row register 5 cline5 r/w byte h'00 h'd204 row register 6 cline6 r/w byte h'00 h'd205 row register 7 cline7 r/w byte h'00 h'd206 row register 8 cline8 r/w byte h'00 h'd207 row register 9 cline9 r/w byte h'00 h'd208 row register 10 cline10 r/w byte h'00 h'd209 row register 11 cline11 r/w byte h'00 h'd20a row register 12 cline12 r/w byte h'00 h'd20b vertical display position register vpos r/w word h'f000 h'd20c horizontal display position register hpos r/w byte h'00 h'd20e digital output specification register dout r/w byte h'02 h'd20f screen control register dcntl r/w word h'0000 h'd210 osd format register dform r/(w) * 2 word h'00f8 h'd212 notes: 1. lower 16 bits of the address. (excluding character data rom) 2. only 0 can be written to bits 8 and 0 to clear the flags. 3. 32768 bytes for the h8s/2199r flash memory version, 24576 bytes for the h8s/2199r group mask-rom version, and 16384 bytes for the h8s/2197s and h8s/2196s. section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 826 of 1174 rej09b0329-0200 29.1.5 tv formats and display modes table 29.3 indicates support for different tv formats in each display mode. operation is not guaranteed if a frequency resulting from division by 4 or 2 from the 4fsc/2fsc input pin is not one of those listed in table 29.3. table 29.3 tv formats and display modes tv format fsc (mhz) text display superimposed mode m/ntsc 3.579545 8 colors supported 4.43-ntsc 4.43361875 8 colors supported m/pal 3.57561149 8 colors supported n/pal 3.58205625 8 colors supported b.g.h/pal, i/pal, d.k/pal 4.43361875 8 colors supported secam 4.43361875 white/black supported 29.2 description of display functions 29.2.1 superimposed mode and text display mode there are two types of osd display: superimposed and text display. (1) superimposed mode in superimposed mode, the state of operation of a vcr, the current time, and other text and graphics are displayed on an ordinary tv image. in doing so, there is no mixing of the background image and the display character co lors. there is an internal afc circuit, enabling reliable text display. in addition, a halftone function, in which the brightness and chroma saturation of the background screen in the character display area is reduced to make characters appear to ?float? above the background, is also available. other features include a character border function. (2) text display mode in text display mode, characters and graphic data can be displayed in synchronous with the internal sync signal generated by the internal csync generator circuit in the sync separator. the background color for display can be selected from among eight hues. there are plentiful ornamental functions, including functions for displaying cursors and buttons; cursor and text colors can be selected from among eight hues, making this function ideal for use in programming vcr recording and setting modes. section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 827 of 1174 rej09b0329-0200 29.2.2 character configuration displayed characters and patterns consist of 12 dots 18 lines per character. there are notes on creation of osd fonts. for details, refer to section 29.8, notes on osd font creation. an example of a character configuration appear s in figure 29.2. an example of an enlarged character appears in figure 29.3. 12 dots 18 lines characters borders (1) character confi g uration example (2) character confi g uration example (with borders outside character) figure 29.2 character configuration examples section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 828 of 1174 rej09b0329-0200 12 dots 24 dots 18 lines 36 lines (1) standard character size (2) enlar g ed character size figure 29.3 enlarged character example 29.2.3 on-screen display configuration the on-screen display area consists of 12 horizontal rows each containing up to 32 characters. the correspondence between display data ram and the screen display is indicated in figure 29.4. the starting position for display can be set freely by using the display position registers to set the horizontal starting display position, vertical starting display position, and row interval. even when the frequency of the afc reference clock (dot clock) is modified, the display configuration (12 horizontal rows each containing 32 characters) will not change; characters in the region protruding outside the display area should be blank characters. for information on the display position registers, refer to section 29.5.1, display positions, and section 29.5.8, display position registers (hpos and vpos). section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 829 of 1174 rej09b0329-0200 row 1 row 2 row 11 row 12 1st character d800 d840 da80 dac0 da82 dac2 da84 dac4 da86 dac6 dabe dafe d802 d842 d804 d844 d806 d846 d83e d87e note: d800 to dafe indicate the lower 16 bits of addresses in the on-screen display ram. 32nd character 2nd character 3rd character 4th character figure 29.4 correspondence between disp lay data ram and on-screen display 29.3 settings in character units the following items can be set in character units by using the display data ram. 29.3.1 character configuration characters can be set freely by writing, to the di splay data ram, the character data rom address (character code) at which the char acter to be displayed is stored. for explanations of the character data rom and display data ram, refer to section 29.3.6, character data rom (osdrom), and section 29.3.7, display data ram (osdram). 29.3.2 character colors character colors in text display mode can be se t in character units thro ugh the character color specification bit in display data ram. table 29.4 shows the correspondence between character color code settings and color output signals. for details on display data ram, refer to section 29.3.7, display data ram (osdram). in the secam tv format, only black and white can be used in text display mode, and in superimposed mode characters are wh ite, with a faint background color. section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 830 of 1174 rej09b0329-0200 table 29.4 correspondence between character color code settings and color output signals r 1 1 1 1 0 0 0 0 g 1 1 0 0 1 1 0 0 b display data ram settings * 1 0 1 0 1 0 1 0 r, g, or b port output white yellow magenta red cyan green blue black c.video output (ntsc) white same phase 3 /4 /2 3 /2 7 /4 black c.video output (pal) white 0 3 /4 /2 3 /2 7 /4 black note: * can be specified in character units. 29.3.3 halftones/cursors (1) halftones the halftone function reduces the brightness and chroma saturation of the image signal in the character background to make it semi-transparent , so that characters appear to float above the background. by specifying halftone in the display data ram, halftone can be toggled in character units. here the halftone levels are specified in the row register. in the secam format, use of halftones or bordering is recommended. (2) cursors the cursor function colors the background area of a character. by specifying the cursor in display data ram, cursor display can be toggled in character units. the cursor color and brightness are specified in the row register; within a given ro w, the same color and brightness are used. the chroma saturation can be set for the entire screen. note: cursor display is a function for use in text display mode only; halftones are a function for use in superimposed mode only. the display data ram halftone/cursor specification bit is dual-purpose, so that depending on the disp lay mode, function may switch automatically between halftone/cursor. figure 29.5 shows examples of halftone and cursor display. for details on display data ram, refer to section 29.3.7, display data ram (osdram). for an explanation of each register, refer to section 29.4.5, row registers (clinen, n = rows 1 to 12). section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 831 of 1174 rej09b0329-0200 18 lines 12 dots cursor (1) halftone display (supported in superimposed mode) (2) cursor display (supported in text display mode) back g round character 12 dots halftone back g round character 18 lines figure 29.5 halftone and cursor display examples 29.3.4 blinking blinking is a function in which displayed characters are displayed intermittently. by specifying blinking in display data ram, text can be made to blink in character units. the blinking period can be chosen from two values through the screen control register. blinking is supported both in superimposed mode and text display mode. digital outputs (yco, r, g, and b) can be made to blink or not blink through the digital output specification register. the ybo digital output cannot be made to blink. for details on display data ram, refer to section 29.3.7, display data ram (osdram). for an explanation of each register, refer to sec tion 29.5.9, screen control register (dcntl), and section 29.7.3, digital output specification register (dout). buttons cannot be made to blink. for notes on blinking, refer to section 29.8.3, note 3 on font creation (blinking). section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 832 of 1174 rej09b0329-0200 29.3.5 button display button display is a function in which a frame is drawn around a character string; buttons can be set in character units in display data ram. there are two types of button: one type of button appears to be raised or floating, and the other type appe ars to be lowered or sunken. by switching from the raised button type to the lowered button type, the button appears to have been depressed; such displays are ideal for screens on which various settings are to be made. button displays can be used simultaneously with the blinking function, but blinking can only be used for characters; buttons cannot be made to blink. when used with enlarged char acters, the button width is enlarged to two dots by two lines. buttons are horizontal rectangles; vertical-rectangle buttons cannot be created. in order to create a button with three or more ch aracters, a button display (start) character and a button display (end) character should be specified. multiple buttons can be created in a single row, but the button pattern in a given row is the same for all buttons in that row. the button pattern can be set in row units; white brightness is 75ire, and black brightness is 15 ire. both are values relative to the pedestal (5 ire). these brightness values are for reference. figure 29.6 shows examples of button display. for details on display data ram, refer to section 29.3.7, display data ram (osdram). for an explanation of each register, refe r to section 29.4.5, row registers (clinen, n = rows 1 to 12). in a button display, the button pattern re places the outer periphery of the 12 dot 18 line character region; this should be born in mind when creating character fonts. refer to section 29.8.4, note 4 on font creation (buttons). section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 833 of 1174 rej09b0329-0200 bptn bon1 bon0 bptn bon1 bon0 0 0 0 0 0 1 0 1 0 0 0 0 0 0/1* 0/1* 0 1 1 note: * do not set (start) or (end). 1 0 0 1 0 0 1 0 0 1 0 1 1 1 0 1 1 1 figure 29.6 button display examples 29.3.6 character data rom (osdrom) the character data rom (osdrom) contains 384 character types*, each c onsisting of 12 dots by 18 lines. user programs can write individual character data sets. however, character code h'000 is fixed as a blank character, and a new character pa ttern for this code cannot be set by the user. the character data rom (osdrom) is referenced by character codes in the display data ram, and dots of display character data are read for each scanning line. this character data rom can be accessed by the cpu as part of user rom. for details, refer to section 29.11, character data rom (osdrom) access by cpu. the memory map appears in figure 29.7. an ex ample of configuration for a single character appears in figure 29.8. note: 512 character types for the h8s/2199r flash memory version, 384 character types for the h8s/2199r group mask-rom version, and 256 character types for the h8s/2197s and h8s/2196s. section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 834 of 1174 rej09b0329-0200 memory map bit data for character code h'000 (blank character display) * 1 notes: 1. character code h'000 is reserved for blank character display and is not available for the user. all bit data of this character code must be 0, as shown below. line 1, bits 11 to 8 osd rom internal i/o re g isters internal i/o re g isters osd ram 000000 040000 040040 040041 040042 040043 040044 040045 040062 040063 040064 04007f 04013f 045fc0 045fff * 2 04003f 040040 04007f 040080 0400bf 0400c0 0400ff 040100 040000 045fff * 2 cpu pro g ram ffffff h' f h' f h' f h' f h' ff h' ff 040000 : h'f0 040001 : h'00 040002 : h'f0 040003 : h'00 040022 : h'f0 040023 : h'00 040024 : h'ff 04003f : h'ff : : : : bit data for character code h'001 bit data for character code h'002 bit data for character code h'003 bit data for character code h'004 bit data for character code h'17f line 1, bits 7 to 0 line 2, bits 7 to 0 line 3, bits 7 to 0 line 2, bits 11 to 8 line 3, bits 11 to 8 line 18, bits 7 to 0 line 18, bits 11 to 8 ) line 1 ) line 2 ) line 18 2. these addresses represent the h8s/2199r group addresses. figure 29.7 osd rom map section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 835 of 1174 rej09b0329-0200 line number data 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 32 f000 f000 f3fc f3fc f300 f300 f300 f300 f3f0 f3f0 f300 f300 f300 f300 f300 f300 f000 f000 ffff ffff 1110987654321 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 line 12 dots 18 dots 32 words 16 bits bit unused area figure 29.8 osdrom data configuration (for the letter ?f?) note: osdrom consists of 12 dots 18 lines per character. when character data is written to flash memory, addresses are written in a 16-bit 32-word area as shown in figure 29.8. data in the unused area should be set to 1. in addition, character data for blank display should always be set to 0. 29.3.7 display data ram (osdram) 8 * 9 * r/w 10 * r/w 11 * 12 * r/w * r/w 13 15 bon0 cr cg cb c8 * r/w blnk 14 * r/w ht/cr r/w r/w bon1 bit: initial value: r/w: 0 * 1 * r/w 2 * r/w 3 * 4 * r/w * r/w 5 7 c4 c3 c2 c1 c0 * r/w c7 6 * r/w c6 r/w r/w c5 bit: initial value: r/w: * : undefined display data ram for osd (osdra m) contains 12 rows of 32 characters each, or 384 characters (384 words), and consists of master ram and slave ram. master ram can be read and written by the cpu; slave ram is accessed by the osd. section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 836 of 1174 rej09b0329-0200 the osd display changes when the data written to master ram is transferred to the slave ram. data is transferred from the master ram to the slave ram by setting the ldreq bit in the osd format register to 1. at this time, when the dtmv bit is 0, transfer is performed at the moment the ldreq bit is set to 1; when the dtmv bit is 1, transfer is performed in synchronous with the vsync signal after the ldreq bit is set to 1. after transfer, the ldreq bit is cleared to 0. during transfer, the ldreq bit remains set to 1; ma ster ram should be accessed only after confirming that the ldreq bit has been cl eared to 0. if the cpu accesses master ram during transfer, the access is invalid and the vacs bit in the osd format register is se t to 1. the master ram can be accessed by the cpu even in the module stop mode. after power-down mode is cancelled, the osdram must be initialized. for details on the osd format register, refer to section 29.6.6, osd format register (dform). bit 15 ? blinking specification bit (blnk): turns blinking (intermittent display) on and off for characters in character units. blinking for digital outputs (yco, r, g, and b) is set by the digital output specification register. digital output (ybo) cannot be set to blink. osdram bit 15 description blnk c.video output 0 blinking is off 1 blinking is on dout osdram bit 4 bit 15 description dobc blnk digital output (yco, r, g, b) 0 blinking is off 0 1 blinking is off 1 0 blinking is off 1 blinking is on section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 837 of 1174 rej09b0329-0200 bit 14 ? halftone/cursor display specification bit (ht/cr): turns halftone/cursor display on and off in character units. the superimposed/text display mode switching bit of the screen control register is used for switching between halftone and cursor display. in digital outputs (r, g, and b), when the rgbc bit of the digital output specification register is set to 1 in either superimposed or text display mode to select output of display data for all of characters/borders/cursor/background/button display, the cursor color data specified by the cursor color specification bit of the row register is output. in secam tv format, it is recommended that halftone display be used. dcntl osdram bit 14 bit 14 description dispm ht/cr c.video output 0 halftone is off 0 1 halftone is on 1 0 cursor display is off 1 cursor display is on dout osdram bit 6 bit 14 description rgbc ht/cr digital output (r, g, b) 0 0/1 character is output (halftone/cursor specification invalid) 1 0 character is output (halftone/cursor display off) 1 cursor color data specified by the cursor color specification bit of row register is output section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 838 of 1174 rej09b0329-0200 bits 13 and 12 ? button specification bits (bon1, bon0): set buttons in character units in conjunction with the bptnn bit of the row register. to create a button with three or more characters, no-button display characters or butt on display (one character) must be specified between a button display (start) character and a button display (end) character. for details, refer to figure 29.6, button display example. clinen osdram bit 7 bit 13 bit 12 bptnn bon1 bon0 description display 0 no button is displayed 0 1 button is displayed (start) 0 button is displayed (end) 0 1 1 button is displayed (one character) 1 0 no button is displayed 0 1 button is displayed (start) 1 0 button is displayed (end) 1 button is displayed (one character) section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 839 of 1174 rej09b0329-0200 bits 11 to 9 ? character color specificati on bits (cr, cg, cb): specify character colors in character units. in superimposed mode, the only character colo r is white, and register settings are invalid. for digital outputs (r, g, and b), character color data specified by the char acter color specification bits for both superimposed and text display modes is output. osdram character color bit 11 bit 10 bit 9 c.video output cr cg cb ntsc pal r,g,b outputs 0 black black black 0 1 blue 0 7 /4 7 /4 green 0 1 1 3 /2 3 /2 cyan 1 0 /2 /2 red 0 1 3 /4 3 /4 magenta 1 0 same phase 0 yellow 1 white white white bits 8 to 0 ? character codes (c8 to c0): set character codes (h'000 to h'17f) to be displayed. note: character code h'000 is defined as blank (nothing displayed). for the h8s/2199r group, character display is not guaranteed if character codes from h'180 to h'1ff are specified. for the h8s/2197s and h8s/2196s, character display is not guaranteed if character codes from h'100 to h'1ff are specified. section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 840 of 1174 rej09b0329-0200 29.4 settings in row units the following items can be set in row units by using the row registers. 29.4.1 button patterns characters can be set freely by writing, to disp lay data ram, the character data rom address (character code) at which the char acter to be displayed is stored. for information on character data rom and display data ram, refer to section 29.3.6, character data rom (osdrom), and section 29.3.7, display data ram (osdram). the button pattern specification bit of the row regi sters can be used to select the button pattern (raised or lowered pattern) in row units. 29.4.2 display enlargement the size of characters can be sel ected in row units by using the ch aracter size specification bit of the row register. when selecting enlarged char acters, the border width and button width also change to accommodate the character size. 29.4.3 character brightness character brightness can be set in row units using the character brightness specification bit of the row register. four different charact er brightnesses can be selected. 29.4.4 cursor color, brightness, halftone levels (1) cursor color cursor colors can be set in row units using the cursor color specification bit of the row register. table 29.5 shows the correspondence between cursor color code settings and color output signals. cursor display functions in text display mode only. for details on row registers, refer to section 29.4.5, row registers (clinen, n = rows 1 to 12). section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 841 of 1174 rej09b0329-0200 table 29.5 correspondence between cursor color code settings and co lor output signals r 1 0 g 1 0 1 0 b row register settings * 1 0 1 0 1 0 1 0 r, g, or b port output white yellow magenta red cyan green blue black c.video output (ntsc) white same phase 3 /4 /2 3 /2 7 /4 black c.video output (pal) white 0 3 /4 /2 3 /2 7 /4 black note: * can be set in display block units. (2) cursor brightness cursor brightness can be set in row units using the cursor brightness specification bit of the row register. two different brightness levels can be selected. for details on row registers, refer to section 29.4.5, row registers (clinen, n = rows 1 to 12). (3) halftone levels halftone levels can be set in row units using the cursor brightness specification bit of the row register. two different halftone levels can be selected. figure 29.9 shows examples of a halftone level. halftone settings function only in superimposed mode. for details on row registers, refer to section 29.4.5, row registers (clinen, n = rows 1 to 12). section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 842 of 1174 rej09b0329-0200 100ire 0ire ?40ire 100ire 0ire ?40ire 100ire 0ire ?40ire white character 50% halftone cursor re g ion cursor re g ion cursor re g ion (b) 50% halftone (a) no halftone (c) 30% halftone 30% halftone white character white character figure 29.9 halftone level examples (c.video) 29.4.5 row registers (clinen, n = rows 1 to 12) 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 7 clun0 krn kgn kbn klun 0 r/w bptnn 6 0 r/w szn r/w r/w clun1 bit: initial value: r/w: there are a total of 12 row registers (clinen), for use with rows 1 to 12. row register n is used in conjunction with display data ram to set the character size, button pattern, cursor color, etc., for the nth row. e ach of these is an 8-b it read/write register. section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 843 of 1174 rej09b0329-0200 when reset, when the module is stopped, in sleep mode, in standby mode, in watch mode, in subactive mode, or in subsleep mode, the registers are initialized to h'00. all of the row registers 1 to 12 have the same specifiable format. when the osd display update timing control bit (dtmv) is 1, the osd display is updated to the row register settings in synchronous with the vsync signal (osdv). bit 7 ? button pattern specification bit (bptnn n = 1 to 12): sets the button pattern for the nth row. for button specification, refer to section 29.3.7, display data ram (osdram). bit 7 bptnn description 0 pattern causing buttons in the nth row to appear to be raised aa (initial value) 1 pattern causing buttons in the nth row to appear to be lowered aa bit 6 ? character size specification bit (szn, n = 1 to 12): sets the size of characters. the border width and button width also change accordi ng to the character size. these settings are common to superimposed and text display modes and to c.video output and digital outputs. bit 6 szn description 0 character display size: single height single width (initial value) 1 character display size: double height double width section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 844 of 1174 rej09b0329-0200 bits 5 and 4 ? character brightness specification bits (clun1, clun0, n = 1 to 12): set the character brightness. the character bright ness differs with the character color. in superimposed mode, white is the only character color. this setting has no effect on digital outputs (yco, ybo, r, g, and b). bit 5 bit 4 clun1 clun0 character color character brightness level 0 0 ire (initial value) 0 1 10 ire 0 20 ire 1 1 black 30 ire 0 25 ire (initial value) 0 1 45 ire 0 55 ire 1 1 blue, green, cyan, red, yellow, magenta 65 ire 0 white 45 ire (initial value) 0 1 70 ire 1 0 80 ire 1 90 ire note: all brightness levels are with reference to the pedestal level (5 ire). brightness levels are reference values. section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 845 of 1174 rej09b0329-0200 bits 3 to 1 ? cursor color specification bits (krn, kgn, kbn, n = 1 to 12): set the cursor color in row units. c.video output in superimposed mode uses halftone display, so that cursor color specifications are invalid. ? cursor colors in text display mode cursor color bit 3 bit 2 bit 1 c.video output krn kgn kbn ntsc pal r, g, b outputs 0 black black black (initial value) 0 1 blue 0 7 /4 7 /4 green 0 1 1 3 /2 3 /2 cyan 1 0 /2 /2 red 0 1 3 /4 3 /4 magenta 1 0 same phase 0 yellow 1 white white white ? cursor colors in superimposed mode bit 3 bit 2 bit 1 cursor color krn kgn kbn c.video output r, g, b outputs 0 black (initial value) 0 1 blue 0 green 0 1 1 cyan 0 red 0 1 magenta 0 yellow 1 1 1 specification invalid (halftone display in superimposed mode) white section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 846 of 1174 rej09b0329-0200 bit 0 ? cursor brightness/halftone level specification bit (klun, n = 1 to 12): sets the cursor brightness/halftone level in row units. cursor brightness differs for different cursor colors. this setting has no effect on digital outputs (yco, ybo, r, g, and b). ? cursor brightness in text display mode bit 0 klun cursor color cursor brightness level 0 0 ire (initial value) 1 black 25 ire 0 25 ire (initial value) 1 blue, green, cyan, red, yellow, magenta 45 ire 0 white 45 ire (initial value) 1 55 ire note: all brightness levels are with reference to the pedestal level (5ire). brightness levels are reference values. ? halftone levels in superimposed mode bit 0 klun description (halftone levels) 0 50% halftone (initial value) 1 30% halftone section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 847 of 1174 rej09b0329-0200 29.5 settings in screen units the following items can be set in screen units by using vertical display position register, horizontal display position register, and screen control register. 29.5.1 display positions (1) vertical display start position the vertical display start position can be set in single scanning line units using the vertical position specification bits of the vertical display position register. in setting display positions, the following should be noted. ? settings should be chosen to ensure that the display does not overlap with the vertical retrace line. ? when the display protrudes outside the screen, characters in the protruding region should be blank characters (cha racter code h'000). the base point for display start positions is shown in figure 29.10. pre-equalizin g period post-equalizin g period vertical synchro- nization period line counter 0123456 figure 29.10 base point for vertical display start positions (2) vertical display interval the vertical display interval can be set in single scanning line units using the line interval specification bit of the vertical display position register. ? when the display protrudes outside the screen, characters in the protruding region should be blank characters (char acter code h'000). (3) horizontal display start position the horizontal display start position can be set in units equal to double the dot clock cycle using the horizontal position specification bit of the horizontal display position register. section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 848 of 1174 rej09b0329-0200 the base point for the horizontal display start position is the center of the horizontal sync signal. note the following when choosing display position settings. ? settings should be chosen such that the display does not overlap with the color burst. ? when the display protrudes outside the screen, characters in the protruding region should be blank characters (cha racter code h'000). the base point for the horizontal display start position is shown in figure 29.11. horizontal display start position set by the display position specification re g ister osd display base point note: * base point when the 4/2fsc clock is selected as the dot clock. * figure 29.11 base point for horizontal display start position 29.5.2 turning the osd display on and off the osd display can be turned on and off using the display on/off bit of the screen control register. 29.5.3 display method display can be switched between text display mode and superimposed mode, and while in text display mode the display can be switched between interlaced and noninterl aced display, using the display mode specification bit of the screen control register. 29.5.4 blinking period a blinking period of either approximately 0.5 sec (32/fv) or approximately 1 sec (64/fv) can be selected using the blinking period specification bit of the screen control register. section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 849 of 1174 rej09b0329-0200 29.5.5 borders borders on the periphery of characters can be set using the border specifica tion bit of the screen control register. for an example of border display, see figure 29.2. the border color can be set in screen units using the border color specification bit of the screen control register. in text display mode, the border color can be selected from either white or black. in superimposed mode, all borders are black only. the horizontal size of borders is one dot (the same as one dot in a character), but for enlarged characters is two dots. the vertical size of borders is one line (the same as one line in a character), but for enlarged characters is two lines. for an explanation of the screen control register, refer to section 29.5.9, screen control register (dcntl). there are notes on borders; refer to section 29.8, notes on osd font creation. in the secam format, use of halftones or bordering is recommended. 29.5.6 background color and brightness in text display mode, the background color can be selected from among eight hues, and the brightness from among four levels, using the background color specification bits and background brightness select bits of the screen control register. 29.5.7 character, cursor, and background chroma saturation in text display mode, the chroma saturation of the character, cursor, and background can each be selected from among two levels using the charact er chroma specification bit, cursor chroma specification bit, and background chroma specification bit of the screen control register, respectively. section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 850 of 1174 rej09b0329-0200 29.5.8 display position registers (hpos and vpos) the hpos and vpos include the horizontal display position register and the vertical display position register. (1) horizontal display position register (hpos) 0 1 r/w 2 r/w 3 4 r/w r/w 5 7 hp4 0 hp3 0 hp2 0 hp1 0 hp0 0 r/w hp7 0 r/w r/w r/w hp6 0 hp5 0 6 bit: initial value: r/w: the horizontal display position register is used to set the horizontal display start position for characters. it is an 8-bit read/write register. when reset, when the module is stopped, in sleep mode, in standby mode, in watch mode, in subactive mode, or in subsleep mode, the horizontal display position register is initialized to h'00. when the osd display update timing control bit (dtmv) is 1, the osd display is updated to th e horizontal display pos ition register settings synchronously with the vsync signal (osdv). bits 7 to 0 ? horizontal display start position specification bits (hp7 to hp0): set the display start position in the horizontal direction. setting units are twice the dot clock cycle. refer to the base point for the horizontal display start position in figure 29.11. if the horizontal display start position is hs ( s), then hs is given by 2 tc (value of hp7 to hp0), where tc is the dot clock cycle. (2) vertical display position register (vpos) 8 9 r/w 10 r/w 11 12 ? ? 13 15 ? 1 vspc2 0 vspc1 0 vspc0 0 vp8 0 ? ? 1 r/w r/w ? ? 1 ? 1 14 bit: initial value: r/w: 0 1 r/w 2 r/w 3 4 r/w r/w 5 7 vp4 0 vp3 0 vp2 0 vp1 0 vp0 0 r/w vp7 0 r/w r/w r/w vp6 0 vp5 0 6 bit: initial value: r/w: the vertical display position register is a 16-bit read /write register used to set the character size, vertical display start position, and vertical-direction row interval. when reset, when the module is stopped, in sleep mode, in standby mode, in watch mode, in subactive mode, or in subsleep mode, the vertical display position register is initiali zed to h'f000. when the osd display update timing control bit (dtmv) is 1, the osd display is updated to the vertical display position register settings synchronously with the vsync signal (osdv). section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 851 of 1174 rej09b0329-0200 bits 15 to 12 ? reserved: cannot be modified and are always read as 1. bits 11 to 9 ? vertical row interval specification bits (vspc2 to vspc0): set the row interval in the vertical direction. they can be set in single scanning line units. bit 11 bit 10 bit 9 vspc2 vspc1 vspc0 description 0 no row interval (initial value) 0 1 row interval: one scanning line 0 row interval: two scanning lines 0 1 1 row interval: three scanning lines 1 0 row interval: four scanning lines 0 1 row interval: five scanning lines 1 0 row interval: six scanning lines 1 row interval: seven scanning lines bits 8 to 0 ? vertical display start position specification bits (vp8 to vp0): set the display start position in the vertical direction. the vertical display start position can be set in single scanning line units. the base point of the display start position is the vertical sync signal. refer to the base point for the vertical display start position in figure 29.10. if the vertical display start position is vs ( s), then vs is given by vs = th (value of vp8 to vp0), where th is the horizontal sync signal period ( s), corresponding to a single horizontal scanning line. 29.5.9 screen control register (dcntl) 8 9 r/w 10 ? 11 12 r/w r/w 13 15 blks 0 osdon 0 ? 0 edge 0 edgc 0 r/w vdspon 0 r/w r/w r/w dispm 0 lacem 0 14 bit: initial value: r/w 0 1 r/w 2 r/w 3 4 r/w r/w 5 7 blu1 0 blu0 0 camp 0 kamp 0 bamp 0 r/w br 0 r/w r/w r/w bg 0 bb 0 6 bit: initial value: r/w the dcntl is a 16-bit read/write register used to switch between superimposed and text display modes, set the background and color for text display mode in screen units, and turn osd display on and off. section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 852 of 1174 rej09b0329-0200 when reset, when the module is stopped, in sleep mode, in standby mode, in watch mode, in subactive mode, or in subsleep mode, the dcntl is initialized to h'0000. when the osd display update timing control bit (dtmv) is 1, the osd display is updated to the screen control register settings except the setting in bit 13 (lacem bit) synchronously with the vsync signal (osdv). bit 15 ? osd c. video display enable bit (vdspon): turns osdc c.video display output on and off. bit 15 vdspon description 0 osd c.video display is off (initial value) 1 osd c.video display is on bit 14 ? superimposed/text display mo de select bit (dispm): selects superimposed mode or text display mode. when selecting a display mode, the dot clock also serves as the afc circuit reference clock, and so the afc circuit reference hsync signal must be switched. for details, refer to section 27.3.6, automatic frequency controller (afc). bit 14 dispm description 0 superimposed mode is selected (initial value) 1 text display mode is selected bit 13 ? interlaced/noninterlaced di splay select bit (lacem): selects interlaced or noninterlaced text displa y mode. when noninterlaced text di splay is selected, the internally generated hsync and vsync freque ncy can be modified. for details, refer to section 27.2.11, internal sync frequency register (infrqr). bit 13 lacem description 0 noninterlaced display is selected (initial value) 1 interlaced display is selected section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 853 of 1174 rej09b0329-0200 bit 12 ? blinking period select bit (blks): selects the character blinking period. the duty is 50%. the blinking period differs somewhat depending on the tv format selected by the tvm2 bit of the osd format register (either a 52 5-line system or a 625-line system). dform dcntl bit 15 bit 12 tvm2 blks description (blinking period) 0 approx. 0.5 sec (32/fv = 0.53 sec) (initial value) 0 1 approx. 1.0 sec (64/fv = 1.07 sec) 1 0 approx. 0.5 sec (32/fv = 0.64 sec) (initial value) 1 approx. 1.0 sec (64/fv = 1.28 sec) note: fv is the vertical sync signal frequency. bit 11 ? osd display start bit (osdon): starts osd display. when the osd display start bit is 0, the osd internal display circuit stops operation. in conjunction with the osd c.video display enable bit (bit 15), changes operation as follows. when accessing character data rom (osdrom) from the cpu, this bit should always be cleared to 0. if this bit is set to 1, access by the cpu is not guaranteed. bit 15 bit 11 vdspon osdon description 0/1 0 osd display is stopped (c.video output and digital output both off) (initial value) 0 1 osd display is started (digital output only) 1 1 osd display is started (both c.video output and digital output enabled) bit 10 ? reserved: cannot be modified and is always read as 0. when 1 is written to this bit, correct operation is not guaranteed. bit 9 ? border specificati on bit (edge): sets the border for characters for the entire screen. bit 9 edge description 0 no character border (initial value) 1 character border section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 854 of 1174 rej09b0329-0200 bit 8 ? border color specifica tion bit (edgc): selects the border color. border color specifications for c.video output are invalid in superimposed mode. border brightness levels are 0 ire for black and 90 ire for white. note: brightness levels are with reference to the pedestal level (5ire). brightness levels are reference values. ? border color in text display mode bit 8 border color edgc c.video output r, g, b outputs 0 black black (initial value) 1 white white ? border color in superimposed mode bit 8 border color edgc c.video output r, g, b outputs 0 specification invalid (black) black (initial value) 1 white section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 855 of 1174 rej09b0329-0200 bits 7 to 5 ? background color specification bits (br, bg, bb): used to select the background color in text display mode. background color specifications for c.video output are invalid in superimposed mode. ? background colors in text display mode background color bit 7 bit 6 bit 5 c.video output br bg bb ntsc pal r, g, b outputs 0 black black black (initial value) 0 1 blue 0 7 /4 7 /4 green 0 1 1 3 /2 3 /2 cyan 0 /2 /2 red 0 1 3 /4 3 /4 magenta 0 same phase 0 yellow 1 1 1 white white white ? background colors in superimposed mode bit 7 bit 6 bit 5 background color br bg bb c.video output r, g, b outputs 0 black (initial value) 0 1 blue 0 green 0 1 1 cyan 0 red 0 1 magenta 0 yellow 1 1 1 specification invalid white section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 856 of 1174 rej09b0329-0200 bits 4 and 3 ? background brightness select bits (blu1, blu0): select the background brightness in text display mode. these settings have no effect on digital outputs (yco, ybo, r, g, and b). bit 4 bit 3 bul1 bul0 background brightness 0 10 ire (initial value) 0 1 30 ire 1 0 50 ire 1 70 ire note: brightness levels are with reference to the pedestal level (5ire). brightness levels are reference values. bit 2 ? character chroma select bit (camp): selects the character chroma amplitude in text display mode. this setting has no effect on digital outputs (yco, ybo, r, g, and b). bit 2 camp description 0 character chroma amplitude: 60 ire (initial value) 1 character chroma amplitude: 80 ire note: amplitudes are reference values. bit 1 ? cursor chroma select bit (kamp): selects the cursor chroma amplitude in text display mode. this setting has no effect on digital outputs (yco, ybo, r, g, and b). bit 1 kamp description 0 cursor chroma amplitude: 60 ire (initial value) 1 cursor chroma amplitude: 80 ire note: amplitudes are reference values. section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 857 of 1174 rej09b0329-0200 bit 0 ? background chroma select bit (bamp): selects the background chroma amplitude in text display mode. this setting has no effect on digital outputs (yco, ybo, r, g, and b). bit 0 bamp description 0 background chroma amplitude: 60 ire (initial value) 1 background chroma amplitude: 80 ire note: amplitudes are reference values. 29.6 other settings 29.6.1 tv format the osd supports m/ntsc, 4.43-ntsc, m/pal, n/pal, b, g, h/pal, i/pal, d, k/pal, and secam formats. see table 29.3. 29.6.2 display data ram control the osd display data ram consists of master ram and slave ram. the master ram can be read and written by the cpu; the slave ram is accessed by the osd. the data written to master ram is transferred to slave ram to switch the osd display. the dtmv bit can be used to switch between timing the transfer of data to occur when the ldreq bit is set to 1, or to occur synchronously with the vsync signal after ldreq is set to 1. for details, refer to section 29.6.6, osd format register (dform). 29.6.3 timing of osd display updates using register rewriting it is possible to switch the timing of osd display updates to occur simultaneously with register rewrites, or to occur synchronously with the vsync signal (osdv) after a register rewrite. for details, refer to section 29.6.6, osd format register (dform). section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 858 of 1174 rej09b0329-0200 29.6.4 4fsc/2fsc for a 4fsc/2fsc signal, either an external cloc k signal is input, or a crystal oscillator can be connected. if an external clock signal is input, the signal must be amplified using a dedicated amplifier circuit; this is set using the register. either 4fsc or 2fsc input can be selected. if a 2fsc signal is input, some colors cannot be displayed. for details, see table 29.7. 29.6.5 osdv interrupts interrupts triggered by the vsync signal input to the osd (osdv interrupts) can be generated. in superimposed mode, interrupts are triggered by the external vsync signal, and in text display mode, they are triggered by the internal vsync signal generated in the sync separator. 29.6.6 osd format register (dform) 8 9 r/w 10 ? 11 12 r/w r/w 13 15 fscin 0 fscext 0 ? 0 osdve 0 osdvf 0 r/w tvm2 0 r/(w) * r/w r/w tvm1 0 tmv0 0 14 bit: initial value: r/w: 0 1 r/w 2 r/w 3 4 ? ? 5 7 ? 1 ? 1 dtmv 0 ldreq 0 vacs 0 ? ? 1 r/(w) * ? ? ? 1 ? 1 6 bit: initial value: r/w: note: * only 0 can be written to clear the fla g . the dform is used to set the tv format and control display data ram. the dform is a 16-bit read/write register. when re set, it is initialized to h'00f8. bits other than bits 12, 11, and 7 to 3 are cleared to 0 in module stop, sleep, standby, watch, subactive, and subsleep modes. when the module stop bit of the sync separator is 0, bits 12 and 11 must not be rewritten. section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 859 of 1174 rej09b0329-0200 bits 15 to 13 ? tv format select bits (tvm2 to tvm0): select the tv format. the specified clock signal should always be input. bit 15 bit 14 bit 13 bit 12 description tvm2 tvm1 tvm0 fscin tv format 4fsc (mhz) 2fsc (mhz) 0 14.31818 ? initial value 0 0 0 1 m/ntsc ? 7.15909 0 0 1 0 4.43-ntsc 17.734475 (17.734476) ? 1 ? 8.8672375 (8.867238) 0 1 0 0 m/pal 14.302446 (14.302444) ? 1 ? 7.15122298 0 1 1 0/1 must not be specified. 0 14.328225 (14.328224) ? 1 0 0 1 n/pal ? 7.1641125 1 0 1 0/1 must not be specified. 0 17.734475 (17.734476) ? 1 1 0 1 b, g, h/pal, i/pal, d, k/pal ? 8.8672375 (8.867238) 0 17.734475 (17.734476) ? 1 1 1 1 b, g, h/secam, l/secam, d, k, k1/secam ? 8.8672375 (8.867238) note: the 4fsc and 2fsc frequencies for secam do not conform to the secam tv format specifications. bit 12 ? 4/2fsc input select bit (fscin): selects 4fsc or 2fsc input. bit 12 fscin description 0 4fsc input is selected (initial value) 1 2fsc input is selected section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 860 of 1174 rej09b0329-0200 bit 11 ? 4/2fsc external input select bit (fscext): selects 4fsc or 2fsc input. bit 11 fscext description 0 4/2fsc oscillator uses a crystal oscillator (initial value) 1 4/2fsc uses a dedicated amplifier circuit for external clock signal input bit 10 ? reserved: always read as 0. when 1 is written to this bit, correct operation is not guaranteed. bit 9 ? osdv interrupt enable bit (osdve): enables or disables osdv interrupts. bit 9 osdve description 0 the osdv interrupt is disabled (initial value) 1 the osdv interrupt is enabled bit 8 ? osdv interrupt flag (osdvf): set when the osd detects the vsync signal. the timing for setting this flag differs depending on the osd display mode. in superimposed mode, it is set on the external vsync signal; in text display mode it is set on the internally generated vsync signal. bit 8 osdvf description 0 [clearing condition] when 0 is written after reading 1 (initial value) 1 [setting condition] when osd detects the vsync signal bits 7 to 3 ? reserved: always read as 1. when 0 is written to these bits, correct operation is not guaranteed. section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 861 of 1174 rej09b0329-0200 bit 2 ? osd display update timing control bit (dtmv): selects the timing for transfer of data from master ram to slave ram and for osd display update by register overwriting. bit 2 dtmv description 0 after the ldreq bit is written to 1, data is transferred from master ram to slave ram regardless of the vsync signal (osdv). the osd display is updated simultaneously with register * rewriting. note: * when transferring data using this setting, do not have the osd display data (initial value) 1 after the ldreq bit is written to 1, data is transferred from master ram to slave ram synchronously with the vsync signal (osdv). after rewriting the register, the osd display is updated synchronously with the vsync signal (osdv). note: the registers and register bits whose settings are reflected in the osd display are the row registers (cline), vertical display position register (vpos), horizontal display position register (hpos), screen control register ( dcntl) except bit 13, and the rgbc, ycoc, and dobc bits of the digital output specification register (dout). bit 1 ? master-slave ram transfer request and state bit (ldreq): requests transfer of data from master ram to slave ram. after this bit is written to 1, a transfer request is issued with timing selected by the dtmv bit. when read, th is bit indicates the state of data transfer from master ram to slave ram. note: to abort data transfer after writing this bit to 1, write it to 0. however, once data transfer begins it cannot be aborted. ? writing bit 1 ldreq description 0 requests abort of data transfer from master ram to slave ram 1 requests transfer of data from master ram to slave ram. after transfer is completed, this bit is cleared to 0 ? reading bit 1 ldreq description 0 data is not being transferred from master ram to slave ram (initial value) 1 data is being transferred from master ram to slave ram, or is being prepared for transfer. after transfer is completed, this bit is cleared to 0 section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 862 of 1174 rej09b0329-0200 bit 0 ? master-slave ram transfer state bit (vacs): is set to 1 if the cpu accesses osdram during transfer of data from master ra m to slave ram; the acce ss is invalid. this bit is not cleared automatically, and so should be cleared by writing 0. bit 0 vacs description 0 the cpu did not access osdram during data transfer (initial value) 1 the cpu accessed osdram during data transfer; the access is invalid 29.7 digital output 29.7.1 r, g, and b outputs r, g, and b outputs consist of display data in dot units for characters, background, cursors and other display elements. either of two output methods can be selected by the r, g, b digital output specification bit: characters only, or output of display data for all elements, including characters, borders, cursors, background, and buttons. here data for borders and buttons is output as white-equivalent (r = 1, g = 1, b = 1) or as black-equivalent (r = 0, g = 0, b = 0) data. the digital output blink control bit is used to select blinking for r, g, and b. the r, g, and b outputs are multiplexed with port 8 inputs/outputs. for details on pin function selection, refer to section 10.9, port 8. display data ram and the screen control register settings are output as display data output for characters, cursors and background in superimposed mode; this differs from the output data from the cvout pin. examples of r, g, b output are shown in figures 29.12 and 29.13. section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 863 of 1174 rej09b0329-0200 0 ram dout blnk dobc rgbc 0 r g b (low) (low) (low) (low) (low) r g b r g b r g b r (blinkin g ) g (blinkin g ) b (blinkin g ) r (blinkin g ) g (blinkin g ) b (blinkin g ) 1 0 0/1 1 0 1 0 11 1 11 back g round output example 1 character color: yellow (cr = 1, cg = 1, cb = 0) cursor color: cyan (kr = 0, kg = 1, kb = 1) back g round color: green (br = 0, bg = 1, bb = 0) border: none (edge = 0) button: displayed (pattern 1) button cursor border character border cursor button back g round figure 29.12 rgb output example (1) section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 864 of 1174 rej09b0329-0200 0 ram dout blnk dobc rgbc 0 r g b (low) (low) (low) (low) (low) (low) (hi g h) (low) (low) (low) (low) (low) r g b r g b r g b r (blinkin g ) g (blinkin g ) b (blinkin g ) r (blinkin g ) g (blinkin g ) b (blinkin g ) 1 0 0/1 1 0 1 0 11 1 1 1 output example 2 character color: yellow (cr = 1, cg = 1, cb = 0) cursor color: none (ht/cr = 0) back g round color: green (br = 0, bg = 1, bb = 0) border: black (edge = 1, edgc = 0) button: none button cursor border character border cursor button back g round back g round figure 29.13 rgb output example (2) section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 865 of 1174 rej09b0329-0200 29.7.2 yco and ybo outputs yco output consists of character and border data in dot units. either of two yco output methods can be selected by the yco digital output specification bit: output of characters only, or combined output of character and border data. the digital output blink control bit can be used to select blinking for yco output. the yco data output specification bit must be reset to 0 when bordering is not performed, and must be set to 1 when bordering is performed. ybo output is data for the character display area. 32 characters? worth of data is output starting from the start position set by the horizontal-direction start position specification bit of the display position register. here blank- character intervals have no character display, an d so there is no output. in addition, ybo output cannot be made to blink. the yco and ybo outputs are multiplexed with port 8 inputs/outputs. for details on pin function selection, refer to section 10.9, port 8. an example of yco output and that of ybo output appear in figures 29.14 and 29.15, respectively. 0 ram dout blnk dobc ycobc 0 1 0 1 0 1 yco yco yco yco yco (blinkin g ) yco (blinkin g ) (low) (low) 0/1 0 1 1 output example character color: yellow (cr = 1, cg = 1, cb = 0) cursor color: none (ht/cr = 0) back g round color: green (br = 0, bg = 1, bb = 0) border: black (edge = 1, edgc = 0) button: none button cursor border character border cursor button back g round back g round figure 29.14 yco output example section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 866 of 1174 rej09b0329-0200 horizontal display position display block character display position blank character row 1 ybo 1234567 29 32 ....................................................................... ..... figure 29.15 ybo output example 29.7.3 digital output specification register (dout) 0 1 ? 2 r/w 3 4 r/w r/w 5 7 dobc 0 dsel 0 crsel 0 ? 1 ? 0 ? ? 0 ? r/w r/w rgbc 0 ycoc 0 6 bit: initial value: r/w: the dout is used to choose settings for digital output. the dout is an 8-bit read/write register. when re set, when the module is stopped, in sleep mode, in standby mode, in watch mode, in subactive mode, or in subsleep mode, it is initialized to h'02. when the osd display update timing control bit is 1, the osd display is updated to the rgbc, ycoc and dobc bit settings synchronously with the vsync signal (osdv). the r, g, b, yco, and ybo outputs are multiplexed with port 8 inputs/outputs. for details on pin function selection, refer to section 10.9, port 8. bit 7 ? reserved: always read as 0. when 1 is written to this bit, correct operation is not guaranteed. bit 6 ? r, g, b digital output specification bit (rgbc): specifies the r, g, b digital output format. bit 6 rgbc description 0 character output is specified (initial value) 1 combined character, border, cursor, background, and button output is specified section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 867 of 1174 rej09b0329-0200 bit 5 ? yco digital output specification bit (ycoc): specifies the yco digital output format. this bit must be reset to 0 when bordering is not performed, and must be set to 1 when bordering is performed. bit 5 ycoc description 0 character output is specified (initial value) 1 combined character and border output is specified bit 4 ? digital output blink control bit (dobc): turns blinking on and off for digital outputs (yco, r, g, and b). digital output ybo cannot be made to blink. osdram dout bit 15 bit 4 blnk dobc description 0 does not blink (initial value) 0 1 does not blink 1 0 does not blink 1 blinks bit 3 ? r, g, b, yco, ybo pin function select bit (dsel): selects the r, g, b, yco, and ybo pins to function either as digital output pins, or as data slicer internal monitor signal pins. bit 3 dsel description 0 r, g, b, yco, ybo output function is selected (initial value) 1 data slicer monitor output function is selected r pin = signal selected by bit 2 (crsel) g pin = slice data signal analog-compared with cvin2 b pin = sampling clock generated within data slicer yco pin = external hsync signal (afch) synchronized within the lsi ybo pin = external vsync signal (afcv) synchronized within the lsi section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 868 of 1174 rej09b0329-0200 bit 2 ? monitor signal switching bit (crsel): selects whether a clock run-in detection window signal or a start bit det ection window signal is output. this bit setting is valid when dsel is 1, so that pins are used as data slicer internal monitor signal outputs. bit 2 crsel description 0 clock run-in detection window signal output is selected (initial value) 1 start bit detection window signal output is selected for information on slice data and the sampling clock, refer to section 28.2.2, slice line setting registers 1 to 4 (sline1 to sline4). for details on the clock run-in detection window signal, start bit detection window signal, external hsync signal (afch), and external vsync signal (afcv), refer to section 27, sync separator for osd and data slicer. bit 1 ? reserved: cannot be modified and is always read as 1. bit 0 ? reserved: always read as 0. when 1 is written to this bit, correct operation is not guaranteed. 29.7.4 module stop control register (mtstpcr) 7 1 r/w mstp 15 mstp 14 mstp 13 mstp 12 mstp 11 mstp 10 mstp 9 mstp 8 mstp 7 mstp 6 mstp 5 mstp 4 mstp 3 mstp 2 mstp 1 mstp 0 6 1 r/w 54 1 r/w mstpcrh mstpcrl 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w bit: initial value: r/w: the mstpcr consists of two 8-bit read/write registers for controlling the module stop mode. writing 0 to the mstp0 bit starts the osd modul e; setting the mstp0 bit to 1 stops the osd module at the end of a bus cycle and the module stop mode is entered. at this time, the cvout and digital outputs also stop. before writing 0 to this bit, set the mstp9 bit to 0, to operate the sync separator. the registers cannot be read or written to in module stop mode. however, character data rom (osdrom) and display data ram (osdram) can be read and written. for details, refer to section 4.5, module stop mode. section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 869 of 1174 rej09b0329-0200 bit 0 ? module stop (mstp0): specifies the module stop m ode for the osd module. bit 0 mstp0 description 0 clears the module stop mode for the osd module 1 specifies the module stop mode for the osd module (initial value) section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 870 of 1174 rej09b0329-0200 29.8 notes on osd font creation 29.8.1 note 1 on font creation (font width) in osd display, vertical and diagonal lines in fonts that are one dot wide may appear to be narrow due to a shift of 0.5h. display fonts should be created with liberal thicknesses. 29.8.2 note 2 on font creation (borders) borders extend beyond the character display frame in the x-direction, but no borders extend beyond the display frame in the y-direction. moreover, when borders are to the right or left of blank characters (h'000), borders extend beyond the display frame, but for the first and the 32nd characters in a displayed row (16th character when the character size is enlarged to double height double width), no borders extend beyond the display frame. examples of borders which extend beyond the display frame appear in figure 29.16 through figure 29.18. x-direction y-direction 12 dots characters borders 18 dots figure 29.16 border extending be yond the display frame (example) section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 871 of 1174 rej09b0329-0200 12 dots characters borders 18 dots blank display figure 29.17 border neighboring a blank character (example) 12 dots (a) 1st character (b) 32nd character 12 dots characters borders figure 29.18 examples of characters at the starting and ending positions in a row section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 872 of 1174 rej09b0329-0200 29.8.3 note 3 on font creation (blinking) blinking involves intermitte nt display within a specified disp lay frame only. when blinking is necessary, font data should not be set to the first or twelfth dots in the x-direction. figure 29.19 shows an example of blinking for characters with borders extending beyond the display frame. 12 dots x-direction y-direction 12 dots 18 dots characters borders figure 29.19 example of blinking with borders extending beyond the display frame section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 873 of 1174 rej09b0329-0200 29.8.4 note 4 on font creation (buttons) buttons replace the outermost perimeter of the ch aracter display area with a button pattern. it should be remembered that the button pattern display takes priority over display of the font and border, if any. figure 29.20 shows an example of button pattern display that takes priority over font and border. 12 dots button pattern: white 12 dots 18 dots characters borders button pattern: white button pattern: black button pattern: blac k figure 29.20 example of button pattern di splay taking priority over font and border section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 874 of 1174 rej09b0329-0200 29.9 osd oscillator, afc, and dot clock in order to use the osd, sync signals and a 4/2fsc clock signal are required. 29.9.1 sync signals the sync signal for text display mode is a signal created from a 4/2fsc clock or an afc reference clock. in superimposed mode, sync signals may be selected from one of the following three types. 1. horizontal/vertical sync signals separated by the sync separator from the composite video signal (cvin2) 2. horizontal/vertical sync signals separated by the sync separator from the composite sync signal (csync) 3. hsync and vsync signals input separately for details, refer to section 27, sync separator for osd and data slicer. 29.9.2 afc circuit the afc circuit averages the ?fluctuation? in the horizontal sync signal (hsync) during normal vcr playback, reducing osd display jitter. in addition, the afc circuit generates the dot clock. be sure that an external circuit is connected. for details, refer to section 27.3.6, automatic frequency controller (afc). 29.9.3 dot clock the dot clock is a clock used for x-direction (horizontal direction) osd display. the reference clock from the afc circuit or the 4/2fsc clock from the 4/2fscin pin can be selected with the dotcksl bit in the sync separator. ? reference clock from afc circuit the dot clock generated by the afc circuit is a clock synchronized with the horizontal sync signal. the dot clock frequency is 576 or 448 times the horizontal sync signal frequency (576 fh or 448 fh). the size of one dot in the horizontal direction of the osd display appearing on the screen is the equivalent of one dot clock cycle. accordingly, modifying the frqsel bit in the sync separator to change the horizontal sync signal frequency can adjust the dot size. the dot clock cycle is the same in superimposed mode and text display mode; it is also the same for both interlaced and n oninterlaced displays. it changes somewhat depending on the tv format. the relation between tv format and dot clock cycle is shown in table 29.6. section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 875 of 1174 rej09b0329-0200 ? 4/2fsc clock the dot clock generated by the 4/2fsc clock is the same clock that is input from the 4/2fscin pin. as a result, when the 4fsc-clock frequency is input, the osd display becomes smaller in the horizontal direction. when the 4/2fsc clock is used, use the osd in text display mode. using the osd in superimposed mode causes characters to flicker. table 29.6 dot clock cycle dot clock cycle tv format reference clock: 576 fh reference clock: 448 fh m/ntsc, 4.43-ntsc, m/pal, n/pal 110 ns (9.06 mhz) 142 ns (7.06 mhz) b, g, h/pal, i/pal, d, k/pal, secam 111 ns (9.00 mhz) 143 ns (7.00 mhz) 29.9.4 4/2fsc 1. 4/2fsc oscillator the 4/2fsc oscillator generates color signals for text display mode, and also generates the internal sync signal. a crystal oscillator can be connected, or an external clock can be input. the 4/2fsc frequency should be appropriate for the tv format. if an inappropriate frequency is used, or if no 4/2fsc signal is input, osd operation is not guaranteed. circuit constants should be chosen such that frequency deviation, including temperature effects, is within 30 ppm. an example of connection of a crystal oscillator appears in figure 29.21; an example of input of an external clock is shown in figure 29.22. section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 876 of 1174 rej09b0329-0200 power-down mode controller 4/2fsc in rf crystal c2 c1 note: rf = 1 m typ. crystal should be at a frequency appropriate for the tv format. c1, c2 should be specified such that frequency deviation, includin g temperature effects, is less than 30 ppm. figure 29.21 example of connection of a 4/2fsc crystal oscillator power-down mode controller external clock duty: 47 to 53% 4/2fsc in c r (open) note: c = 1000 pf typ when the external clock amplitude is 1 vp-p or lar g er, connect a resistor in series with capacitor c. external clock select figure 29.22 example of input of a 4/2fsc external clock section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 877 of 1174 rej09b0329-0200 2. for information on osd display colors for a 2fsc signal input, refer to table 29.7. in ntsc format, some colors cannot be displayed. in pal format, because alternating display is used, color muddiness, flickering and other problems may arise. table 29.7 osd display colors for 2fsc signal input character, cursor, and background color settings ntsc pal * rgb digital output yellow (same phase) yellow (same phase) yellow (3 /2, ? /2) yellow cyan (3 /2) cyan (3 /2) cyan ( , 0) cyan green (7 /4) cannot be specified green (? /2, 0) green magenta (3 /4) cannot be specified magenta (+ /2, ? ) magenta red ( /2) red ( /2) red (+ /2, ? /2) red blue ( ) blue ( ) blue ( /2, ?3 /2) blue white white white white black black black black note: * the pal color burst phase angle is /4 rad for 4fsc input, but is 0 rad or ? /2 rad for 2fsc, so that colors may differ from the color settings. 29.10 osd operation in cpu operation modes table 29.8 shows the osd cvout pin status for different cpu operating modes. during a transition to power-down mode, registers are initialized, and so register settings must be restored on return to active mode. table 29.8 osd operation for different cpu operating modes operating mode module stop bit dispm bit cvout pin reset 1 0 no output 0 chroma-through and osd display active 0 1 text display module stop 1 0 no output sleep, standby, watch, subactive, or subsleep retained 0 no output section 29 on-screen display (osd) rev.2.00 jan. 15, 2007 page 878 of 1174 rej09b0329-0200 29.11 character data rom (osdrom) access by cpu the character data rom can be accessed by the cp u as part of user rom. before accessing the character data rom by the cpu, clear the osdon bit in the screen control register to 0 to stop osd display, then set the osrome bit in the seri al timer register to 1. the character data rom can be accessed even in the module stop mode. if the osrome bit is set to 1 during osd disp lay, the character data rom cannot be accessed correctly by cpu. for details on osrome bit setting, refer to section 29.5.9, screen control register (dcntl). 29.11.1 serial timer co ntrol register (stcr) 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 ? osrome flshe ? iicx0 iicx1 ? ? r/w r/w ? r/w r/w ? ? ? 0 bit : initial value : r/w : bit 2 ? osd rom enable (osrome): controls the osd character data rom (osdrom) access. when this bit is set to 1, the osdrom can be accessed by th e cpu, and when this bit is cleared to 0, the osdrom cannot be accessed by the cpu but accessed by the osd module. before writing to or erasing the osdrom in the f-ztat version, be sure to set this bit to 1. note: during osd display, the osdrom cannot be accessed by the cpu. before accessing the osdrom by the cpu, be sure to clear the osdon bit in the screen control register to 0 then set the osrome bit to 1. if the osrome bit is set to 1 during osd display, the character data rom cannot be accessed correctly by cpu. bit 2 osrome description 0 osdrom is accessed by the osd (initial value) 1 osdrom is accessed by the cpu section 30 power supply circuit rev.2.00 jan. 15, 2007 page 879 of 1174 rej09b0329-0200 section 30 power supply circuit 30.1 overview the h8s/2199r group incorporates an internal power supply step-down circuit. use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 v, independently of the voltage of the power supply connected to the external v cc pin. as a result, the current consumed when an external power supply is used at 3.0 v or above can be held down to virtually the same low level as when used at approximately 3.0 v. 30.2 power supply connection (int ernal power supply step-down circuit on-chip) connect the external power supply to the v cc pin, and connect a capacitance of approximately 0.1 f between v cl and v ss , as shown in figure 30.1. the internal step-down circuit is made effective simply by adding this external circuit. notes: 1. in the external circuit interface, the external power supply voltage connected to v cc and the gnd potential connected to v ss are the reference levels . for example, for port input/output levels, the v cc level is the reference for the high level, and the v ss level is that for the low level. 2. the a/d converter, servo, and osd analog power supply are not affected by internal step-down processing. v cl v ss internal lo g ic step-down circuit internal power supply stabilization capacitance (approx. 0.1 f) v cc v cc = 4.0 v to 5.5 v figure 30.1 power supply connection (internal power supply step-down circuit on- chip) section 30 power supply circuit rev.2.00 jan. 15, 2007 page 880 of 1174 rej09b0329-0200 section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 881 of 1174 rej09b0329-0200 section 31 electrical characteristics 31.1 absolute maximum ratings table 31.1 lists the absolute maximum ratings. table 31.1 absolute maximum ratings item symbol value unit power supply voltage vcc ? 0.3 to +7.0 v input voltage (ports other than port 0) vin ? 0.3 to vcc +0.3 v input voltage (port 0) vin ? 0.3 to avcc +0.3 v a/d converter power supply voltage avcc ? 0.3 to +7.0 v a/d converter input voltage avin ? 0.3 to avcc +0.3 v servo power supply voltage svcc ? 0.3 to +7.0 v servo amplifier input voltage vin ? 0.3 to svcc +0.3 v osd power supply voltage ovcc ? 0.3 to +7.0 v operating temperature topr ? 20 to +75 c operating temperature (at flash memory program/erase) topr 0 to +75 c storage temperature tstr ? 55 to +125 c notes: 1. permanent damage may occur to the chip if absolute maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. 2. all voltages are relative to vss = svss = ovss = avss = 0.0 v. section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 882 of 1174 rej09b0329-0200 31.2 electrical characteristics of HD6432199R, hd6432198r, hd6432197r, and hd6432196r 31.2.1 dc characteristics of HD6432199R, hd6432198r, hd6432197r, and hd6432196r table 31.2 dc characteristics of HD6432199R, hd6432198r, hd6432197r, and hd6432196r (conditions: vcc = avcc = 4.0 v to 5.5 v * 1 , vss = 0.0 v, ta = ?20 to +75 c unless otherwise specified.) values item symbol applicable pins test conditions min typ max unit note md0 vcc = 2.5 v to 5.5 v 0.9 vcc ? vcc +0.3 0.8 vcc ? vcc +0.3 res , ic , irq0 to irq5 , synci vcc = 2.5 v to 5.5 v 0.9 vcc ? vcc +0.3 sck1, si1, ftia, ftib, ftic, ftid, rptrg, tmbi, adtrg 0.8 vcc ? vcc +0.3 osc1 vcc ?0.5 ? vcc +0.3 0.7 vcc ? vcc +0.3 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p60 to p67, p70 to p77, p80 to p87 vcc = 2.5 v to 5.5 v 0.8 vcc ? vcc +0.3 input high voltage v ih csync 0.7 vcc ? vcc +0.3 v section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 883 of 1174 rej09b0329-0200 values item symbol applicable pins test conditions min typ max unit note md0 vcc = 2.5 v to 5.5 v ?0.3 ? 0.1 vcc ? 0.3 ? 0.2 vcc res , ic , irq0 to irq5 , synci vcc = 2.5 v to 5.5 v ? 0.3 ? 0.1 vcc sck1, si1, ftia, ftib, ftic, ftid, rptrg, tmbi, adtrg ? 0.3 ? 0.2 vcc osc1 ? 0.3 ? 0.5 ? 0.3 ? 0.3 vcc p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p60 to p67, p70 to p77, p80 to p87 vcc = 2.5 v to 5.5 v ? 0.3 ? 0.2 vcc input low voltage v il csync ? 0.3 ? 0.2 vcc v ? i oh = 1.0 ma vcc ?1.0 ? ? v ? i oh = 0.5 ma ? vcc ?0.5 ? v refer- ence value output high voltage v oh so1, sck1, pwm0, pwm1, pwm2, pwm3, pwm14, buzz, tmo, tmow, ftoa, ftob, ppg0 to ppg7, rp0 to rp7, rp8 to rpb, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p60 to p67, p70 to p77, p80 to p87, sv1, sv2, r, g, b, yco, ybo ? i oh = 0.1 ma vcc = 2.5 v to 5.5 v vcc ?0.5 ? ? v section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 884 of 1174 rej09b0329-0200 values item symbol applicable pins test conditions min typ max unit note i ol = 1.6 ma ? ? 0.6 v so1, sck1, pwm0, pwm1, pwm2, pwm3, pwm14, buzz, tmo, tmow, ftoa, ftob, ppg0 to ppg7, rp0 to rp7, rp8 to rpb, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p70 to p77, p80 to p87, sv1, sv2, r, g, b, yco, ybo i ol = 0.4 ma vcc = 2.5 v to 5.5 v ? ? 0.4 v i ol = 20 ma ? ? 1.7 v i ol = 1.6 ma ? ? 0.6 v output low voltage v ol p60 to p67, i ol = 0.4 ma vcc = 2.5 v to 5.5 v ? ? 0.4 v md0 vin = 0.5 to vcc ?0.5 v ? ? 1.0 res , irq0 to irq5 , ic vin = 0.5 to vcc ?0.5 v ? ? 1.0 sck1, si1, sda0, scl0, sda1, scl1, ftia, ftib, ftic, ftid, trig, tmbi, adtrg vin = 0.5 to vcc ?0.5 v ? ? 1.0 osc1 vin = 0.5 to vcc ?0.5 v ? ? 1.0 input/ output leakage current ? i il ? p10 to p17, p20 to p27, p30 to p37, p40 to p47, p60 to p67, p70 to p77, p80 to p87, vin = 0.5 to vcc ?0.5 v ? ? 1.0 a p00 to p07, an8 to anb vin = 0.5 to avcc ?0.5 v ? ? 1.0 section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 885 of 1174 rej09b0329-0200 values item symbol applicable pins test conditions min typ max unit note pull-up mos current ? ip p10 to p17, p20 to p27, p30 to p37 vcc = 5.0 v, vin = 0 v 50 ? 300 a * 2 input capacity cin all input pins except power supply pins p23, p24, p25, and p26, and analog pins fin = 1 mhz, vin = 0 v, ta = 25 c ? ? 15 pf p23, p24, p25, p26 fin = 1 mhz, vin = 0 v, ta = 25 c ? ? 20 pf vcc = 5 v, f osc =10 mhz, high-speed mode ? 40 50 ma * 3 * 4 active mode current dissipation (cpu operating) i ope vcc vcc = 5 v, f osc =10 mhz, medium-speed mode (1/64) ? 25 ? ma refer- ence value * 4 active mode current dissipation (reset) i res vcc vcc = 5 v, f osc = 10 mhz ? 12 15 ma * 3 * 4 sleep mode current dissipation i sleep vcc vcc = 5 v, f osc = 10 mhz high-speed mode ? 15 20 ma * 3 * 4 vcc = 2.5 v, 32 khz with crystal oscillator ( sub = w/2) ? 90 150 * 3 * 4 subactive mode current dissipation i sub vcc vcc = 2.5 v, 32 khz with crystal oscillator ( sub = w/8) ? 40 ? a refer- ence value * 3 * 4 section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 886 of 1174 rej09b0329-0200 values item symbol applicable pins test conditions min typ max unit note vcc = 2.5 v, 32 khz with crystal oscillator ( sub = w/2) ? 30 50 * 3 * 4 subsleep mode current dissipation i subslp vcc vcc = 2.5 v, 32 khz with crystal oscillator ( sub = w/8) ? 20 ? a refer- ence value * 3 * 4 vcc = 2.5 v, 32 khz with crystal oscillator ? 6 12 a * 3 * 4 watch mode current dissipation i watch vcc vcc = 5.0 v, 32 khz with crystal oscillator ? 12 ? a refer- ence value * 3 * 4 standby mode current dissipation i stby vcc x1 = v cl , 32 khz without crystal oscillator ? ? 10 a * 3 * 4 ram data retaining voltage in standby mode v stby 2.0 v notes: 1. do not open the avcc and avss pin even when the a/d converter is not in use. 2. current value when the relevant bit of the pull-up mos select register (pur1 to pur3) is set to 1. 3. the current on the pull-up mos or the output buffer excluded. 4. excludes the current flowing in svcc and ovcc. section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 887 of 1174 rej09b0329-0200 table 31.3 pin status at cu rrent dissipation measurement mode res pin internal state pin oscillator pin active mode high-speed, medium- speed vcc operating vcc sleep mode high-speed, medium- speed vcc only cpu, servo circuits, and osd halted vcc reset vss reset vcc standby mode vcc all circuits halted vcc main clock: crystal oscillator sub clock: x1 pin = v cl subactive mode vcc only cpu and timer a operating vcc subsleep mode vcc only timer a operating vcc watch mode vcc only timer a operating vcc main clock: crystal oscillator sub clock: crystal oscillator section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 888 of 1174 rej09b0329-0200 table 31.4 bus drive characteristics of HD6432199R, hd6432198r, hd6432197r, and hd6432196r (conditions: vcc = avcc = 4.0 v to 5.5 v, vss = 0.0 v, ta = ?20 to +75 c) applicable pin: scl0 , scl1, sda0, sda1 values item symbol applicable pins test conditions min typ max unit note v t ? 0.2 vcc ? ? v v t + ? ? 0.7 vcc v schmitt trigger input v t + ?v t ? scl0, sda0, scl1, sda1 0.05 vcc ? ? v input high level voltage v ih scl0, sda0, scl1, sda1 0.7 vcc ? vcc +0.5 v input low level voltage v il scl0, sda0, scl1, sda1 ? 0.5 ? 0.2 vcc v i ol = 8 ma ? ? 0.5 output low level voltage v ol scl0, sda0, scl1, sda1 i ol = 3 ma ? ? 0.4 v scl and sda output fall time t of scl0, sda0, scl1, sda1 20 + 0.1cb ? 250 ns section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 889 of 1174 rej09b0329-0200 31.2.2 allowable output currents of HD6432199R, hd6432198r, hd6432197r, and hd6432196r the specifications for the digital pins are shown below. table 31.5 allowable output currents of HD6432199R, hd6432198r, hd6432197r, and hd6432196r (conditions: vcc = 2.5 v to 5.5 v, vss = 0.0 v, ta = ?20 to +75 c) item symbol value unit note allowable input current (to chip) i o 2 ma 1 allowable input current (to chip) i o 22 ma 2 allowable input current (to chip) i o 10 ma 3 allowable output current (from chip) ? i o 2 ma 4 total allowable input current (to chip) i o 80 ma 5 total allowable output current (from chip) ? i o 50 ma 6 notes: 1. the allowable input current is the maximum value of the current flowing from each i/o pin to v ss (except for port 6, scl0, sda0, scl1 and sda1). 2. the allowable input current is the maximum value of the current flowing from each i/o pin to v ss . this applies to port 6. 3. the allowable input current is the maximum value of the current flowing from each i/o pin to v ss . this applies to scl0, sda0, scl1 and sda1. 4. the allowable output current is the maximum value of the current flowing from v cc to each i/o pin. 5. the total allowable input current is the sum of the currents flowing from all i/o pins to v ss simultaneously. 6. the total allowable output current is the sum of the currents flowing from v cc to all i/o pins. section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 890 of 1174 rej09b0329-0200 31.2.3 ac characteristics of HD6432199R, hd6432198r, hd6432197r, and hd6432196r table 31.6 ac characteristics of HD6432199R, hd6432198r, hd6432197r, and hd6432196r (conditions: vcc = avcc = 4.0 v to 5.5 v, vss = 0.0 v, ta = ?20 to +75 c unless otherwise specified, ovcc = svcc = 4.75 v to 5.25 v.) values item symbol applicable pins test conditions min typ max unit note clock oscillation frequency f osc osc1, osc2 8 ? 10 mhz clock cycle time t cyc osc1, osc2 100 ? 125 ns figure 31.1 subclock oscillation frequency f x x1, x2 vcc = 2.5 v to 5.5 v ? 32.768 ? khz subclock cycle time t subcyc x1, x2 vcc = 2.5 v to 5.5 v ? 30.518 ? s osc1, osc2 crystal oscillator ? ? 10 ms oscillation stabilization time t rc x1, x2 32-khz crystal oscillator (vcc = 2.5 v to 5.5 v) ? ? 2 s external clock high width t cph osc1 40 ? ? ns external clock low width t cpl osc1 40 ? ? ns external clock rise time t cpr osc1 ? ? 10 ns external clock fall time t cpf osc1 ? ? 10 ns figure 31.1 external clock stabilization delay time t dext osc1 500 ? ? s figure 31.2 section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 891 of 1174 rej09b0329-0200 values item symbol applicable pins test conditions min typ max unit figure res pin low level width t rel res vcc = 2.5 v to 5.5 v 20 ? ? t cyc figure 31.3 input pin high level width t ih irq0 to irq5 , ic , adtrg , tmbi, ftia, ftib, ftic, ftid, rptrig vcc = 2.5 v to 5.5 v 2 ? ? t cyc t subcyc figure 31.4 input pin low level width t il irq0 to irq5 , ic , adtrg , tmbi, ftia, ftib, ftic, ftid, rptrig vcc = 2.5 v to 5.5 v 2 ? ? t cyc t subcyc t cyc t cph v il v ih osc1 t cpl t cpf t cpr figure 31.1 system clock timing section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 892 of 1174 rej09b0329-0200 vcc osc1 t dext * res (internal) 4.0v the t dext includes the res pin low level width 20 t cyc . note: * figure 31.2 external clock stabilization delay timing res v il t rel figure 31.3 reset input timing t il t ih v ih irq0 to irq5 , ic , adtrg , tmbi, ftia, ftib, ftic, ftid, rptrig v il figure 31.4 input timing section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 893 of 1174 rej09b0329-0200 31.2.4 serial interface timing of HD6432199R, hd6432198r, hd6432197r, and hd6432196r table 31.7 serial interface timing of HD6432199R, hd6432198r, hd6432197r, and hd6432196r (conditions: vcc = avcc = 4.0 v to 5.5 v, vss = 0.0 v, ta = ?20 to +75 c unless otherwise specified.) values item symbol applicable pins test conditions min typ max unit figure asynchronization 4 ? ? input clock cycle t scyc sck1 clock synchronization 6 ? ? t cyc input clock pulse width t sckw sck1 0.4 ? 0.6 t scyc input clock rise time t sckr sck1 ? ? 1.5 t cyc input clock fall time t sckf sck1 ? ? 1.5 t cyc figure 31.5 transmit data delay time (clock sync) t txd so1 ? ? 100 ns figure 31.6 receive data setup time (clock sync) t rxs si1 100 ? ? ns receive data hold time (clock sync) t rxh si1 100 ? ? ns t sckf t sckr v il or v ol v ih or v oh sck1 t sckw t scyc figure 31.5 sck1 clock timing section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 894 of 1174 rej09b0329-0200 v il v ih t txd sck1 so1 si1 t rxs t rxh v oh v ol figure 31.6 sci i/o timing/clock synchronization mode lsi output pin timin g reference level v oh : 2.0 v v ol : 0.8 v 30 pf 12 k 2.4 k vcc figure 31.7 output load conditions section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 895 of 1174 rej09b0329-0200 table 31.8 i 2 c bus interface timing of HD6432199R, hd6432198r, hd6432197r, and hd6432196r (conditions: vcc = avcc = 4.0 v to 5.5 v, vss = 0.0 v, ta = ?20 to +75 c unless otherwise specified.) values item symbol test conditions min typ max unit figure scl input cycle time t scl 12 ? ? t cyc scl input high pulse width t sclh 3 ? ? t cyc scl input low pulse width t scll 5 ? ? t cyc scl, sda input rise time t sr ? ? 7.5 * t cyc scl, sda input fall time t sf ? ? 300 ns scl, sda input spike pulse removal time t sp ? ? 1 t cyc sda input bus free time t buf 5 ? ? t cyc start condition input hold time t stah 3 ? ? t cyc re-transmit start condition input setup time t stas 3 ? ? t cyc stop condition input setup time t stos 3 ? ? t cyc data input setup time t sdas 0.5 ? ? t cyc data input hold time t sdah 0 ? ? ns scl, sda capacity load c b ? ? 400 pf figure 31.8 note: * can also be set to 17.5 t cyc depending on the selection of clock to be used by the i 2 c module. section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 896 of 1174 rej09b0329-0200 t stah t sr t sdah t scl t scll t sclh t sf t stas t sp t stos t sdas v il v ih sda scl p * s * sr * p * s, p and sr denote the followin g : s : start conditions p : stop conditions sr: re-transmit start conditions note: * t buf figure 31.8 i 2 c bus interface i/o timing section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 897 of 1174 rej09b0329-0200 31.2.5 a/d converter characteristics of HD6432199R, hd6432198r, hd6432197r, and hd6432196r table 31.9 a/d converter characteristics of HD6432199R, hd6432198r, hd6432197r, and hd6432196r (conditions: vcc = avcc = 4.0 v to 5.5 v, vss = avss = 0.0 v, ta = ?20 to +75 c unless otherwise specified.) values item symbol applicable pins test conditions min typ max unit note analog power supply voltage avcc avcc vcc ? 0.3 vcc vcc +0.3 v analog input voltage a vin an0 to an7, an8 to anb avss ? avcc v a icc avcc avcc = 5.0 v ? ? 2.0 ma analog power supply current a istop avcc vcc = 2.5 v to 5.5 v at reset and in power-down mode ? ? 10 a analog input capacitance c ain an0 to an7, an8 to anb ? ? 30 pf allowable signal source impedance r ain an0 to an7, an8 to anb ? ? 10 k resolution ? ? 10 bit absolute accuracy vcc = avcc = 5.0 v ? ? 4 lsb vcc = avcc = 4.0 v to 5.0 v ? 4 ? lsb referen- ce value conversion time 13.4 ? 26.6 s note: do not open the avcc and avss pin even when the a/d converter is not in use. set avcc = vcc and avss = vss. section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 898 of 1174 rej09b0329-0200 31.2.6 servo section electrical characteristics of HD6432199R, hd6432198r, hd6432197r, and hd6432196r table 31.10 servo section electrical characteristics of HD6432199R, hd6432198r, hd6432197r, and hd6432196r (reference values) (conditions: vcc = svcc = 5.0 v, vss = svss = 0.0 v, ta = 25 c unless otherwise specified.) reference values item symbol applicable pins test conditions min typ max unit note ctlgr3 = 0, ctlgr2 = 0, ctlgr1 = 0, ctlgr0 = 0, f = 10 khz 32.0 34.0 36.0 ctlgr3 = 0, ctlgr2 = 0, ctlgr1 = 0, ctlgr0 = 1, f = 10 khz 34.5 36.5 38.5 ctlgr3 = 0, ctlgr2 = 0, ctlgr1 = 1, ctlgr0 = 0, f = 10 khz 37.0 39.0 41.0 ctlgr3 = 0, ctlgr2 = 0, ctlgr1 = 1, ctlgr0 = 1, f = 10 khz 39.5 41.5 43.5 ctlgr3 = 0, ctlgr2 = 1, ctlgr1 = 0, ctlgr0 = 0, f = 10 khz 42.0 44.0 46.0 ctlgr3 = 0, ctlgr2 = 1, ctlgr1 = 0, ctlgr0 = 1, f = 10 khz 44.5 46.5 48.5 ctlgr3 = 0, ctlgr2 = 1, ctlgr1 = 1, ctlgr0 = 0, f = 10 khz 47.0 49.0 51.0 ctlgr3 = 0, ctlgr2 = 1, ctlgr1 = 1, ctlgr0 = 1, f = 10 khz 49.5 51.5 53.5 ctlgr3 = 1, ctlgr2 = 0, ctlgr1 = 0, ctlgr0 = 0, f = 10 khz 52.0 54.0 56.0 ctlgr3 = 1, ctlgr2 = 0, ctlgr1 = 0, ctlgr0 = 1, f = 10 khz 54.5 56.5 58.5 ctlgr3 = 1, ctlgr2 = 0, ctlgr1 = 1, ctlgr0 = 0, f = 10 khz 57.0 59.0 61.0 ctlgr3 = 1, ctlgr2 = 0, ctlgr1 = 1, ctlgr0 = 1, f = 10 khz 59.5 61.5 63.5 ctlgr3 = 1, ctlgr2 = 1, ctlgr1 = 0, ctlgr0 = 0, f = 10 khz 62.0 64.0 66.0 ctlgr3 = 1, ctlgr2 = 1, ctlgr1 = 0, ctlgr0 = 1, f = 10 khz 64.5 66.5 68.5 ctlgr3 = 1, ctlgr2 = 1, ctlgr1 = 1, ctlgr0 = 0, f = 10k hz 67.0 69.0 71.0 pb-ctl input amplifier voltage gain ctl (+) ctlgr3 = 1, ctlgr2 = 1, ctlgr1 = 1, ctlgr0 = 1, f = 10 khz 69.5 71.5 73.5 db section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 899 of 1174 rej09b0329-0200 reference values item symbol applicable pins test conditions min typ max unit note v+th ac coupling, c = 0.1 f typ (non pol) ? 250 ? pb-ctl schmitt input v ? th ctlsmt (i) ac coupling, c = 0.1 f typ (non pol) ? ? 250 ? mvp analog switch on resistance reb ctlfb ? 150 ? ctl (+) ? 12 ? rec-ctl output current ictl ctl ( ? ) series resistance = 0 ? 12 ? ma rec-ctl pin-to- pin resistance rctl ? 10 ? k ctl reference output voltage ctlref ? 1/2 svcc ? v cfg pin bias voltage cfg ? 1/2 sv cc ? v cfg input level cfg ac coupling, c = 1 f typ, f = 1 khz 1.0 ? ? vpp cfg digital input high level v ih cfg when digital signal input method is selected (cfgcomp = 1) 0.8 vcc ? vcc +0.3 v cfg digital input v il cfg when digital signal input method is selected (cfgcomp = 1) ? 0.3 ? 0.2 vcc v cfg input impedance cfg ? 10 ? k v+thcf rise threshold level ? 2.25 ? cfg input threshold value v ? thcf cfg fall threshold level ? 2.75 ? v v+thdf rising edge schmitt level ? 1.95 ? dfg schmitt input v ? thdf dfg falling edge schmitt level ? 1.85 ? v v+thdp rising edge schmitt level ? 3.55 ? dpg schmitt input v ? thdp dpg falling edge schmitt level ? 3.45 ? v v oh ? i oh = 0.1 ma 4.0 ? ? v om no load, hi-z = 1 ? 2.5 ? 3-level output voltage v ol vpulse i ol = 0.1 ma ? ? 1.0 v 3-level output pin divided voltage resistance vpulse ? 15 ? k digital input high level v ih 0.8 vcc ? vcc +0.3 digital input low level v il comp, exctl, excap, exttrg ? 0.3 ? 0.2 vcc v section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 900 of 1174 rej09b0329-0200 reference values item symbol applicable pins test conditions min typ max unit note digital output high level v oh ? i oh = 1 ma vcc ?1.0 ? ? digital output low level v ol h.ampsw, c.rotary, videoff, audioff, drmpwm, cappwm, sv1, sv2 i ol = 1.6 ma ? ? 0.6 v current dissipation i ccsv svcc at no load ? 5 10 ma cfg duty cfg ac coupling, c = 1 f typ, f = 1 khz 48 ? 52 % section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 901 of 1174 rej09b0329-0200 31.2.7 osd electrical characteristics of HD6432199R, hd6432198r, hd6432197r, and hd6432196r table 31.11 osd electrical characteristics of HD6432199R, hd6432198r, hd6432197r, and hd6432196r (reference value) (conditions: vcc = ovcc = 5.0 v, vss = ovss = 0.0 v, ta = 25 c unless otherwise specified) reference values item symbol applicable pins test conditions min typ max unit note composite video input voltage v cvin cv in1 cv in2 ? 2 v pp v cl1 cv in1 ? 1.2 1.4 1.6 clamp voltage v cl2 cv in2 ? 1.8 2 2.2 v c.video gain g cvc cv in1 cv out at chromathrough f = 3.58 mhz v in = 500 mvpp ? 3 ? 2 0 db pedestal bias v ped cv out 45 ire * 1 color burst bias v bst 40 ire * 1 v bl1 10 v bl2 30 v bl3 50 background bias black, blue, green, cyan, red, magenta, yellow, white v bl4 70 ire * 2 v kbl1 0 black v kbl2 25 v kol1 25 blue, green, cyan, red, magenta, yellow v kol2 45 v kcl1 45 cursor bias white v kcl2 55 ire * 2 section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 902 of 1174 rej09b0329-0200 reference values item symbol applicable pins test conditions min typ max unit note v cbl1 cv out 0 v cbl2 10 v cbl3 20 black v cbl4 30 v col1 25 v col2 45 v col3 55 blue, green, cyan, red, magenta, yellow v col4 65 v ccl1 45 v ccl2 70 v ccl3 80 character bias white v ccl4 90 ire * 2 v edg1 0 edge brightness level v edg2 90 ire * 2 v btn1 15 button brightness level v btn2 75 ire * 2 color burst amplitude v bsta 40 ire v cra1 60 chroma amplitude (background, cursor, character) blue, green, cyan, red, magenta, yellow v cra2 80 ire colorburst bstn 0 blue blun green grnn 7 /4 cyan cynn 3 /2 red redn /2 magenta mztn 3 /4 chroma hue angle (background, cursor, character) (ntsc) yellow yetn 0 rad * 3 section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 903 of 1174 rej09b0329-0200 reference values item symbol applicable pins test conditions min typ max unit note colorburst bstp cvout /4 blue blup green grnp 7 /4 cyan cynp 3 /2 red redp /2 magenta mztp 3 /4 chroma hue angle (background, cursor, character) (pal) yellow yelp 0 rad * 3 ccmp1 cvin2 ? 5 ? ccmp2 ? 10 ? ccmp3 ? 15 ? csync separation comparator ccmp4 ? 20 ? ire * 1 ecmp1 cvin2 ? 0 ? ecmp2 ? 5 ? ecmp3 ? 15 ? ecmp4 ? 20 ? ecmp5 ? 25 ? ecmp6 ? 35 ? eds separation comparator ecmp7 ? 40 ? ire * 2 v ih 0.85 ovcc ? ovcc +0.3 v input high level v iht csync/hsync v lpf /vsync 0.7 ovcc ? ovcc +0.3 v v il ? 0.3 ? 0.3 ovcc v input low level v ilt csync/hsync v lpf /vsync ? 0.3 ? 0.15 ovcc v output high level v oh csync/hsync ? i oh = 0.4 ma ovcc ? 1.4 ? ? v output low level v ol csync/hsync i ol = 0.4 ma ? ? 1.4 v oscillation stabilizing time t rc 4/2fscin 4/2fscout crystal oscillator ? ? 40 ms section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 904 of 1174 rej09b0329-0200 reference values item symbol applicable pins test conditions min typ max unit note m/ntsc ? 14.31818 ? mhz 4/2fscin 4/2fscout b, g, h/pal i/pal d, k/pal 4.43-ntsc b, g, h/secam l/secam d, k, k1/secam ? 17.734475 (17.734476) ? mhz n/pal ? 14.328225 ? mhz 4 fsc m/pal ? 14.30244596 ? mhz 2 fsc m/ntsc ? 7.15909 ? mhz 4/2fscin 4/2fscout b, g, h/pal i/pal d, k/pal 4.43-ntsc b, g, h/secam l/secam d, k, k2/secam ? 8.8672375 (8.867238) ? mhz n/pal ? 7.1641125 ? mhz oscillating frequency m/pal ? 7.15122298 ? mhz v fsc 4/2fscin 4/2fscout ac coupling c = 1 f typ 0.3 ? vcc +0.3 vpp v ih 4/2fscin 0.7 vcc ? vcc +0.3 external clock input level v il ? 0.3 ? 0.3 vcc v external clock duty 4/2fscin 4/2fscout 47 50 53 % 6.3 9 11.7 mhz afc reference clock (dot clock) afc osc afc osc lc oscillation 4.9 7 9.1 mhz current dissipation i ccosd ovcc at no signal ? 14 ? ma notes: ire: units for video amplitude; 0.714 v video level is specified as 100 ire 4fsc and 2fsc must be adjusted within 30 ppm, including temperature dependency. 1. bias from the sync tip clamp level (reference value after ? 6 db). 2. bias from the pedestal level (reference value after ? 6 db). 3. at 4fsc input. section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 905 of 1174 rej09b0329-0200 31.3 electrical characteristics of hd6432197s and hd6432196s 31.3.1 dc characteristics of hd6432197s and hd6432196s ? preliminary ? table 31.12 dc characteristics of hd6432197s and hd6432196s (conditions: vcc = avcc = 4.0 v to 5.5 v * 1 , vss = 0.0 v, ta = ?20 to +75 c unless otherwise specified.) values item symbol applicable pins test conditions min typ max unit note md0 vcc = 2.5 v to 5.5 v 0.9 vcc ? vcc +0.3 0.8 vcc ? vcc +0.3 res, ic, irq0 to irq5 vcc = 2.5 v to 5.5 v 0.9 vcc ? vcc +0.3 sck1, si1, rptrg, tmbi, adtrg 0.8 vcc ? vcc +0.3 osc1 vcc ?0.5 ? vcc +0.3 0.7 vcc ? vcc +0.3 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p60 to p67, p70 to p77, p80 to p87 vcc = 2.5 v to 5.5 v 0.8 vcc ? vcc +0.3 input high voltage v ih csync 0.7 vcc ? vcc +0.3 v section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 906 of 1174 rej09b0329-0200 values item symbol applicable pins test conditions min typ max unit note md0 vcc = 2.5 v to 5.5 v ?0.3 ? 0.1 vcc ? 0.3 ? 0.2 vcc res, ic, irq0 to irq5 vcc = 2.5 v to 5.5 v ? 0.3 ? 0.1 vcc sck1, si1, rptrg, tmbi, adtrg ? 0.3 ? 0.2 vcc osc1 ? 0.3 ? 0.5 ? 0.3 ? 0.3 vcc p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p60 to p67, p70 to p77, p80 to p87 vcc = 2.5 v to 5.5 v ? 0.3 ? 0.2 vcc input low voltage v il csync ? 0.3 ? 0.2 vcc v ? i oh = 1.0 ma vcc ?1.0 ? ? v ? i oh = 0.5 ma ? vcc ?0.5 ? v refer- ence value output high voltage v oh so1, sck1, pwm0, pwm1, buzz, tmo, tmow, ppg0 to ppg7, rp0 to rp7, rp8 to rpb, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p60 to p67, p70 to p77, p80 to p87, sv1, sv2, r, g, b, yco, ybo ? i oh = 0.1 ma vcc = 2.5 v to 5.5 v vcc ?0.5 ? ? v section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 907 of 1174 rej09b0329-0200 values item symbol applicable pins test conditions min typ max unit note i ol =1.6 ma ? ? 0.6 v so1, sck1, pwm0, pwm1, buzz, tmo, tmow, ppg0 to ppg7, rp0 to rp7, rp8 to rpb, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p70 to p77, p80 to p87, sv1, sv2, r, g, b, yco, ybo i ol = 0.4 ma vcc = 2.5 v to 5.5 v ? ? 0.4 v i ol = 20 ma ? ? 1.7 v i ol = 1.6 ma ? ? 0.6 v output low voltage v ol p60 to p67, i ol = 0.4 ma vcc = 2.5 v to 5.5 v ? ? 0.4 v md0 vin = 0.5 to vcc ?0.5 v ? ? 1.0 res, irq0 to irq5, ic vin = 0.5 to vcc ?0.5 v ? ? 1.0 sck1, si1, sda1, scl1, trig, tmbi, adtrg vin = 0.5 to vcc ?0.5 v ? ? 1.0 osc1 vin = 0.5 to vcc ? 0.5 v ? ? 1.0 input/ output leakage current ? i il ? p10 to p17, p20 to p27, p30 to p37, p40 to p47, p60 to p67, p70 to p77, p80 to p87, vin = 0.5 to vcc ?0.5 v ? ? 1.0 a p00 to p07, an8 to anb vin = 0.5 to avcc ?0.5 v ? ? 1.0 section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 908 of 1174 rej09b0329-0200 values item symbol applicable pins test conditions min typ max unit note pull-up mos current ? ip p10 to p17, p20 to p27, p30 to p37 vcc = 5.0 v, vin = 0 v 50 ? 300 a * 2 input capacity cin all input pins except power supply pins p23 and p24, and analog pins fin = 1 mhz, vin = 0 v, ta = 25 c ? ? 15 pf p23 and p24 fin = 1 mhz, vin = 0 v, ta = 25 c ? ? 20 pf vcc = 5 v, f osc = 10 mhz, high-speed mode ? 40 50 ma * 3 * 4 active mode current dissipation (cpu operating) i ope vcc vcc = 5 v, f osc = 10 mhz, medium-speed mode (1/64) ? 25 ? ma reference value * 4 active mode current dissipation (reset) i res vcc vcc = 5 v, f osc = 10 mhz ? 12 15 ma * 3 * 4 sleep mode current dissipation i sleep vcc vcc = 5 v, f osc = 10 mhz high-speed mode ? 15 20 ma * 3 * 4 vcc = 2.5 v, 32 khz with crystal oscillator ( sub = w/2) ? 90 150 * 3 * 4 subactive mode current dissipation i sub vcc vcc = 2.5 v, 32 khz with crystal oscillator ( sub = w/8) ? 40 ? a reference value * 3 * 4 section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 909 of 1174 rej09b0329-0200 values item symbol applicable pins test conditions min typ max unit note subsleep mode current dissipation i subslp vcc vcc = 2.5 v, 32 khz with crystal oscillator ( sub = w/2) ? 30 50 a * 3 * 4 vcc = 2.5 v, 32 khz with crystal oscillator ( sub = w/8) ? 20 ? reference value * 3 * 4 vcc = 2.5 v, 32 khz with crystal oscillator ? 6 12 a * 3 * 4 watch mode current dissipation i watch vcc vcc = 5.0 v, 32 khz with crystal oscillator ? 12 ? a reference value * 3 * 4 standby mode current dissipation i stby vcc x1 = v cl , 32 khz without crystal oscillator ? ? 10 a * 3 * 4 ram data retaining voltage in standby mode v stby 2.0 v notes: 1. do not open the avcc and avss pin even when the a/d converter is not in use. 2. current value when the relevant bit of the pull-up mos select register (pur1 to pur3) is set to 1. 3. the current on the pull-up mos or the output buffer excluded. 4. excludes the current flowing in svcc and ovcc. section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 910 of 1174 rej09b0329-0200 table 31.13 pin status at cu rrent dissipation measurement mode res pin internal state pin oscillator pin active mode high-speed, medium- speed vcc operating vcc sleep mode high-speed, medium- speed vcc only cpu, servo circuits, and osd halted vcc reset vss reset vcc standby mode vcc all circuits halted vcc main clock: crystal oscillator sub clock: x1 pin = v cl subactive mode vcc only cpu and timer a operating vcc subsleep mode vcc only timer a operating vcc watch mode vcc only timer a operating vcc main clock: crystal oscillator sub clock: crystal oscillator table 31.14 bus drive characteristics of hd6432197s and hd6432196s ? preliminary ? (conditions: vcc = avcc = 4.0 v to 5.5 v, vss = 0.0 v, ta = ?20 to +75 c) applicable pin: scl1, sda1 values item symbo l applicable pins test conditions min typ max unit note v t ? 0.2 vcc ? ? v v t + ? ? 0.7 vcc v schmitt trigger input v t + ?v t ? scl1, sda1 0.05 vcc ? ? v input high level voltage v ih scl1, sda1 0.7 vcc ? vcc +0.5 v input low level voltage v il scl1, sda1 ? 0.5 ? 0.2 vcc v i ol = 8 ma ? ? 0.5 output low level voltage v ol scl1, sda1 i ol = 3 ma ? ? 0.4 v scl and sda output fall time t of scl1, sda1 20 + 0.1cb ? 250 ns section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 911 of 1174 rej09b0329-0200 31.3.2 allowable output currents of hd6432197s and hd6432196s the specifications for the digital pins are shown below. table 31.15 allowable output currents of hd6432197s and hd6432196s (conditions: vcc = 2.5 v to 5.5 v, vss = 0.0 v, ta = ?20 to +75 c) item symbol value unit note allowable input current (to chip) i o 2 ma 1 allowable input current (to chip) i o 22 ma 2 allowable input current (to chip) i o 10 ma 3 allowable output current (from chip) ? i o 2 ma 4 total allowable input current (to chip) i o 80 ma 5 total allowable output current (from chip) ? i o 50 ma 6 notes: 1. the allowable input current is the maximum value of the current flowing from each i/o pin to v ss (except for port 6, scl1 and sda1). 2. the allowable input current is the maximum value of the current flowing from each i/o pin to v ss . this applies to port 6. 3. the allowable input current is the maximum value of the current flowing from each i/o pin to v ss . this applies to scl1 and sda1. 4. the allowable output current is the maximum value of the current flowing from v cc to each i/o pin. 5. the total allowable input current is the sum of the currents flowing from all i/o pins to v ss simultaneously. 6. the total allowable output current is the sum of the currents flowing from v cc to all i/o pins. section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 912 of 1174 rej09b0329-0200 31.3.3 ac characteristics of hd6432197s and hd6432196s table 31.16 ac characteristics of hd6432197s and hd6432196s ? preliminary ? (conditions: vcc = avcc = 4.0 v to 5.5 v, vss = 0.0 v, ta = ?20 to +75 c unless otherwise specified, ovcc = svcc = 4.75 v to 5.25 v.) values item symbol applicable pins test conditions min typ max unit note clock oscillation frequency f osc osc1, osc2 8 ? 10 mhz clock cycle time t cyc osc1, osc2 100 ? 125 ns figure 31.9 subclock oscillation frequency f x x1, x2 vcc = 2.5 v to 5.5 v ? 32.768 ? khz subclock cycle time t subcyc x1, x2 vcc = 2.5 v to 5.5 v ? 30.518 ? s osc1, osc2 crystal oscillator ? ? 10 ms oscillation stabilization time t rc x1, x2 32-khz crystal oscillator (vcc = 2.5 v to 5.5 v) ? ? 2 s external clock high width t cph osc1 40 ? ? ns external clock low width t cpl osc1 40 ? ? ns external clock rise time t cpr osc1 ? ? 10 ns external clock fall time t cpf osc1 ? ? 10 ns figure 31.9 external clock stabilization delay time t dext osc1 500 ? ? s figure 31.10 res pin low level width t rel res vcc = 2.5 v to 5.5 v 20 ? ? t cyc figure 31.11 section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 913 of 1174 rej09b0329-0200 values item symbol applicable pins test conditions min typ max unit note input pin high level width t ih irq0 to irq5 , ic , adtrg , tmbi, rptrig vcc = 2.5 v to 5.5 v 2 ? ? t cyc t subcyc figure 31.12 input pin low level width t il irq0 to irq5 , ic , adtrg , tmbi, rptrig vcc = 2.5 v to 5.5 v 2 ? ? t cyc t subcyc t cyc t cph v il v ih osc1 t cpl t cpf t cpr figure 31.9 system clock timing section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 914 of 1174 rej09b0329-0200 vcc osc1 t dext * res (internal) 4.0v the t dext includes the res pin low level width 20 t cyc . note: * figure 31.10 external clock stabilization delay timing res v il t rel figure 31.11 reset input timing t il t ih v ih irq0 to irq5 , ic , adtrg , tmbi, rptrig v il figure 31.12 input timing section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 915 of 1174 rej09b0329-0200 31.3.4 serial interface timing of hd6432197s and hd6432196s table 31.17 serial interface timing of hd6432197s and hd6432196s ? preliminary ? (conditions: vcc = avcc = 4.0 v to 5.5 v, vss = 0.0 v, ta = ?20 to +75 c unless otherwise specified.) values item symbol applicable pins test conditions min typ max unit figure asynchronization 4 ? ? input clock cycle t scyc sck1 clock synchronization 6 ? ? t cyc input clock pulse width t sckw sck1 0.4 ? 0.6 t scyc input clock rise time t sckr sck1 ? ? 1.5 t cyc input clock fall time t sckf sck1 ? ? 1.5 t cyc figure 31.13 transmit data delay time (clock sync) t txd so1 ? ? 100 ns receive data setup time (clock sync) t rxs si1 100 ? ? ns receive data hold time (clock sync) t rxh si1 100 ? ? ns figure 31.14 t sckf t sckr v il or v ol v ih or v oh sck1 t sckw t scyc figure 31.13 sck1 clock timing section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 916 of 1174 rej09b0329-0200 v il v ih t txd sck1 so1 si1 t rxs t rxh v oh v ol figure 31.14 sci i/o timing/clock synchronization mode lsi output pin timin g reference level v oh : 2.0 v v ol : 0.8 v 30 pf 12 k 2.4 k vcc figure 31.15 output load conditions section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 917 of 1174 rej09b0329-0200 table 31.18 i 2 c bus interface timing of hd6432197s and hd6432196s ? preliminary ? (conditions: vcc = avcc = 4.0 v to 5.5 v, vss = 0.0 v, ta = ?20 to +75 c unless otherwise specified.) values item symbol test conditions min typ max unit figure scl input cycle time t scl 12 ? ? t cyc scl input high pulse width t sclh 3 ? ? t cyc scl input low pulse width t scll 5 ? ? t cyc scl, sda input rise time t sr ? ? 7.5 * t cyc scl, sda input fall time t sf ? ? 300 ns scl, sda input spike pulse removal time t sp ? ? 1 t cyc sda input bus free time t buf 5 ? ? t cyc start condition input hold time t stah 3 ? ? t cyc re-transmit start condition input setup time t stas 3 ? ? t cyc stop condition input setup time t stos 3 ? ? t cyc data input setup time t sdas 0.5 ? ? t cyc data input hold time t sdah 0 ? ? ns scl, sda capacity load c b ? ? 400 pf figure 31.16 note: * can also be set to 17.5 t cyc depending on the selection of clock to be used by the i 2 c module. section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 918 of 1174 rej09b0329-0200 t stah t sr t sdah t scl t scll t sclh t sf t stas t sp t stos t sdas v il v ih sda scl p * s * sr * p * s, p and sr denote the followin g : s : start conditions p : stop conditions sr: re-transmit start conditions note: * t buf figure 31.16 i 2 c bus interface i/o timing section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 919 of 1174 rej09b0329-0200 31.3.5 a/d converter characteristics of hd6432197s and hd6432196s table 31.19 a/d converter characteristics of hd6432197s and hd6432196s ? preliminary ? (conditions: vcc = avcc = 4.0 v to 5.5 v, vss = avss = 0.0 v, ta = ?20 to +75 c unless otherwise specified.) values item symbol applicable pins test conditions min typ max unit note analog power supply voltage avcc avcc vcc ? 0.3 vcc vcc +0.3 v analog input voltage a vin an0 to an7, an8 to anb avss ? avcc v a icc avcc avcc = 5.0 v ? ? 2.0 ma analog power supply current a istop avcc vcc = 2.5 v to 5.5 v at reset and in power-down mode ? ? 10 a analog input capacitance c ain an0 to an7, an8 to anb ? ? 30 pf allowable signal source impedance r ain an0 to an7, an8 to anb ? ? 10 k resolution ? ? 10 bit absolute accuracy vcc = avcc = 5.0 v ? ? 4 lsb vcc = avcc = 4.0 v to 5.0 v ? 4 ? lsb reference value conversion time 13.4 ? 26.6 s note: do not open the avcc and avss pin even when the a/d converter is not in use. set avcc = vcc and avss = vss. section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 920 of 1174 rej09b0329-0200 31.3.6 servo section electrical characteristics of hd6432197s and hd6432196s table 31.20 servo section electrical characteristics of hd6432197s and hd6432196s ? preliminary ? (conditions: vcc = svcc = 5.0 v, vss = svss = 0.0 v, ta = 25 c unless otherwise specified.) reference values item symbol applicable pins test conditions min typ max unit note ctlgr3 = 0, ctlgr2 = 0, ctlgr1 = 0, ctlgr0 = 0, f = 10 khz 32.0 34.0 36.0 ctlgr3 = 0, ctlgr2 = 0, ctlgr1 = 0, ctlgr0 = 1, f = 10 khz 34.5 36.5 38.5 ctlgr3 = 0, ctlgr2 = 0, ctlgr1 = 1, ctlgr0 = 0, f = 10 khz 37.0 39.0 41.0 ctlgr3 = 0, ctlgr2 = 0, ctlgr1 = 1, ctlgr0 = 1, f = 10 khz 39.5 41.5 43.5 ctlgr3 = 0, ctlgr2 = 1, ctlgr1 = 0, ctlgr0 = 0, f = 10 khz 42.0 44.0 46.0 ctlgr3 = 0, ctlgr2 = 1, ctlgr1 = 0, ctlgr0 = 1, f = 10 khz 44.5 46.5 48.5 ctlgr3 = 0, ctlgr2 = 1, ctlgr1 = 1, ctlgr0 = 0, f = 10 khz 47.0 49.0 51.0 ctlgr3 = 0, ctlgr2 = 1, ctlgr1 = 1, ctlgr0 = 1, f = 10 khz 49.5 51.5 53.5 ctlgr3 = 1, ctlgr2 = 0, ctlgr1 = 0, ctlgr0 = 0, f = 10 khz 52.0 54.0 56.0 ctlgr3 = 1, ctlgr2 = 0, ctlgr1 = 0, ctlgr0 = 1, f = 10 khz 54.5 56.5 58.5 ctlgr3 = 1, ctlgr2 = 0, ctlgr1 = 1, ctlgr0 = 0, f = 10 khz 57.0 59.0 61.0 ctlgr3 = 1, ctlgr2 = 0, ctlgr1 = 1, ctlgr0 = 1, f = 10 khz 59.5 61.5 63.5 ctlgr3 = 1, ctlgr2 = 1, ctlgr1 = 0, ctlgr0 = 0, f = 10 khz 62.0 64.0 66.0 ctlgr3 = 1, ctlgr2 = 1, ctlgr1 = 0, ctlgr0 = 1, f = 10 khz 64.5 66.5 68.5 ctlgr3 = 1, ctlgr2 = 1, ctlgr1 = 1, ctlgr0 = 0, f = 10 khz 67.0 69.0 71.0 pb-ctl input amplifier voltage gain ctl (+) ctlgr3 = 1, ctlgr2 = 1, ctlgr1 = 1, ctlgr0 = 1, f = 10 khz 69.5 71.5 73.5 db section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 921 of 1174 rej09b0329-0200 reference values item symbol applicable pins test conditions min typ max unit note v+th ac coupling, c = 0.1 f typ (non pol) ? 250 ? pb-ctl schmitt input v ? th ctlsmt (i) ac coupling, c = 0.1 f typ (non pol) ? ? 250 ? mvp analog switch on resistance reb ctlfb ? 150 ? ctl (+) ? 12 ? rec-ctl output current ictl ctl ( ? ) series resistance = 0 ? 12 ? ma rec-ctl pin-to- pin resistance rctl ? 10 ? k ctl reference output voltage ctlref ? 1/2 svcc ? v cfg pin bias voltage cfg ? 1/2 sv cc ? v cfg input level cfg ac coupling, c = 1 f typ, f = 1 khz 1.0 ? ? vpp cfg digital input high level v ih cfg when digital signal input method is selected (cfgcomp = 1) 0.8 vcc ? vcc +0.3 v cfg digital input v il cfg when digital signal input method is selected (cfgcomp = 1) ? 0.3 ? 0.2 vcc v cfg input impedance cfg ? 10 ? k v+thcf rise threshold level ? 2.25 ? cfg input threshold value v ? thcf cfg fall threshold level ? 2.75 ? v v+thdf rising edge schmitt level ? 1.95 ? dfg schmitt input v ? thdf dfg falling edge schmitt level ? 1.85 ? v v+thdp rising edge schmitt level ? 3.55 ? dpg schmitt input v ? thdp dpg falling edge schmitt level ? 3.45 ? v v oh ? i oh = 0.1 ma 4.0 ? ? v om no load, hi-z = 1 ? 2.5 ? 3-level output voltage v ol vpulse i ol = 0.1 ma ? ? 1.0 v 3-level output pin divided voltage resistance vpulse ? 15 ? k section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 922 of 1174 rej09b0329-0200 reference values item symbol applicable pins test conditions min typ max unit note digital input high level v ih 0.8 vcc ? vcc +0.3 digital input low level v il comp, exctl, excap, exttrg ? 0.3 ? 0.2 vcc v digital output high level v oh ? i oh = 1 ma vcc ?1.0 ? ? digital output low level v ol h.ampsw, c.rotary, videoff, audioff, drmpwm, cappwm, sv1, sv2 i ol = 1.6 ma ? ? 0.6 v current dissipation i ccsv svcc at no load ? 5 10 ma cfg duty cfg ac coupling, c = 1 f typ, f = 1 khz 48 ? 52 % section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 923 of 1174 rej09b0329-0200 31.3.7 osd electrical characteristics of hd6432197s and hd6432196s table 31.21 osd electrical characteristics of hd6432197s and hd6432196s (refernce values) ? preliminary ? (conditions: vcc = ovcc = 5.0 v, vss = ovss = 0.0 v, ta = 25 c unless otherwise specified) reference values item symbol applicable pins test conditions min typ max unit note composite video input voltage v cvin cv in1 cv in2 ? 2 v pp v cl1 cv in1 ? 1.2 1.4 1.6 clamp voltage v cl2 cv in2 ? 1.8 2 2.2 v c.video gain g cvc cv in1 cv out at chromathrough f = 3.58 mhz v in = 500 mvpp ? 3 ? 2 0 db pedestal bias v ped cv out 45 ire * 1 color burst bias v bst 40 ire * 1 v bl1 10 v bl2 30 v bl3 50 background bias black, blue, green, cyan, red, magenta, yellow, white v bl4 70 ire * 2 v kbl1 0 black v kbl2 25 v kol1 25 blue, green, cyan, red, magenta, yellow v kol2 45 v kcl1 45 cursor bias white v kcl2 55 ire * 2 section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 924 of 1174 rej09b0329-0200 reference values item symbol applicable pins test conditions min typ max unit note v cbl1 cv out 0 v cbl2 10 v cbl3 20 black v cbl4 30 v col1 25 v col2 45 v col3 55 blue, green, cyan, red, magenta, yellow v col4 65 v ccl1 45 v ccl2 70 v ccl3 80 character bias white v ccl4 90 ire * 2 v edg1 0 edge brightness level v edg2 90 ire * 2 v btn1 15 button brightness level v btn2 75 ire * 2 color burst amplitude v bsta 40 ire v cra1 60 chroma amplitude (background, cursor, character) blue, green, cyan, red, magenta, yellow v cra2 80 ire colorburst bstn 0 blue blun green grnn 7 /4 cyan cynn 3 /2 red redn /2 magenta mztn 3 /4 chroma hue angle (background, cursor, character) (ntsc) yellow yetn 0 rad * 3 section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 925 of 1174 rej09b0329-0200 reference values item symbol applicable pins test conditions min typ max unit note colorburst bstp cvout /4 blue blup green grnp 7 /4 cyan cynp 3 /2 red redp /2 magenta mztp 3 /4 chroma hue angle (background, cursor, character) (pal) yellow yelp 0 rad * 3 ccmp1 cvin2 ? 5 ? ccmp2 ? 10 ? ccmp3 ? 15 ? csync separation comparator ccmp4 ? 20 ? ire * 1 ecmp1 cvin2 ? 0 ? ecmp2 ? 5 ? ecmp3 ? 15 ? ecmp4 ? 20 ? ecmp5 ? 25 ? ecmp6 ? 35 ? eds separation comparator ecmp7 ? 40 ? ire * 2 v ih 0.85 ovcc ? ovcc +0.3 v input high level v iht csync/hsync v lpf /vsync 0.7 ovcc ? ovcc +0.3 v v il ? 0.3 ? 0.3 ovcc v input low level v ilt csync/hsync vlpf/vsync ? 0.3 ? 0.15 ovcc v output high level v oh csync/hsync ? i oh = 0.4 ma ovcc ? 1.4 ? ? v output low level v ol csync/hsync i ol = 0.4 ma ? ? 1.4 v section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 926 of 1174 rej09b0329-0200 reference values item symbol applicable pins test conditions min typ max unit note oscillation stabilizing time t rc 4/2fscin 4/2fscout crystal oscillator ? ? 40 ms m/ntsc ? 14.31818 ? mhz 4/2fscin 4/2fscout b, g, h/pal i/pal d, k/pal 4.43-ntsc b, g, h/secam l/secam d, k, k1/secam ? 17.734475 (17.734476) ? mhz n/pal ? 14.328225 ? mhz 4 fsc m/pal ? 14.30244596 ? mhz 2 fsc m/ntsc ? 7.15909 ? mhz 4/2fscin 4/2fscout b, g, h/pal i/pal d, k/pal 4.43-ntsc b, g, h/secam l/secam d, k, k2/secam ? 8.8672375 (8.867238) ? mhz n/pal ? 7.1641125 ? mhz oscillating frequency m/pal ? 7.15122298 ? mhz v fsc 4/2fscin 4/2fscout ac coupling c = 1 f typ 0.3 ? vcc +0.3 vpp v ih 4/2fscin 0.7 vcc ? vcc +0.3 external clock input level v il ? 0.3 ? 0.3 vcc v external clock duty 4/2fscin 4/2fscout 47 50 53 % 6.3 9 11.7 mhz afc reference clock (dot clock) afc osc afc osc lc oscillation 4.9 7 9.1 mhz current dissipation i ccosd ovcc at no signal ? 14 ? ma notes: ire: units for video amplitude; 0.714 v video level is specified as 100 ire 4fsc and 2fsc must be adjusted within 30 ppm, including temperature dependency. 1. bias from the sync tip clamp level (reference value after ? 6 db). 2. bias from the pedestal level (reference value after ? 6 db). 3. at 4fsc input. section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 927 of 1174 rej09b0329-0200 31.4 electrical characteristics of hd64f2199r 31.4.1 dc characteristics of hd64f2199r table 31.22 dc characteristics of hd64f2199r (conditions: vcc = avcc = 4.0 v to 5.5 v * 1 , vss = 0.0 v, ta = ?20 to +75 c unless otherwise specified.) values item symbol applicable pins test conditions min typ max unit note md0 vcc = 2.7 v to 5.5 v 0.9 vcc ? vcc +0.3 0.8 vcc ? vcc +0.3 res , fwe, ic , irq0 to irq5 , synci vcc = 2.7 v to 5.5 v 0.9 vcc ? vcc +0.3 sck1, si1, ftia, ftib, ftic, ftid, rptrg, tmbi, adtrg 0.8 vcc ? vcc +0.3 osc1 vcc ?0.5 ? vcc +0.3 0.7 vcc ? vcc +0.3 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p60 to p67, p70 to p77, p80 to p87 vcc = 2.7 v to 5.5 v 0.8 vcc ? vcc +0.3 input high voltage v ih csync 0.7 vcc ? vcc +0.3 v section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 928 of 1174 rej09b0329-0200 values item symbol applicable pins test conditions min typ max unit note md0 vcc = 2.7 v to 5.5 v ?0.3 ? 0.1 vcc ? 0.3 ? 0.2 vcc res , fwe, ic , irq0 to irq5 , synci vcc = 2.7 v to 5.5 v ? 0.3 ? 0.1 vcc sck1, si1, ftia, ftib, ftic, ftid, rptrg, tmbi, adtrg ? 0.3 ? 0.2 vcc osc1 ? 0.3 ? 0.5 ? 0.3 ? 0.3 vcc p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p60 to p67, p70 to p77, p80 to p87 vcc = 2.7 v to 5.5 v ? 0.3 ? 0.2 vcc input low voltage v il csync ? 0.3 ? 0.2 vcc v ? i oh = 1.0 ma vcc ?1.0 ? ? v ? i oh = 0.5 ma ? vcc ?0.5 ? v refer- ence value output high voltage v oh so1, sck1, pwm0, pwm1, pwm2, pwm3, pwm14, buzz, tmo, tmow, ftoa, ftob, ppg0 to ppg7, rp0 to rp7, rp8 to rpb, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p60 to p67, p70 to p77, p80 to p87, sv1, sv2, r, g, b, yco, ybo ? i oh = 0.1 ma vcc = 2.7 v to 5.5 v vcc ?0.5 ? ? v section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 929 of 1174 rej09b0329-0200 values item symbol applicable pins test conditions min typ max unit note i ol = 1.6 ma ? ? 0.6 v so1, sck1, pwm0, pwm1, pwm2, pwm3, pwm14, buzz, tmo, tmow, ftoa, ftob, ppg0 to ppg7, rp0 to rp7, rp8 to rpb, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p70 to p77, p80 to p87, sv1, sv2, r, g, b, yco, ybo i ol = 0.4 ma vcc = 2.7 v to 5.5 v ? ? 0.4 v i ol = 20 ma ? ? 1.7 v i ol = 1.6 ma ? ? 0.6 v output low voltage v ol p60 to p67, i ol = 0.4 ma vcc = 2.7 v to 5.5 v ? ? 0.4 v section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 930 of 1174 rej09b0329-0200 values item symbol applicable pins test conditions min typ max unit note md0, fwe vin = 0.5 to vcc ?0.5 v ? ? 1.0 res , irq0 to irq5 , ic vin = 0.5 to vcc ?0.5 v ? ? 1.0 sck1, si1, sda0, scl0, sda1, scl1, ftia, ftib, ftic, ftid, trig, tmbi, adtrg vin = 0.5 to vcc ?0.5 v ? ? 1.0 osc1 vin = 0.5 to vcc ?0.5 v ? ? 1.0 input/ output leakage current ? i il ? p10 to p17, p20 to p27, p30 to p37, p40 to p47, p60 to p67, p70 to p77, p80 to p87, vin = 0.5 to vcc ?0.5 v ? ? 1.0 a p00 to p07, an8 to anb vin = 0.5 to avcc ?0.5 v ? ? 1.0 pull-up mos current ? ip p10 to p17, p20 to p27, p30 to p37 vcc = 5.0 v, vin = 0 v 50 ? 300 a * 2 input capacity cin all input pins except power supply pins p23, p24, p25, and p26, and analog pins fin = 1 mhz, vin = 0 v, ta = 25 c ? ? 15 pf p23, p24, p25, p26 fin = 1 mhz, vin = 0 v, ta = 25 c ? ? 20 pf section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 931 of 1174 rej09b0329-0200 values item symbol applicable pins test conditions min typ max unit note vcc = 5 v, f osc = 10 mhz, high-speed mode ? 40 50 ma * 3 * 4 active mode current dissipation (cpu operating) i ope vcc vcc = 5 v, f osc = 10 mhz, medium-speed mode (1/64) ? 25 ? ma reference value * 3 * 4 active mode current dissipation (reset) i res vcc vcc = 5 v, f osc = 10 mhz ? 12 15 ma * 3 * 4 sleep mode current dissipation i sleep vcc vcc = 5 v, f osc = 10 mhz high-speed mode ? 15 20 ma * 3 * 4 vcc = 2.7 v, 32 khz with crystal oscillator ( sub = w/2) ? 90 150 * 3 * 4 subactive mode current dissipation i sub vcc vcc = 2.7 v, 32 khz with crystal oscillator ( sub = w/8) ? 40 ? a reference value * 3 * 4 vcc = 2.7 v, 32 khz with crystal oscillator ( sub = w/2) ? 30 50 * 3 * 4 subsleep mode current dissipation i subslp vcc vcc = 2.7 v, 32 khz with crystal oscillator ( sub = w/8) ? 20 ? a reference value * 3 * 4 vcc = 2.7 v, 32 khz with crystal oscillator ? 6 12 a * 3 * 4 watch mode current dissipation i watch vcc vcc = 5.0 v, 32 khz with crystal oscillator ? 12 ? a reference value * 3 * 4 standby mode current dissipation i stby vcc x1 = v cl , 32 khz without crystal oscillator ? ? 10 a * 3 * 4 section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 932 of 1174 rej09b0329-0200 values item symbol applicable pins test conditions min typ max unit note ram data retaining voltage in standby mode v stby 2.0 v notes: 1. do not open the avcc and avss pin even when the a/d converter is not in use. 2. current value when the relevant bit of the pull-up mos select register (pur1 to pur3) is set to 1. 3. the current on the pull-up mos or the output buffer excluded. 4. excludes the current flowing in svcc and ovcc. table 31.23 pin status at cu rrent dissipation measurement mode res pin internal state pin oscillator pin active mode high-speed, medium- speed vcc operating vcc sleep mode high-speed, medium- speed vcc only cpu, servo circuits, and osd halted vcc reset vss reset vcc standby mode vcc all circuits halted vcc main clock: crystal oscillator sub clock: x1 pin = v cl subactive mode vcc cpu and timer a operating vcc subsleep mode vcc timer a operating vcc watch mode vcc timer a operating vcc main clock: crystal oscillator sub clock: crystal oscillator section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 933 of 1174 rej09b0329-0200 table 31.24 bus drive characteristics of hd64f2199r (conditions: vcc = avcc = 4.0 v to 5.5 v, vss = 0.0 v, ta = ?20 to +75 c.) applicable pin: scl0 , scl1, sda0, sda1 values item symbol applicable pins test conditions min typ max unit note v t ? 0.2 vcc ? ? v v t + ? ? 0.7 vcc v schmitt trigger input v t + ?v t ? scl0, sda0, scl1, sda1 0.05 vcc ? ? v input high level voltage v ih scl0, sda0, scl1, sda1 0.7 vcc ? vcc +0.5 v input low level voltage v il scl0, sda0, scl1, sda1 ? 0.5 ? 0.2 vcc v i ol = 8 ma ? ? 0.5 output low level voltage v ol scl0, sda0, scl1, sda1 i ol = 3 ma ? ? 0.4 v scl and sda output fall time t of scl0, sda0, scl1, sda1 20 + 0.1cb ? 250 ns section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 934 of 1174 rej09b0329-0200 31.4.2 allowable output currents of hd64f2199r the specifications for the digital pins are shown below. table 31.25 allowable out put currents of hd64f2199r (conditions: vcc = 2.7 v to 5.5 v, vss = 0.0 v, ta = ?20 to +75 c) item symbol value unit note allowable input current (to chip) i o 2 ma * 1 allowable input current (to chip) i o 22 ma * 2 allowable input current (to chip) i o 10 ma * 3 allowable output current (from chip) ? i o 2 ma * 4 total allowable input current (to chip) i o 80 ma * 5 total allowable output current (from chip) ? i o 50 ma * 6 notes: 1. the allowable input current is the maximum value of the current flowing from each i/o pin to v ss (except for port 6, scl0, sda0, scl1, and sda1). 2. the allowable input current is the maximum value of the current flowing from each i/o pin to v ss . this applies to port 6. 3. the allowable input current is the maximum value of the current flowing from each i/o pin to v ss . this applies to scl0, sda0, scl1, and sda1. 4. the allowable output current is the maximum value of the current flowing from v cc to each i/o pin. 5. the total allowable input current is the sum of the currents flowing from all i/o pins to v ss simultaneously. 6. the total allowable output current is the sum of the currents flowing from v cc to all i/o pins. section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 935 of 1174 rej09b0329-0200 31.4.3 ac characteristics of hd64f2199r table 31.26 ac characteristics of hd64f2199r (conditions: vcc = avcc = 4.0 v to 5.5 v, vss = 0.0 v, ta = ?20 to +75 c unless otherwise specified, ovcc = svcc = 4.75 v to 5.25 v.) values item symbol applicable pins test conditions min typ max unit note clock oscillation frequency f osc osc1, osc2 8 ? 10 mh z clock cycle time t cyc osc1, osc2 100 ? 125 ns figure 31.17 subclock oscillation frequency f x x1, x2 vcc = 2.7 v to 5.5 v ? 32.768 ? khz subclock cycle time t subcyc x1, x2 vcc = 2.7 v to 5.5 v ? 30.518 ? s osc1, osc2 crystal oscillator ? ? 10 ms oscillation stabilization time t rc x1, x2 32 khz crystal oscillator (vcc = 2.7 v to 5.5 v) ? ? 2 s external clock high width t cph osc1 40 ? ? ns external clock low width t cpl osc1 40 ? ? ns external clock rise time t cpr osc1 ? ? 10 ns external clock fall time t cpf osc1 ? ? 10 ns figure 31.17 external clock stabilization delay time t dext osc1 500 ? ? s figure 31.18 res pin low level width t rel res vcc = 2.7 v to 5.5 v 20 ? ? t cyc figure 31.19 section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 936 of 1174 rej09b0329-0200 values item symbol applicable pins test conditions min typ max unit note input pin high level width t ih irq0 to irq5 , ic , adtrg , tmbi, ftia, ftib, ftic, ftid, rptrig vcc = 2.7 v to 5.5 v 2 ? ? t cyc t subcyc figure 31.20 input pin low level width t il irq0 to irq5 , ic , adtrg , tmbi, ftia, ftib, ftic, ftid, rptrig vcc = 2.7 v to 5.5 v 2 ? ? t cyc t subcyc t cyc t cph v il v ih osc1 t cpl t cpf t cpr figure 31.17 system clock timing section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 937 of 1174 rej09b0329-0200 vcc osc1 t dext * res (internal) 4.0v the t dext includes the res pin low level width 20 t cyc . note: * figure 31.18 external clock stabilization delay timing res v il t rel figure 31.19 reset input timing t il t ih v ih v il irq0 to irq5 , ic , adtrg , tmbi, ftia, ftib, ftic, ftid, rptrig figure 31.20 input timing section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 938 of 1174 rej09b0329-0200 31.4.4 serial interface timing of hd64f2199r table 31.27 serial interface timing of hd64f2199r (conditions: vcc = avcc = 4.0 v to 5.5 v, vss = 0.0 v, ta = ?20 to +75 c unless otherwise specified.) values item symbol applicable pins test conditions min typ max unit figure asynchronization 4 ? ? input clock cycle t scyc sck1 clock synchronization 6 ? ? t cyc input clock pulse width t sckw sck1 0.4 ? 0.6 t scyc input clock rise time t sckr sck1 ? ? 1.5 t cyc input clock fall time t sckf sck1 ? ? 1.5 t cyc figure 31.21 transmit data delay time (clock sync) t txd so1 ? ? 100 ns figure 31.22 receive data setup time (clock sync) t rxs si1 100 ? ? ns receive data hold time (clock sync) t rxh si1 100 ? ? ns t sckf t sckr v il or v ol v ih or v oh sck1 t sckw t scyc figure 31.21 sck1 clock timing section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 939 of 1174 rej09b0329-0200 v il v ih t txd sck1 so1 si1 t rxs t rxh v oh v ol figure 31.22 sci i/o timing/clock synchronization mode lsi output pin timing reference level v oh : 2.0 v v ol : 0.8 v 30 pf 12 k 2.4 k vcc figure 31.23 output load conditions section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 940 of 1174 rej09b0329-0200 table 31.28 i 2 c bus interface timing of hd64f2199r (conditions: vcc = avcc = 4.0 v to 5.5 v, vss = 0.0 v, ta = ?20 to +75 c unless otherwise specified.) values item symbol test conditions min typ max unit figure scl input cycle time t scl 12 ? ? t cyc scl input high pulse width t sclh 3 ? ? t cyc scl input low pulse width t scll 5 ? ? t cyc scl, sda input rise time t sr ? ? 7.5 * t cyc scl, sda input fall time t sf ? ? 300 ns scl, sda input spike pulse removal time t sp ? ? 1 t cyc sda input bus free time t buf 5 ? ? t cyc start condition input hold time t stah 3 ? ? t cyc re-transmit start condition input setup time t stas 3 ? ? t cyc stop condition input setup time t stos 3 ? ? t cyc data input setup time t sdas 0.5 ? ? t cyc data input hold time t sdah 0 ? ? ns scl, sda capacity load c b ? ? 400 pf figure 31.24 note: can also be set to 17.5 t cyc depending on the selection of clock to be used by the i 2 c module. section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 941 of 1174 rej09b0329-0200 t stah t sr t sdah t scl t scll t sclh t sf t stas t sp t stos t sdas v il v ih sda scl p * s * sr * p * s, p and sr denote the following: s : start conditions p : stop conditions sr: re-transmit start conditions note: * t buf figure 31.24 i 2 c bus interface i/o timing section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 942 of 1174 rej09b0329-0200 31.4.5 a/d converter characteristics of hd64f2199r table 31.29 a/d converter characteristics of hd64f2199r (conditions: vcc = avcc = 4.0 v to 5.5 v, vss = avss = 0.0 v, ta = ?20 to +75 c unless otherwise specified.) values item symbol applicable pins test conditions min typ max unit note analog power supply voltage avcc avcc vcc ? 0.3 vcc vcc +0.3 v analog input voltage a vin an0 to an7, an8 to anb avss ? avcc v a icc avcc avcc = 5.0 v ? ? 2.0 ma analog power supply current a istop avcc vcc = 2.7 v to 5.5 v at reset and in power-down mode ? ? 10 a analog input capacitance c ain an0 to an7, an8 to anb ? ? 30 pf allowable signal source impedance r ain an0 to an7, an8 to anb ? ? 10 k resolution ? ? 10 bit absolute accuracy vcc = avcc = 5.0 v ? ? 4 lsb vcc = avcc = 4.0 v to 5.0 v ? 4 ? lsb reference value conversion time 13.4 ? 26.6 s note: do not open the avcc and avss pin even when the a/d converter is not in use. set avcc = vcc and avss = vss. section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 943 of 1174 rej09b0329-0200 31.4.6 servo section electrical characteristics of hd64f2199r table 31.30 servo section electrical charac teristics of hd64f2199r (reference values) (conditions: vcc = svcc = 5.0 v, vss = svss = 0.0 v, ta = 25 c unless otherwise specified.) reference values item symbol applicable pins test conditions min typ max unit note ctlgr3 = 0, ctlgr2 = 0, ctlgr1 = 0, ctlgr0 = 0, f = 10 khz 32.0 34.0 36.0 ctlgr3 = 0, ctlgr2 = 0, ctlgr1 = 0, ctlgr0 = 1, f = 10 khz 34.5 36.5 38.5 ctlgr3 = 0, ctlgr2 = 0, ctlgr1 = 1, ctlgr0 = 0, f = 10 khz 37.0 39.0 41.0 ctlgr3 = 0, ctlgr2 = 0, ctlgr1 = 1, ctlgr0 = 1, f = 10 khz 39.5 41.5 43.5 ctlgr3 = 0, ctlgr2 = 1, ctlgr1 = 0, ctlgr0 = 0, f = 10 khz 42.0 44.0 46.0 ctlgr3 = 0, ctlgr2 = 1, ctlgr1 = 0, ctlgr0 = 1, f = 10 khz 44.5 46.5 48.5 ctlgr3 = 0, ctlgr2 = 1, ctlgr1 = 1, ctlgr0 = 0, f = 10 khz 47.0 49.0 51.0 ctlgr3 = 0, ctlgr2 = 1, ctlgr1 = 1, ctlgr0 = 1, f = 10 khz 49.5 51.5 53.5 ctlgr3 = 1, ctlgr2 = 0, ctlgr1 = 0, ctlgr0 = 0, f = 10 khz 52.0 54.0 56.0 ctlgr3 = 1, ctlgr2 = 0, ctlgr1 = 0, ctlgr0 = 1, f = 10 khz 54.5 56.5 58.5 ctlgr3 = 1, ctlgr2 = 0, ctlgr1 = 1, ctlgr0 = 0, f = 10 khz 57.0 59.0 61.0 ctlgr3 = 1, ctlgr2 = 0, ctlgr1 = 1, ctlgr0 = 1, f = 10 khz 59.5 61.5 63.5 ctlgr3 = 1, ctlgr2 = 1, ctlgr1 = 0, ctlgr0 = 0, f = 10 khz 62.0 64.0 66.0 ctlgr3 = 1, ctlgr2 = 1, ctlgr1 = 0, ctlgr0 = 1, f = 10 khz 64.5 66.5 68.5 ctlgr3 = 1, ctlgr2 = 1, ctlgr1 = 1, ctlgr0 = 0, f = 10 khz 67.0 69.0 71.0 pb-ctl input amplifier voltage gain ctl (+) ctlgr3 = 1, ctlgr2 = 1, ctlgr1 = 1, ctlgr0 = 1, f = 10 khz 69.5 71.5 73.5 db section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 944 of 1174 rej09b0329-0200 reference values item symbol applicable pins test conditions min typ max unit note v+th ac coupling, c = 0.1 f typ (non pol) ? 250 ? pb-ctl schmitt input v ? th ctlsmt (i) ac coupling, c = 0.1 f typ (non pol) ? ? 250 ? mvp analog switch on resistance reb ctlfb ? 150 ? ctl (+) ? 12 ? rec-ctl output current ictl ctl ( ? ) series resistance = 0 ? 12 ? ma rec-ctl pin-to- pin resistance rctl ? 10 ? k ctl reference output voltage ctlref ? 1/2 svcc ? v cfg pin bias voltage cfg ? 1/2 sv cc ? v cfg input level cfg ac coupling, c = 1 f typ, f = 1 khz 1.0 ? ? vpp cfg digital input high level v ih cfg when digital signal input method is selected (cfgcomp = 1) 0.8 vcc ? vcc +0.3 v cfg digital input v il cfg when digital signal input method is selected (cfgcomp = 1) ? 0.3 ? 0.2 vcc v cfg input impedance cfg ? 10 ? k v+thcf rise threshold level ? 2.25 ? cfg input threshold value v ? thcf cfg fall threshold level ? 2.75 ? v v+thdf rising edge schmitt level ? 1.95 ? dfg schmitt input v ? thdf dfg falling edge schmitt level ? 1.85 ? v v+thdp rising edge schmitt level ? 3.55 ? dpg schmitt input v ? thdp dpg falling edge schmitt level ? 3.45 ? v v oh ? i oh = 0.1 ma 4.0 ? ? v om no load, hi-z = 1 ? 2.5 ? 3-level output voltage v ol vpulse i ol = 0.1 ma ? ? 1.0 v 3-level output pin divided voltage resistance vpulse ? 15 ? k digital input high level v ih 0.8 vcc ? vcc +0.3 digital input low level v il comp, exctl, excap, exttrg ? 0.3 ? 0.2 vcc v section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 945 of 1174 rej09b0329-0200 reference values item symbol applicable pins test conditions min typ max unit note digital output high level v oh ? i oh = 1 ma vcc ?1.0 ? ? digital output low level v ol h.ampsw, c.rotary, videoff, audioff, drmpwm, cappwm, sv1, sv2 i ol = 1.6 ma ? ? 0.6 v current dissipation i ccsv svcc at no load ? 5 10 ma cfg duty cfg ac coupling, c = 1 f typ, f = 1 khz 48 ? 52 % section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 946 of 1174 rej09b0329-0200 31.4.7 osd electrical characteristics of hd64f2199r table 31.31 osd electrical characteristics of hd64f2199r (reference value) (conditions: vcc = ovcc = 5.0 v, vss = ovss = 0.0 v, ta = 25 c unless otherwise specified) reference values item symbol applicable pins test conditions min typ max unit note composite video input voltage v cvin cv in1 cv in2 ? 2 v pp v cl1 cv in1 ? 1.2 1.4 1.6 clamp voltage v cl2 cv in2 ? 1.8 2 2.2 v c.video gain g cvc cv in1 cv out at chromathrough f = 3.58 mhz v in = 500 mvpp ? 3 ? 2 0 db pedestal bias v ped cv out 45 ire * 1 color burst bias v bst 40 ire * 1 v bl1 10 v bl2 30 v bl3 50 background bias black, blue, green, cyan, red, magenta, yellow, white v bl4 70 ire * 2 v kbl1 0 black v kbl2 25 v kol1 25 blue, green, cyan, red, magenta, yellow v kol2 45 v kcl1 45 cursor bias white v kcl2 55 ire * 2 section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 947 of 1174 rej09b0329-0200 reference values item symbol applicable pins test conditions min typ max unit note v cbl1 cv out 0 v cbl2 10 v cbl3 20 black v cbl4 30 v col1 25 v col2 45 v col3 55 blue, green, cyan, red, magenta, yellow v col4 65 v ccl1 45 v ccl2 70 v ccl3 80 character bias white v ccl4 90 ire * 2 v edg1 0 edge brightness level v edg2 90 ire * 2 v btn1 15 button brightness level v btn2 75 ire * 2 color burst amplitude v bsta 40 ire v cra1 60 chroma amplitude (background, cursor, character) blue, green, cyan, red, magenta, yellow v cra2 80 ire colorburst bstn 0 blue blun green grnn 7 /4 cyan cynn 3 /2 red redn /2 magenta mztn 3 /4 chroma hue angle (background, cursor, character) (ntsc) yellow yetn 0 rad * 3 section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 948 of 1174 rej09b0329-0200 reference values item symbol applicable pins test conditions min typ max unit note colorburst bstp cvout /4 blue blup green grnp 7 /4 cyan cynp 3 /2 red redp /2 magenta mztp 3 /4 chroma hue angle (background, cursor, character) (pal) yellow yelp 0 rad * 3 ccmp1 cvin2 ? 5 ? ccmp2 ? 10 ? ccmp3 ? 15 ? csync separation comparator ccmp4 ? 20 ? ire * 1 ecmp1 cvin2 ? 0 ? ecmp2 ? 5 ? ecmp3 ? 15 ? ecmp4 ? 20 ? ecmp5 ? 25 ? ecmp6 ? 35 ? eds separation comparator ecmp7 ? 40 ? ire * 2 v ih 0.85 ovcc ? ovcc +0.3 v input high level v iht csync/hsync v lpf /vsync 0.7 ovcc ? ovcc +0.3 v v il ? 0.3 ? 0.3 ovcc v input low level v ilt csync/hsync vlpf/vsync ? 0.3 ? 0.15 ovcc v output high level v oh csync/hsync ? i oh = 0.4 ma ovcc ? 1.4 ? ? v output low level v ol csync/hsync i ol = 0.4 ma ? ? 1.4 v oscillation stabilizing time t rc 4/2fscin 4/2fscout crystal oscillator ? ? 40 ms section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 949 of 1174 rej09b0329-0200 reference values item symbol applicable pins test conditions min typ max unit note m/ntsc ? 14.31818 ? mhz 4/2fscin 4/2fscout b, g, h/pal i/pal d, k/pal 4.43-ntsc b, g, h/secam l/secam d, k, k1/secam ? 17.734475 (17.734476) ? mhz n/pal ? 14.328225 ? mhz 4 fsc m/pal ? 14.30244596 ? mhz 2 fsc m/ntsc ? 7.15909 ? mhz 4/2fscin 4/2fscout b, g, h/pal i/pal d, k/pal 4.43-ntsc b, g, h/secam l/secam d, k, k2/secam ? 8.8672375 (8.867238) ? mhz n/pal ? 7.1641125 ? mhz oscillating frequency m/pal ? 7.15122298 ? mhz v fsc 4/2fscin 4/2fscout ac coupling c = 1 f typ 0.3 ? vcc +0.3 vpp v ih 4/2fscin 0.7 vcc ? vcc +0.3 external clock input level v il ? 0.3 ? 0.3 vcc v external clock duty 4/2fscin 4/2fscout 47 50 53 % 6.3 9 11.7 mhz afc reference clock (dot clock) afc osc afc osc lc oscillation 4.9 7 9.1 mhz current dissipation i ccosd ovcc at no signal ? 14 ? ma notes: ire: units for video amplitude; 0.714 v video level is specified as 100 ire 4fsc and 2fsc must be adjusted within 30 ppm, including temperature dependency. 1. bias from the sync tip clamp level (reference value after ? 6 db). 2. bias from the pedestal level (reference value after ? 6 db). 3. at 4fsc input. section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 950 of 1174 rej09b0329-0200 31.4.8 flash memory characteristics table 31.32 flash memory characteristics conditions: v cc = av cc = 4.5 v to 5.5 v, v ss = av ss = 0 v, t a = 0c to +75c (program/erase operating temperature range) item symbol min typ max unit note programming time * 1 * 2 * 4 t p ? 10 200 ms/128 bytes erase time * 1 * 3 * 5 t e ? 100 1200 ms/block reprogramming count n wec 100 * 8 10000 * 9 ? times data retention time * 10 t drp 10 ? ? years programming wait time after swe1 (2) bit setting * 1 t sswe 1 1 ? s wait time after psu1 (2) bit setting * 1 t spsu 50 50 ? s wait time after p1 (2) bit setting * 1 * 4 t sp30 28 30 32 s programming time wait t sp200 198 200 202 s programming time wait t sp10 8 10 12 s additional- programming time wait wait time after p1 (2) bit clearing * 1 t cp 5 5 ? s wait time after psu1 (2) bit clearing * 1 t cpsu 5 5 ? s wait time after pv1 (2) bit setting * 1 t spv 4 4 ? s wait time after h'ff dummy write * 1 t spvr 2 2 ? s wait time after pv1 (2) bit clearing * 1 t cpv 2 2 ? s wait time after swe1 (2) bit clearing * 1 t cswe 100 100 ? s maximum number of writes * 1 * 4 n ? ? 1000 times section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 951 of 1174 rej09b0329-0200 item symbol min typ max unit note erasing wait time after swe1 (2) bit setting * 1 t sswe 1 1 ? s wait time after esu1 (2) bit setting * 1 t sesu 100 100 ? s wait time after e1 (2) bit setting * 1 * 5 t se 10 10 100 ms erase time wait wait time after e1 (2) bit clearing * 1 t ce 10 10 ? s wait time after esu1 (2) bit clearing * 1 t cesu 10 10 ? s wait time after ev1 (2) bit setting * 1 t sev 20 20 ? s wait time after h'ff dummy write * 1 t sevr 2 2 ? s wait time after ev1 (2) bit clearing * 1 t cev 4 4 ? s wait time after swe1 (2) bit clearing * 1 t cswe 100 100 ? s maximum number of erases * 1 * 5 n 12 ? 120 times notes: 1. follow the program/erase algorithms when making the time settings. 2. programming time per 128 bytes. (indicates the total time during which the p1 (2) bit is set in flash memory control register 1 (flmcr1 (2)). does not include the program- verify time.) 3. time to erase one block. (indicates the time during which the e1 (2) bit is set in flmcr1 (2). does not include the erase-verify time.) 4. to specify the maximum programming time value (t p (max)) in the 128-byte programming algorithm, set the max. value (1000) for the maximum number of writes (n). the wait time after p1(2) bit setting should be changed as follows according to the value of the programming counter (n). programming counter (n) = 1 to 6: t sp30 = 30 s programming counter (n) = 7 to 1000: t sp200 = 200 s programming counter (n) [in additional programming] = 1 to 6: t sp10 = 10 s 5. for the maximum erase time (t e ) max), the following relationship applies between the wait time after e1 (2) bit setting (t se ) and the maximum number of erase (n): (t e (max) = wait time after e1 (2) bit setting (t se ) maximum number of erases (n)) to specify the maximum erase time, the values of t se and n should be set so as to satisfy the above formula. section 31 electrical characteristics rev.2.00 jan. 15, 2007 page 952 of 1174 rej09b0329-0200 examples: when t se = 100 [ms], n = 12 when t se = 10 [ms], n = 120 6. minimum number of times for which all ch aracteristics are guaranteed after rewriting (guarantee range is 1 to minimum value). 7. reference value for 25 c (as a guideline, rewriting should normally function up to this value). 8. data retention characteristic when rewriting is performed within the specification range, including the minimum value. appendix a instruction set rev.2.00 jan. 15, 2007 page 953 of 1174 rej09b0329-0200 appendix a instruction set a.1 instructions operation notation rd general register (destination) * 1 rs general register (source) * 1 rn general register * 1 ern general register (32-bit register) mac multiplication-addition register (32-bit register) * 2 (ead) destination operand (eas) source operand exr extend register ccr condition code register n n (negative flag) in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition ? subtraction multiplication division logical and logical or exclusive logical or move from the left to the right logical complement ( ) <> contents of operand :8/:16/:24/:32 8-, 16-, 24-, 32-bit length notes: 1. general register is 8-bit (r0h to r7h, r0l to r7l), 16-bit (r0 to r7) or 32-bit (er0 to er7). 2. mac register cannot be used in this lsi. appendix a instruction set rev.2.00 jan. 15, 2007 page 954 of 1174 rej09b0329-0200 condition code notation symbol description modified according to the instruction result * not fixed (value not guaranteed) 0 always cleared to 0 1 always set to 1 ? not affected by the instruction execution result appendix a instruction set rev.2.00 jan. 15, 2007 page 955 of 1174 rej09b0329-0200 table a.1 data transfer instruction mov.b #xx:8,rd mov.b rs,rd mov.b @ers,rd mov.b @(d:16,ers),rd mov.b @(d:32,ers),rd mov.b @ers+,rd mov.b @aa:8,rd mov.b @aa:16,rd mov.b @aa:32,rd mov.b rs,@erd mov.b rs,@(d:16,erd) mov.b rs,@(d:32,erd) mov.b rs,@-erd mov.b rs,@aa:8 mov.b rs,@aa:16 mov.b rs,@aa:32 mov.w #xx:16,rd mov.w rs,rd mov.w @ers,rd mov.w @(d:16,ers),rd mov.w @(d:32,ers),rd mov.w @ers+,rd mov.w @aa:16,rd mov.w @aa:32,rd mov.w rs,@erd mov.w rs,@(d:16,erd) mov.w rs,@(d:32,erd) mov.w rs,@-erd mov.w rs,@aa:16 mov.w rs,@aa:32 mov.l #xx:32,erd mov.l ers,erd mov.l @ers,erd mov.l @(d:16,ers),erd mov.l @(d:32,ers),erd mov.l @ers+,erd mov.l @aa:16,erd mov.l @aa:32,erd mov.l ers,@erd mov.l ers,@(d:16,erd) mov.l ers,@(d:32,erd) mov.l ers,@-erd mov.l ers,@aa:16 mov.l ers,@aa:32 pop.w rn pop.l ern push.w rn push.l ern ldm @sp+,(erm-ern) stm (erm-ern),@-sp movfpe @aa:16,rd movtpe rs,@aa:16 b b b b b b b b b b b b b b b b w w w w w w w w w w w w w w l l l l l l l l l l l l l l w l w l l l 2 4 6 2 2 2 2 2 2 2 4 4 4 8 4 8 4 8 4 8 6 10 6 10 2 2 2 2 4 4 2 4 6 2 4 6 4 6 4 6 6 8 6 8 mov pop push ldm * 4 stm * 4 movfpe movtpe mnemonic size addressin g mode and instruction len g th (bytes) #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa #xx:8 rd8 rs8 rd8 @ers rd8 @(d:16,ers) rd8 @(d:32,ers) rd8 @ers rd8,ers32+1 ers32 @aa:8 rd8 @aa:16 rd8 @aa:32 rd8 rs8 @erd rs8 @(d:16,erd) rs8 @(d:32,erd) erd32-1 erd32,rs8 @erd rs8 @aa:8 rs8 @aa:16 rs8 @aa:32 #xx:16 rd16 rs16 rd16 @ers rd16 @(d:16,ers) rd16 @(d:32,ers) rd16 @ers rd16,ers32+2 ers32 @aa:16 rd16 @aa:32 rd16 rs16 @erd rs16 @(d:16,erd) rs16 @(d:32,erd) erd32-2 erd32,rs16 @erd rs16 @aa:16 rs16 @aa:32 #xx:32 erd32 ers32 erd32 @ers erd32 @(d:16,ers) erd32 @(d:32,ers) erd32 @ers erd32,ers32+4 ers32 @aa:16 erd32 @aa:32 erd32 ers32 @erd ers32 @(d:16,erd) ers32 @(d:32,erd) erd32-4 erd32,ers32 @erd ers32 @aa:16 ers32 @aa:32 @sp rn16,sp+2 sp @sp ern32,sp+4 sp sp-2 sp,rn16 @sp sp-4 sp,ern32 @sp (@sp ern32,sp+4 sp) repeat for the number of returns (sp-4 sp,ern32 @sp) repeat for the number of returns operation condition code no of execution states * 1 i hn zvc advanced mode 2 4 2 4 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? 1 1 2 3 5 3 2 3 4 2 3 5 3 2 3 4 2 1 2 3 5 3 3 4 2 3 5 3 3 4 3 1 4 5 7 5 5 6 4 5 7 5 5 6 3 5 3 5 7/9/11 [1] 7/9/11 [1] [2] [2] ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cannot be used in this lsi ? ? ? ? ? appendix a instruction set rev.2.00 jan. 15, 2007 page 956 of 1174 rej09b0329-0200 table a.2 arithmetic instructions add.b #xx:8,rd add.b rs,rd add.w #xx:16,rd add.w rs,rd add.l #xx:32,erd add.l ers,erd addx #xx:8,rd addx rs,rd adds #1,erd adds #2,erd adds #4,erd inc.b rd inc.w #1,rd inc.w #2,rd inc.l #1,erd inc.l #2,erd daa rd sub.b rs,rd sub.w #xx:16,rd sub.w rs,rd sub.l #xx:32,erd sub.l ers,erd subx #xx:8,rd subx rs,rd subs #1,erd subs #2,erd subs #4,erd dec.b rd dec.w #1,rd dec.w #2,rd dec.l #1,erd dec.l #2,erd das rd mulxu.b rs,rd mulxu.w rs,erd mulxs.b rs,rd mulxs.w rs,erd divxu.b rs,rd divxu.w rs,erd divxs.b rs,rd divxs.w rs,erd cmp.b #xx:8,rd cmp.b rs,rd cmp.w #xx:16,rd cmp.w rs,rd cmp.l #xx:32,erd cmp.l ers,erd neg.b rd neg.w rd neg.l erd extu.w rd extu.l erd exts.w rd exts.l erd tas @erd * 2 mac @ern+,@erm+ clrmac ldmac ers,mach ldmac ers,macl stmac mach,erd stmac macl,erd b b w w l l b b l l l b w w l l b b w w l l b b l l l b w w l l b b w b w b w b w b b w w l l b w l w l w l b 2 4 6 2 4 6 2 2 4 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 2 2 4 4 2 2 2 2 2 2 2 2 2 2 add addx adds inc daa sub subx subs dec das mulxu mulxs divxu divxs cmp neg extu exts tas mac clrmac ldmac stmac mnemonic size #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ? rd8+#xx:8 rd8 rd8+rs8 rd8 rd16+#xx:16 rd16 rd16+rs16 rd16 erd32+#xx:32 erd32 erd32+ers32 erd32 rd8+#xx:8+c rd8 rd8+rs8+c rd8 erd32+1 erd32 erd32+2 erd32 erd32+4 erd32 rd8+1 rd8 rd16+1 rd16 rd16+2 rd16 erd32+1 erd32 erd32+2 erd32 rd8 10 decimal adjust rd8 rd8-rs8 rd8 rd16-#xx:16 rd16 rd16-rs16 rd16 erd32-#xx:32 erd32 erd32-ers32 erd32 rd8-#xx:8-c rd8 rd8-rs8-c rd8 erd32-1 erd32 erd32-2 erd32 erd32-4 erd32 rd8-1 rd8 rd16-1 rd16 rd16-2 rd16 erd32-1 erd32 erd32-2 erd32 rd8 10 decimal adjust rd8 rd8 rs8 rd16(multiplication w/o si g n) rd16 rs16 erd32 (multiplication w/o si g n) rd8 rs8 rd16(multiplication w/o si g n) rd16 rs16 erd32 (multiplication w/o si g n) rd16 rs8 rd16 (rdh: remainder, rdl: quatient)(division w/o si g n) erd32 rs16 erd32 (ed:remainder, rd: quatient)(division with si g n) rd16 rs8 rd16(rdh: remainder, rdl: quatient)(division w/o si g n) erd32 rs16 erd32 (ed:remainder, rd: quatient)(division with si g n) rd8-#xx:8 rd8-rs8 rd16-#xx:16 rd16-rs16 erd32-#xx:32 erd32-ers32 0-rd8 rd8 0-rd16 rd16 0-erd32 erd32 0 ( appendix a instruction set rev.2.00 jan. 15, 2007 page 957 of 1174 rej09b0329-0200 table a.3 logic operations instructions and.b #xx:8,rd and.b rs,rd and.w #xx:16,rd and.w rs,rd and.l #xx:32,erd and.l ers,erd or.b #xx:8,rd or.b rs,rd or.w #xx:16,rd or.w rs,rd or.l #xx:32,erd or.l ers,erd xor.b #xx:8,rd xor.b rs,rd xor.w #xx:16,rd xor.w rs,rd xor.l #xx:32,erd xor.l ers,erd not.b rd not.w rd not.l erd b b w w l l b b w w l l b b w w l l b w l 2 4 6 2 4 6 2 4 6 2 2 4 2 2 4 2 2 4 2 2 2 and or xor not mnemonic size #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ? rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 ~rd8 rd8 ~rd16 rd16 ~erd32 erd32 operation condition code i hn zvc advanced mode 1 1 2 1 3 2 1 1 2 1 3 2 1 1 2 1 3 2 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 addressin g mode and instruction len g th (bytes) no of execution states * 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? appendix a instruction set rev.2.00 jan. 15, 2007 page 958 of 1174 rej09b0329-0200 table a.4 shift instructions shal.b rd shal.b #2,rd shal.w rd shal.w #2,rd shal.l erd shal.l #2,erd shar.b rd shar.b #2,rd shar.w rd shar.w #2,rd shar.l erd shar.l #2,erd shll.b rd shll.b #2,rd shll.w rd shll.w #2,rd shll.l erd shll.l #2,erd shlr.b rd shlr.b #2,rd shlr.w rd shlr.w #2,rd shlr.l erd shlr.l #2,erd rotxl.b rd rotxl.b #2,rd rotxl.w rd rotxl.w #2,rd rotxl.l erd rotxl.l #2,erd rotxr.b rd rotxr.b #2,rd rotxr.w rd rotxr.w #2,rd rotxr.l erd rotxr.l #2,erd rotl.b rd rotl.b #2,rd rotl.w rd rotl.w #2,rd rotl.l erd rotl.l #2,erd rotr.b rd rotr.b #2,rd rotr.w rd rotr.w #2,rd rotr.l erd rotr.l #2,erd b b w w l l b b w w l l b b w w l l b b w w l l b b w w l l b b w w l l b b w w l l b b w w l l 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 shal shar shll shlr rotxl rotxr rotl rotr mnemonic size #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ? operation condition code i hn zvc advanced mode 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 c 0 msb lsb c msb lsb c msb lsb c msb lsb c msb lsb c 0 msb lsb c 0 msb lsb c msb lsb addressin g mode and instruction len g th (bytes) no of execution states * 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? appendix a instruction set rev.2.00 jan. 15, 2007 page 959 of 1174 rej09b0329-0200 table a.5 bit manipulation instructions bset #xx:3,rd bset #xx:3,@erd bset #xx:3,@aa:8 bset #xx:3,@aa:16 bset #xx:3,@aa:32 bset rn,rd bset rn,@erd bset rn,@aa:8 bset rn,@aa:16 bset rn,@aa:32 bclr #xx:3,rd bclr #xx:3,@erd bclr #xx:3,@aa:8 bclr #xx:3,@aa:16 bclr #xx:3,@aa:32 bclr rn,rd bclr rn,@erd bclr rn,@aa:8 bclr rn,@aa:16 bclr rn,@aa:32 bnot #xx:3,rd bnot #xx:3,@erd bnot #xx:3,@aa:8 bnot #xx:3,@aa:16 bnot #xx:3,@aa:32 bnot rn,rd bnot rn,@erd bnot rn,@aa:8 bnot rn,@aa:16 bnot rn,@aa:32 btst #xx:3,rd btst #xx:3,@erd btst #xx:3,@aa:8 btst #xx:3,@aa:16 btst #xx:3,@aa:32 btst rn,rd btst rn,@erd btst rn,@aa:8 btst rn,@aa:16 btst rn,@aa:32 bld #xx:3,rd bld #xx:3,@erd bld #xx:3,@aa:8 bld #xx:3,@aa:16 bld #xx:3,@aa:32 bild #xx:3,rd bild #xx:3,@erd bild #xx:3,@aa:8 bild #xx:3,@aa:16 bild #xx:3,@aa:32 bst #xx:3,rd bst #xx:3,@erd bst #xx:3,@aa:8 bst #xx:3,@aa:16 bst #xx:3,@aa:32 bist #xx:3,rd bist #xx:3,@erd bist #xx:3,@aa:8 bist #xx:3,@aa:16 bist #xx:3,@aa:32 band #xx:3,rd band #xx:3,@erd band #xx:3,@aa:8 band #xx:3,@aa:16 band #xx:3,@aa:32 b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 bset bclr bnot btst bld bild bst bist band mnemonic size #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ? (#xx:3 of rd8) 1 (#xx:3 of @erd) 1 (#xx:3 of @aa:8) 1 (#xx:3 of @aa:16) 1 (#xx:3 of @aa:32) 1 (rn8 of rd8) 1 (rn8 of @erd) 1 (rn8 of @aa:8) 1 (rn8 of @aa:16) 1 (rn8 of @aa:32) 1 (#xx:3 of rd8) 0 (#xx:3 of @erd) 0 (#xx:3 of @aa:8) 0 (#xx:3 of @aa:16) 0 (#xx:3 of @aa:32) 0 (rn8 of rd8) 0 (rn8 of @erd) 0 (rn8 of @aa:8) 0 (rn8 of @aa:16) 0 (rn8 of @aa:32) 0 (#xx:3 of rd8) [~(#xx:3 of rd8)] (#xx:3 of @erd) [~(#xx:3 of @erd)] (#xx:3 of @aa:8) [~(#xx:3 of @aa:8)] (#xx:3 of @aa:16) [~(#xx:3 of @aa:16)] (#xx:3 of @aa:32) [~(#xx:3 of @aa:32)] (rn8 of rd8) [~(rn8 of rd8)] (rn8 of @erd) [~(rn8 of @erd)] (rn8 of @aa:8) [~(rn8 of @aa:8)] (rn8 of @aa:16) [~(rn8 of @aa:16)] (rn8 of @aa:32) [~(rn8 of @aa:32)] ~(#xx:3 of rd8) z ~(#xx:3 of @erd) z ~(#xx:3 of @aa:8) z ~(#xx:3 of @aa:16) z ~(#xx:3 of @aa:32) z ~(rn8 of rd8) z ~(rn8 of @erd) z ~(rn8 of @aa:8) z ~(rn8 of @aa:16) z ~(rn8 of @aa:32) z (#xx:3 of rd8) c (#xx:3 of @erd) c (#xx:3 of @aa:8) c (#xx:3 of @aa:16) c (#xx:3 of @aa:32) c ~(#xx:3 of rd8) c ~(#xx:3 of @erd) c ~(#xx:3 of @aa:8) c ~(#xx:3 of @aa:16) c ~(#xx:3 of @aa:32) c c (#xx:3 of rd8) c (#xx:3 of @erd) c (#xx:3 of @aa:8) c (#xx:3 of @aa:16) c (#xx:3 of @aa:32) ~c (#xx:3 of rd8) ~c (#xx:3 of @erd) ~c (#xx:3 of @aa:8) ~c (#xx:3 of @aa:16) ~c (#xx:3 of @aa:32) c (#xx:3 of rd8) c c (#xx:3 of @erd) c c (#xx:3 of @aa:8) c c (#xx:3 of @aa:16) c c (#xx:3 of @aa:32) c operation condition code i hn zvc advanced mode ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 4 4 5 6 1 4 4 5 6 1 3 3 4 5 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? addressin g mode and instruction len g th (bytes) no of execution states * 1 appendix a instruction set rev.2.00 jan. 15, 2007 page 960 of 1174 rej09b0329-0200 biand #xx:3,rd biand #xx:3,@erd biand #xx:3,@aa:8 biand #xx:3,@aa:16 biand #xx:3,@aa:32 bor #xx:3,rd bor #xx:3,@erd bor #xx:3,@aa:8 bor #xx:3,@aa:16 bor #xx:3,@aa:32 bior #xx:3,rd bior #xx:3,@erd bior #xx:3,@aa:8 bior #xx:3,@aa:16 bior #xx:3,@aa:32 bxor #xx:3,rd bxor #xx:3,@erd bxor #xx:3,@aa:8 bxor #xx:3,@aa:16 bxor #xx:3,@aa:32 bixor #xx:3,rd bixor #xx:3,@erd bixor #xx:3,@aa:8 bixor #xx:3,@aa:16 bixor #xx:3,@aa:32 b b b b b b b b b b b b b b b b b b b b b b b b b biand bor bior bxor bixor mnemonic size #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ? c [~(#xx:3 of rd8)] c c [~(#xx:3 of @erd)] c c [~(#xx:3 of @aa:8)] c c [~(#xx:3 of @aa:16)] c c [~(#xx:3 of @aa:32)] c c (#xx:3 of rd8) c c (#xx:3 of @erd) c c (#xx:3 of @aa:8) c c (#xx:3 of @aa:16) c c (#xx:3 of @aa:32) c c [~(#xx:3 of rd8)] c c [~(#xx:3 of @erd)] c c [~(#xx:3 of @aa:8)] c c [~(#xx:3 of @aa:16)] c c [~(#xx:3 of @aa:32)] c c (#xx:3 of rd8) c c (#xx:3 of @erd) c c (#xx:3 of @aa:8) c c (#xx:3 of @aa:16) c c (#xx:3 of @aa:32) c c [~(#xx:3 of rd8)] c c [~(#xx:3 of @erd)] c c [~(#xx:3 of @aa:8)] c c [~(#xx:3 of @aa:16)] c c [~(#xx:3 of @aa:32)] c operation i hn zvc advanced mode 2 2 2 2 2 4 4 4 4 4 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 condition code addressin g mode and instruction len g th (bytes) no of execution states * 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? appendix a instruction set rev.2.00 jan. 15, 2007 page 961 of 1174 rej09b0329-0200 table a.6 branch instructions bra d:8(bt d:8) bra d:16(bt d:16) brn d:8(bf d:8) brn d:16(bf d:16) bhi d:8 bhi d:16 bls d:8 bls d:16 bcc d:8(bhs d:8) bcc d:16(bhs d:16) bcs d:8(blo d:8) bcs d:16(blo d:16) bne d:8 bne d:16 beq d:8 beq d:16 bvc d:8 bvc d:16 bvs d:8 bvs d:16 bpl d:8 bpl d:16 bmi d:8 bmi d:16 bge d:8 bge d:16 blt d:8 blt d:16 bcc mnemonic size #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ? operation i branch condition hn zvc advanced mode 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 always never c z=0 c z=1 c=0 c=1 z=0 z=1 v=0 v=1 n=0 n=1 n v=0 n v=1 if condition is true then pc pc+d else next; 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 operation code ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bgt d:8 bgt d:16 ble d:8 ble d:16 jmp @ern jmp @aa:24 jmp @@aa:8 bsr d:8 bsr d:16 jsr @ern jsr @aa:24 jsr @@aa:8 rts jmp bsr jsr rts pc ern pc aa:24 pc @aa:8 pc @-sp,pc pc+d:8 pc @-sp,pc pc+d:16 pc @-sp,pc ern pc @-sp,pc aa:24 pc @-sp,pc @aa:8 pc @sp+ 2 2 4 4 2 4 2 4 2 4 2 2 2 2 3 2 3 2 3 z (n v)=0 z (n v)=1 5 4 5 4 5 6 5 addressin g mode and instruction len g th (bytes) no of execution states * 1 appendix a instruction set rev.2.00 jan. 15, 2007 page 962 of 1174 rej09b0329-0200 table a.7 system co ntrol instructions trapa #x:2 rte sleep ldc #xx:8,ccr ldc #xx:8,exr ldc rs,ccr ldc rs,exr ldc @ers,ccr ldc @ers,exr ldc @(d:16,ers),ccr ldc @(d:16,ers),exr ldc @(d:32,ers),ccr ldc @(d:32,ers),exr ldc @ers+,ccr ldc @ers+,exr ldc @aa:16,ccr ldc @aa:16,exr ldc @aa:32,ccr ldc @aa:32,exr stc.b ccr,rd stc.b exr,rd stc.w ccr,@erd stc.w exr,@erd stc.w ccr,@(d:16,erd) stc.w exr,@(d:16,erd) stc.w ccr,@(d:32,erd) stc.w exr,@(d:32,erd) stc.w ccr,@-erd stc.w exr,@-erd stc.w ccr,@aa:16 stc.w exr,@aa:16 stc.w ccr,@aa:32 stc.w exr,@aa:32 andc #xx:8,ccr andc #xx:8,exr orc #xx:8,ccr orc #xx:8,exr xorc #xx:8,ccr xorc #xx:8,exr nop ? ? ? b b b b w w w w w w w w w w w w b b w w w w w w w w w w w w b b b b b b ? trapa rte sleep ldc stc andc orc xorc nop mnemonic size #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ? pc @-sp,ccr @-sp, exr @-sp, appendix a instruction set rev.2.00 jan. 15, 2007 page 963 of 1174 rej09b0329-0200 table a.8 block transfer instructions eepmov.b eepmov.w ? ? eepmov mnemonic size #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ? operation i hn zvc advanced mode 4 4 4+2n * 3 4+2n * 3 ? ? ? ? ? ? ? ? ? ? ? ? condition code if r4l 0 repeat @er5 @er6 er5+1 er5 er6+1 er6 r4l-1 r4l until r4l=0 else next; if r4 0 repeat @er5 @er6 er5+1 er5 er6+1 er6 r4-1 r4 until r4=0 else next; addressin g mode and instruction len g th (bytes) no of execution states * 1 notes: 1. the values indicated in the column of number of execution states apply when instruction code and operand exist in the on-chip memory. 2. only register er0, er1, er4, or er5 should be used when using the tas instruction. 3. n is the initial setting value of r4l or r4. 4. only registers er0 to er6 should be used when using the stm/ldm instruction. [1] 7 states when the number of return/retract registers is 2, 9 states when the number of registers is 3, and 11 states when the number of registers is 4. [2] cannot be used in this lsi. [3] set to 1 when a carry or borrow occurs at bit 11, otherwise cleared to 0. [4] set to 1 when a carry or borrow occurs at bit 27, otherwise cleared to 0. [5] retains the value before computation when the computation result is 0, otherwise cleared to 0. [6] set to 1 when the divisor is negative, otherwise cleared to 0. [7] set to 1 when the divisor is 0, otherwise cleared to 0. [8] set to 1 when the quotient is negative, otherwise cleared to 0. [9] 1 is added to the number of execution states when exr is valid. appendix a instruction set rev.2.00 jan. 15, 2007 page 964 of 1174 rej09b0329-0200 a.2 instruction codes table a.9 instruction codes add adds addx and andc band bcc add.b #xx:8,rd add.b rs,rd add.w #xx:16,rd add.w rs,rd add.l #xx:32,erd add.l ers,erd adds #1,erd adds #2,erd adds #4,erd addx #xx:8,rd addx rs,rd and.b #xx:8,rd and.b rs,rd and.w #xx:16,rd and.w rs,rd and.l #xx:32,erd and.l ers,erd andc #xx:8,ccr andc #xx:8,exr band #xx:3,rd band #xx:3,@erd band #xx:3,@aa:8 band #xx:3,@aa:16 band #xx:3,@aa:32 bra d:8 (bt d:8) bra d:16 (bt d:16) brn d:8 (bf d:8) brn d:16 (bf d:16) bhi d:8 bhi d:16 bls d:8 bls d:16 bcc d:8 (bhs d:8) bcc d:16 (bhs d:16) bcs d:8 (blo d:8) bcs d:16 (blo d:16) bne d:8 bne d:16 beq d:8 beq d:16 bvc d:8 bvc d:16 bvs d:8 bvs d:16 mnemonic instruction format 1st byte b b w w l l l l l b b b b w w l l b b b b b b b ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 8 0 7 0 7 0 0 0 0 9 0 e 1 7 6 7 0 0 0 7 7 7 6 6 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 rd 8 9 9 a a b b b rd e rd 6 9 6 a 1 6 1 6 c e a a 0 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 8 rs 1 rs 1 1 ers 0 8 9 rs rs 6 rs 6 f 4 0 imm 0 erd 1 3 0 1 2 3 4 5 6 7 8 9 imm imm imm imm abs disp disp disp disp disp disp disp disp disp disp rd rd rd 0 erd 0 erd 0 erd 0 erd 0 erd rd rd rd rd 0 erd 0 1 rd 0 0 0 0 0 0 0 0 0 0 0 0 0 0 imm 0 imm 0 0 6 0 7 7 imm imm abs disp disp disp disp disp disp disp disp disp disp imm imm abs 6 6 6 6 0 imm 0 7 6 0 imm 0 7 6 2nd byte 3rd byte 4th byte 5th byte 6th byte 7the byte 8th byte 9th byte 10th byte size instruction 0 ers 0 erd imm appendix a instruction set rev.2.00 jan. 15, 2007 page 965 of 1174 rej09b0329-0200 bcc (cont.) bclr biand bild bior bist bpl d:8 bpl d:16 bmi d:8 bmi d:16 bge d:8 bge d:16 blt d:8 blt d:16 bgt d:8 bgt d:16 ble d:8 ble d:16 bclr #xx:3,rd bclr #xx:3,@erd bclr #xx:3,@aa:8 bclr #xx:3,@aa:16 bclr #xx:3,@aa:32 bclr rn,rd bclr rn,@erd bclr rn,@aa:8 bclr rn,@aa:16 bclr rn,@aa:32 biand #xx:3,rd biand #xx:3,@erd biand #xx:3,@aa:8 biand #xx:3,@aa:16 biand #xx:3,@aa:32 bild #xx:3,rd bild #xx:3,@erd bild #xx:3,@aa:8 bild #xx:3,@aa:16 bild #xx:3,@aa:32 bior #xx:3,rd bior #xx:3,@erd bior #xx:3,@aa:8 bior #xx:3,@aa:16 bior #xx:3,@aa:32 bist #xx:3,rd bist #xx:3,@erd bist #xx:3,@aa:8 bist #xx:3,@aa:16 bist #xx:3,@aa:32 mnemonic instruction format 1st byte ? ? ? ? ? ? ? ? ? ? ? ? b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b 4 5 4 5 4 5 4 5 4 5 4 5 7 7 7 6 6 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 a 8 b 8 c 8 d 8 e 8 f 8 2 d f a a 2 d f a a 6 c e a a 7 c e a a 4 c e a a 7 d f a a a b c d e f 0 imm 0 erd 1 3 rn 0 erd 1 3 1 imm 0 erd 1 3 1 imm 0 erd 1 3 1 imm 0 erd 1 3 1 imm 0 erd 1 3 disp disp disp disp disp disp abs abs abs abs abs abs 0 0 0 0 0 0 rd 0 8 8 rd 0 8 8 rd 0 0 0 rd 0 0 0 rd 0 0 0 rd 0 8 8 7 7 6 6 7 7 7 7 7 7 6 6 disp disp disp disp disp disp 2 2 abs 2 2 abs 6 6 abs 7 7 abs 4 4 abs 7 7 abs 0 imm 0 imm rn rn 1 imm 1 imm 1 imm 1 imm 1 imm 1 imm 1 imm 1 imm 0 0 abs 0 0 abs 0 0 abs 0 0 abs 0 0 abs 0 0 abs 7 6 7 7 7 6 2 2 6 7 4 7 0 imm rn 1 imm 1 imm 1 imm 1 imm 0 0 0 0 0 0 7 6 7 7 7 6 2 2 6 7 4 7 0 imm rn 1 imm 1 imm 1 imm 1 imm 0 0 0 0 0 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte size instruction appendix a instruction set rev.2.00 jan. 15, 2007 page 966 of 1174 rej09b0329-0200 bixor bld bnot bor bset bsr bst bixor #xx:3,rd bixor #xx:3,@erd bixor #xx:3,@aa:8 bixor #xx:3,@aa:16 bixor #xx:3,@aa:32 bld #xx:3,rd bld #xx:3,@erd bld #xx:3,@aa:8 bld #xx:3,@aa:16 bld #xx:3,@aa:32 bnot #xx:3,rd bnot #xx:3,@erd bnot #xx:3,@aa:8 bnot #xx:3,@aa:16 bnot #xx:3,@aa:32 bnot rn,rd bnot rn,@erd bnot rn,@aa:8 bnot rn,@aa:16 bnot rn,@aa:32 bor #xx:3,rd bor #xx:3,@erd bor #xx:3,@aa:8 bor #xx:3,@aa:16 bor #xx:3,@aa:32 bset #xx:3,rd bset #xx:3,@erd bset #xx:3,@aa:8 bset #xx:3,@aa:16 bset #xx:3,@aa:32 bset rn,rd bset rn,@erd bset rn,@aa:8 bset rn,@aa:16 bset rn,@aa:32 bsr d:8 bsr d:16 bst #xx:3,rd bst #xx:3,@erd bst #xx:3,@aa:8 bst #xx:3,@aa:16 bst #xx:3,@aa:32 mnemonic instruction format 1st byte b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b ? ? b b b b b 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 5 5 6 7 7 6 6 5 c e a a 7 c e a a 1 d f a a 1 d f a a 4 c e a a 0 d f a a 0 d f a a 5 c 7 d f a a 1 imm 0 erd abs 1 3 0 imm 0 erd abs 1 3 0 imm 0 erd abs 1 3 rn 0 erd abs 1 3 0 imm 0 erd abs 1 3 0 imm 0 erd abs 1 3 rn 0 erd abs 1 3 disp 0 0 imm 0 erd abs 1 3 rd 0 0 0 rd 0 0 0 rd 0 8 8 rd 0 8 8 rd 0 0 0 rd 0 8 8 rd 0 8 8 0 rd 0 8 8 7 7 7 7 7 7 6 6 7 7 7 7 6 6 6 6 5 5 abs 7 7 abs 1 1 abs 1 1 abs 4 4 abs 0 0 abs 0 0 abs disp 7 7 abs 1 imm 1 imm 0 imm 0 imm 0 imm 0 imm rn rn 0 imm 0 imm 0 imm 0 imm rn rn 0 imm 0 imm 0 0 abs 0 0 abs 0 0 abs 0 0 abs 0 0 abs 0 0 abs 0 0 abs 0 0 abs 7 7 7 6 7 7 6 6 5 7 1 1 4 0 0 7 1 imm 0 imm 0 imm rn 0 imm 0 imm rn 0 imm 0 0 0 0 0 0 0 0 7 7 7 6 7 7 6 6 5 7 1 1 4 0 0 7 1 imm 0 imm 0 imm rn 0 imm 0 imm rn 0 imm 0 0 0 0 0 0 0 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte size instruction appendix a instruction set rev.2.00 jan. 15, 2007 page 967 of 1174 rej09b0329-0200 btst bxor clrmac cmp daa das dec divxs divxu eepmov exts extu btst #xx:3,rd btst #xx:3,@erd btst #xx:3,@aa:8 btst #xx:3,@aa:16 btst #xx:3,@aa:32 btst rn,rd btst rn,@erd btst rn,@aa:8 btst rn,@aa:16 btst rn,@aa:32 bxor #xx:3,rd bxor #xx:3,@erd bxor #xx:3,@aa:8 bxor #xx:3,@aa:16 bxor #xx:3,@aa:32 clrmac cmp.b #xx:8,rd cmp.b rs,rd cmp.w #xx:16,rd cmp.w rs,rd cmp.l #xx:32,erd cmp.l ers,erd daa rd das rd dec.b rd dec.w #1,rd dec.w #2,rd dec.l #1,erd dec.l #2,erd divxs.b rs,rd divxs.w rs,erd divxu.b rs,rd divxu.w rs,erd eepmov.b eepmov.w exts.w rd exts.l erd extu.w rd extu.l erd mnemonic instruction format 1st byte cannot be used in this lsi b b b b b b b b b b b b b b b ? b b w w l l b b b w w l l b w b w ? ? w l w l 7 7 7 6 6 6 7 7 6 6 7 7 7 6 6 a 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 1 1 1 1 3 c e a a 3 c e a a 5 c e a a rd c 9 d a f f f a b b b b 1 1 1 3 b b 7 7 7 7 0 imm 0 erd abs 1 3 rn 0 erd abs 1 3 0 imm 0 erd abs 1 3 imm rs 2 rs 2 1 ers 0 0 0 5 d 7 f d d rs rs 5 d d f 5 7 rd 0 0 0 rd 0 0 0 rd 0 0 0 rd rd rd 0 erd 0 erd rd rd rd rd rd 0 erd 0 erd 0 0 rd 0 erd c 4 rd 0 erd rd 0 erd 7 7 6 6 7 7 5 5 5 5 3 3 abs 3 3 abs 5 5 abs imm 1 3 9 9 0 imm 0 imm rn rn 0 imm 0 imm rs rs 8 8 0 0 abs 0 0 abs 0 0 abs imm rd 0 erd f f 7 6 7 3 3 5 0 imm rn 0 imm 0 0 0 7 6 7 3 3 5 0 imm rn 0 imm 0 0 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte size instruction appendix a instruction set rev.2.00 jan. 15, 2007 page 968 of 1174 rej09b0329-0200 inc jmp jsr ldc ldm * 3 ldmac mac mov inc.b rd inc.w #1,rd inc.w #2,rd inc.l #1,erd inc.l #2,erd jmp @ern jmp @aa:24 jmp @@aa:8 jsr @ern jsr @aa:24 jsr @@aa:8 ldc #xx:8,ccr ldc #xx:8,exr ldc rs,ccr ldc rs,exr ldc @ers,ccr ldc @ers,exr ldc @(d:16,ers),ccr ldc @(d:16,ers),exr ldc @(d:32,ers),ccr ldc @(d:32,ers),exr ldc @ers+,ccr ldc @ers+,exr ldc @aa:16,ccr ldc @aa:16,exr ldc @aa:32,ccr ldc @aa:32,exr ldm.l @sp+, (ern-ern+1) ldm.l @sp+, (ern-ern+2) ldm.l @sp+, (ern-ern+3) ldmac ers,mach ldmac ers,macl mac @ern+,@erm+ mov.b #xx:8,rd mov.b rs,rd mov.b @ers,rd mov.b @(d:16,ers),rd mov.b @(d:32,ers),rd mov.b @ers+,rd mov.b @aa:8,rd mov.b @aa:16,rd mov.b @aa:32,rd mov.b rs,@erd mov.b rs,@(d:16,erd) mov.b rs,@(d:32,erd) mnemonic instruction format cannot be used in this lsi 1st byte b w w l l ? ? ? ? ? ? b b b b w w w w w w w w w w w w l l l l l ? b b b b b b b b b b b b 0 0 0 0 0 5 5 5 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f 0 6 6 7 6 2 6 6 6 6 7 a b b b b 9 a b d e f 7 1 3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 rd c 8 e 8 c rd a a 8 e 8 0 5 d 7 f 0 ern abs 0 ern abs imm 4 0 1 4 4 4 4 4 4 4 4 4 4 4 4 1 2 3 imm rs 0 ers 0 ers 0 ers 0 ers abs 0 2 1 erd 1 erd 0 erd rd rd rd 0 erd 0 erd 0 0 1 rs rs 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 rd rd rd 0 rd rd rd rs rs 0 abs abs 0 6 6 6 6 7 7 6 6 6 6 6 6 6 6 6 6 6 7 9 9 f f 8 8 d d b b b b d d d disp a abs disp a imm 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 0 2 2 7 7 7 2 a 0 0 0 0 0 0 0 0 0 0 0 0 0 ern+1 0 ern+2 0 ern+3 rd abs rs 6 6 disp disp b b abs abs 2 2 0 0 abs abs disp disp disp disp 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10 byte size instruction appendix a instruction set rev.2.00 jan. 15, 2007 page 969 of 1174 rej09b0329-0200 mov (cont.) movfpe movtpe mulxs mulxu neg nop mov.b rs,@-erd mov.b rs,@aa:8 mov.b rs,@aa :16 mov.b rs,@aa:32 mov.w #xx:16,rd mov.w rs,rd mov.w @ers,rd mov.w @(d:16,ers),rd mov.w @(d:32,ers),rd mov.w @ers+,rd mov.w @aa:16,rd mov.w @aa:32,rd mov.w rs,@erd mov.w rs,@(d:16,erd) mov.w rs,@(d:32,erd) mov.w rs,@-erd mov.w rs,@aa:16 mov.w rs,@aa:32 mov.l #xx:32,rd mov.l ers,erd mov.l @ers,erd mov.l @(d:16,ers),erd mov.l @(d:32,ers),erd mov.l @ers+,erd mov.l @aa:16 ,erd mov.l @aa:32 ,erd mov.l ers,@erd mov.l ers,@(d:16,erd) mov.l ers,@(d:32,erd) * 1 mov.l ers,@-erd mov.l ers,@aa:16 mov.l ers,@aa:32 movfpe @aa:16,rd movtpe rs,@aa:16 mulxs.b rs,rd mulxs.w rs,erd mulxu.b rs,rd mulxu.w rs,erd neg.b rd neg.w rd neg.l erd nop mnemonic instruction format 1st byte cannot be used in this lsi b b b b w w w w w w w w w w w w w w w l l l l l l l l l l l l l b b b w b w b w l ? 6 3 6 6 7 0 6 6 7 6 6 6 6 6 7 6 6 6 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 5 1 1 1 0 c rs a a 9 d 9 f 8 d b b 9 f 8 d b b a f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 2 7 7 7 0 1 erd abs 8 a 0 rs 0 ers 0 ers 0 ers 0 ers 0 2 1 erd 1 erd 0 erd 1 erd 8 a 0 1 ers 0 0 0 0 0 0 0 0 0 0 0 0 c c rs rs 8 9 b 0 rs rs rs rd rd rd rd 0 rd rd rd rs rs 0 rs rs rs 0 erd 0 erd 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd 0 erd rd rd 0 erd 0 6 6 6 6 7 6 6 6 6 6 7 6 6 6 5 5 abs imm disp b abs disp b abs 9 f 8 d b b 9 f 8 d b b 0 2 2 a 0 ers 0 ers 0 ers 0 ers 0 2 1 erd 1 erd 0 erd 1 erd 8 a rs rs abs rd abs rs abs imm 0 erd 0 erd 0 0 erd 0 erd 0 erd 0 ers 0 ers 0 0 ers 0 ers 0 ers rd 0 erd 6 6 disp b abs disp b abs 2 a disp disp 0 erd abs 0 ers abs disp disp 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte size instruction appendix a instruction set rev.2.00 jan. 15, 2007 page 970 of 1174 rej09b0329-0200 not or orc pop push rotl rotr rotxl rotxr rte rts not.b rd not.w rd not.l erd or.b #xx:8,rd or.b rs,rd or.w #xx:16,rd or.w rs,rd or.l #xx:32,erd or.l ers,erd orc #xx:8,ccr orc #xx:8,exr pop.w rn pop.l ern push.w rn push.l ern rotl.b rd rotl.b #2, rd rotl.w rd rotl.w #2, rd rotl.l erd rotl.l #2, erd rotr.b rd rotr.b #2, rd rotr.w rd rotr.w #2, rd rotr.l erd rotr.l #2, erd rotxl.b rd rotxl.b #2, rd rotxl.w rd rotxl.w #2, rd rotxl.l erd rotxl.l #2, erd rotxr.b rd rotxr.b #2, rd rotxr.w rd rotxr.w #2, rd rotxr.l erd rotxr.l #2, erd rte rts mnemonic instruction format 1st byte b w l b b w w l l b b w l w l b b w w l l b b w w l l b b w w l l b b w w l l ? ? 1 1 1 c 1 7 6 7 0 0 0 6 0 6 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 7 7 7 rd 4 9 4 a 1 4 1 d 1 d 1 2 2 2 2 2 2 3 3 3 3 3 3 2 2 2 2 2 2 3 3 3 3 3 3 6 4 0 1 3 imm rs 4 rs 4 f imm 4 7 0 f 0 8 c 9 d b f 8 c 9 d b f 0 4 1 5 3 7 0 4 1 5 3 7 7 7 rd rd 0 erd rd rd rd 0 erd 0 1 rn 0 rn 0 rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 0 6 0 6 6 imm 4 4 d d 0 ers imm 7 f imm 0 erd 0 ern 0 ern 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte size instruction appendix a instruction set rev.2.00 jan. 15, 2007 page 971 of 1174 rej09b0329-0200 shal shar shll shlr sleep stc stm * 3 stmac shal.b rd shal.b #2, rd shal.w rd shal.w #2, rd shal.l erd shal.l #2, erd shar.b rd shar.b #2, rd shar.w rd shar.w #2, rd shar.l erd shar.l #2, erd shll.b rd shll.b #2, rd shll.w rd shll.w #2, rd shll.l erd shll.l #2, erd shlr.b rd shlr.b #2, rd shlr.w rd shlr.w #2, rd shlr.l erd shlr.l #2, erd sleep stc.b ccr,rd stc.b exr,rd stc.w ccr,@erd stc.w exr,@erd stc.w ccr,@(d:16,erd) stc.w exr,@(d:16,erd) stc.w ccr,@(d:32,erd) stc.w exr,@(d:32,erd) stc.w ccr,@-erd stc.w exr,@-erd stc.w ccr,@aa:16 stc.w exr,@aa:16 stc.w ccr,@aa:32 stc.w exr,@aa:32 stm.l(ern-ern+1) , @-sp stm.l (ern-ern+2) , @-sp stm.l (ern-ern+3) , @-sp stmac mach,erd stmac macl,erd mnemonic instruction format 1st byte b b w w l l b b w w l l b b w w l l b b w w l l ? b b w w w w w w w w w w w w l l l l l 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 c 9 d b f 8 c 9 d b f 0 4 1 5 3 7 0 4 1 5 3 7 8 0 1 4 4 4 4 4 4 4 4 4 4 4 4 1 2 3 rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 rd rd 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 6 6 6 6 7 7 6 6 6 6 6 6 6 6 6 9 9 f f 8 8 d d b b b b d d d 1 erd 1 erd 1 erd 1 erd 0 erd 0 erd 1 erd 1 erd 8 8 a a f f f 0 0 0 0 0 0 0 0 0 0 0 0 0 ern 0 ern 0 ern 6 6 disp disp b b abs abs a a 0 0 abs abs disp disp 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte size instruction cannot be used in this lsi appendix a instruction set rev.2.00 jan. 15, 2007 page 972 of 1174 rej09b0329-0200 sub subs subx tas trapa xor xorc sub.b rs,rd sub.w #xx:16,rd sub.w rs,rd sub.l #xx:32,erd sub.l ers,erd subs #1,erd subs #2,erd subs #4,erd subx #xx:8,rd subx rs,rd tas @erd * 2 trapa #x:2 xor.b #xx:8,rd xor.b rs,rd xor.w #xx:16,rd xor.w rs,rd xor.l #xx:32,erd xor.l ers,erd xorc #xx:8,ccr xorc #xx:8,exr mnemonic instruction format 1st byte b w w l l l l l b b b ? b b w w l l b b 1 7 1 7 1 1 1 1 b 1 0 5 d 1 7 6 7 0 0 0 8 9 9 a a b b b rd e 1 7 rd 5 9 5 a 1 5 1 rs 3 rs 3 1 ers 0 8 9 imm rs e imm imm rs 5 rs 5 f imm 4 rd rd rd 0 erd 0 erd 0 erd 0 erd 0 erd rd 0 0 rd rd rd 0 erd 0 1 7 6 0 imm b imm 5 5 0 erd 0 ers imm imm c imm 0 erd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte size instruction notes: 1. either 1 or 0 can be set to bit 7 in 4th byte of mov.l ers, @(d: 32, erd) instruction. 2. only register er0, er1, er4, or er5 should be used when using the tas instruction. 3. only registers er0 to er6 should be used when using the stm/ldm instruction. legend: imm : immediate data (2, 3, 8, 16, 32 bits) abs : absolute address (8, 16, 24, 32 bits) disp : displacement (8, 16, 32 bits) rs, rd, rn : register fields (8-bit register or 16-bit register is selected in 4 bits. rs, rd and rn correspond to the operand type rs, rd, and rn respectively.) ers, erd, ern, erm : register fields (address register or 32-bit register is selected in 3 bits. ers, erd ern and erm correspon d to the operand type ers, erd, ern and rm respectively.) 00 appendix a instruction set rev.2.00 jan. 15, 2007 page 973 of 1174 rej09b0329-0200 the following table shows the correspondence between the register field and the general register. address register, 32-bit register 16-bit register 8-bit register register field general register register field general register register field general register 000 001 : : : : 111 er0 er1 : : : : er7 0000 0001 : : : : 0111 1000 1001 : : : : 1111 r0 r1 : : : : r7 e0 e1 : : : : e7 0000 0001 : : : : 0111 1000 1001 : : : : 1111 r0h r1h : : : : r7h r0l r1l : : : : r7l appendix a instruction set rev.2.00 jan. 15, 2007 page 974 of 1174 rej09b0329-0200 a.3 operation code map table a.10 shows an operation code map. table a.10 operation code map instruction code: 1st byte 2nd byte ah al bh bl bh highest bit is set to 0. bh highest bit is set to 1 0 nop bra mulxu bset ah al 0 1 2 3 4 5 6 7 8 9 a b c d e f 1 brn divxu bnot 2 bhi mulxu bclr 3 bls divxu btst stc stmac ldc ldmac 4 orc or bcc rts or bor bior 6 andc and bne rte and 5 xorc xor bcs bsr xor bxor bixor band biand 7 ldc beq trapa bst bist bld bild 8 bvc mov 9 bvs a bpl jmp b bmi eepmov c bge bsr d blt mov e addx subx bgt jsr f ble mov.b add addx cmp subx or xor and mov add sub mov mov cmp table a.2 ** note: * cannot be used in this lsi table a.2 table a.2 table a.2 table a.2 table a.2 table a.2 tablea.2 table a.2 table a.2 table a.2 table a.2 table a.2 table a.2 table a.2 table a.2 table a.2 appendix a instruction set rev.2.00 jan. 15, 2007 page 975 of 1174 rej09b0329-0200 instruction code: 1st byte 2nd byte ah al bh bl 01 0a 0b 0f 10 11 12 13 17 1a 1b 1f 58 6a 79 7a 0 mov inc adds daa dec subs das bra mov mov mov shll shlr rotxl rotxr not 1 ldm brn add add 2 bhi mov cmp cmp 3 stm not bls sub sub 4 shll shlr rotxl rotxr bcc movfpe or or 5 inc extu dec bcs xor xor 6 mac bne and and 7 inc shll shlr rotxl rotxr extu dec beq ldc stc 8 sleep bvc mov adds shal shar rotl rotr neg subs 9 bvs a clrmac bpl mov b neg bmi add mov sub cmp c shal shar rotl rotr bge movtpe d inc exts dec blt e tas bgt f inc shal shar rotl rotr exts dec ble bh ah al * * note: * cannot be used in this lsi * * table a.2 table a.2 table a.2 table a.2 table a.2 appendix a instruction set rev.2.00 jan. 15, 2007 page 976 of 1174 rej09b0329-0200 instruction code: 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl r is the register specification section. absolute address is set at aa. dh highest bit is set to 0. dh highest bit is set to 1. notes: ah al bh bl ch cl 01c05 01d05 01f06 7cr06 * 1 7cr07 * 1 7dr06 * 1 7dr07 * 1 7eaa6 * 2 7eaa7 * 2 7faa6 * 2 7faa7 * 2 0 mulxs bset bset bset bset 1 divxs bnot bnot bnot bnot 2 mulxs bclr bclr bclr bclr 3 divxs btst btst btst btst 4 or 5 xor 6 and 789abcdef 1. 2. bor bior bxor bixor band biand bld bild bst bist bor bior bxor bixor band biand bld bild bst bist appendix a instruction set rev.2.00 jan. 15, 2007 page 977 of 1174 rej09b0329-0200 instruction code: 1st byte 2nd byte ah al bh bl 3th byte 4th byte ch cl dh dl fh highest bit is set to 0. fh highest bit is set to 1. 5th byte 6th byte eh el fh fl instruction code: 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl hh highest bit is set to 0. hh highest bit is set to 1. note: * absolute address is set at aa. 5th byte 6th byte eh el fh fl 7th byte 8th byte gh gl hh hl 6a10aaaa6 * 6a10aaaa7 * 6a18aaaa6 * 6a18aaaa7 * ahalbhblchcldhdleh el 0 bset 1 bnot 2 bclr 3 btst bor bior bxor bixor band biand bld bild bst bist 456789abcdef 6a30aaaaaaaa6 * 6a30aaaaaaaa7 * 6a38aaaaaaaa6 * 6a38aaaaaaaa7 * ahalbhbl ... fhflgh gl 0 bset 1 bnot 2 bclr 3 btst bor bior bxor bixor band biand bld bild bst bist 456789abcdef appendix a instruction set rev.2.00 jan. 15, 2007 page 978 of 1174 rej09b0329-0200 a.4 number of ex ecution states this section explains execution st ate and how to calculate the number of execution states for each instruction of the h8s/2000 cpu. table a.12 indicates number of cycles of instruction fetch and data read/write during instruction execution, and table a.11 indicates number of states required for each instruction size. the number of execution states can be obtained from the equation below. number of execution states = i ? s i + j ? s j + k ? s k + l ? s l + m ? s m + n ? s n examples of execution state number calculation the conditions are as follows: in advanced mode, program and stack areas are set in the on-chip memory, a wait is inserted every 2 states in the on-chip supporting module access with 8-bit bus width. 1. bset #0, @ffffc7:8 from table a.12, i = l = 2, j = k = m = n = 0 from table a.11, s i = 1, s l = 2 number of execution states = 2 1 + 2 2 = 6 2. jsr @@30 from table a.12, i = j = k = 2, l = m = n = 0 from table a.11, s i = s j = s k = 1 number of execution states = 2 1 + 2 1 + 2 1 = 6 appendix a instruction set rev.2.00 jan. 15, 2007 page 979 of 1174 rej09b0329-0200 table a.11 number of states required for each execution status (cycle) target of access on-chip supporting module execution status (cycle) on-chip memory 8-bit bus 16-bit bus instruction fetch s i branch address read s j stack operation s k ? ? byte data access s l 2 2 word data access s m 1 4 internal operation s n 1 appendix a instruction set rev.2.00 jan. 15, 2007 page 980 of 1174 rej09b0329-0200 table a.12 instruction execution status (number of cycles) instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n add add.b #xx:8,rd add.b rs, rd add.w #xx:16,rd add.w rs,rd add l #xx:32,erd add.l ers,erd 1 1 2 1 3 1 adds adds #1/2/4,erd 1 addx addx #xx:8,rd addx rs,rd 1 1 and and.b #xx:8,rd and.b rs,rd and.w #xx.16,rd and.w rs,rd and l #xx:32,erd and.l ers,erd 1 1 2 1 3 2 andc andc #xx:8,ccr andc #xx:8,exr 1 2 band band #xx:3,rd band #xx:3,@erd band #xx:3@aa:8 band #xx:3@aa:16 band #xx:3@aa:32 1 2 2 3 4 1 1 1 1 bcc bra d:8 (bt d:8) brn d:8 (bf d:8) bhi d:8 bls d:8 bcc d:8 (bhs d:8) bcs d:8 (blo d:8) bne d:8 beq d:8 bvc d:8 bvs d:8 bpl d:8 bmi d:8 bge d:8 blt d:8 bgt d:8 ble d:8 bra d:16 (bt d:16) brn d:16 (bf d:16) bhi d:16 bls d:16 bcc d:16 (bhs d:16) bcs d:16 (blo d:16) bne d:16 beq d:16 bvc d:16 bvs d:16 bpl d:16 bmi d:16 bge d:16 blt d:16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 appendix a instruction set rev.2.00 jan. 15, 2007 page 981 of 1174 rej09b0329-0200 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n bcc bgt d:16 ble d:16 2 2 1 1 bclr bclr #xx:3,rd bclr #xx:3,@erd bclr #xx:3,@aa:8 bclr #xx:3,@aa:16 bclr #xx:3,@aa:32 bclr rn,rd bclr rn,@erd bclr rn,@aa:8 bclr rn,@aa:16 bclr rn,@aa:32 1 2 2 3 4 1 2 2 3 4 2 2 2 2 2 2 2 2 biand biand #xx:3,rd biand #xx:3,@erd biand #xx:3,@aa:8 biand #xx:3,@aa:16 biand #xx:3,@aa:32 1 2 2 3 4 1 1 1 1 bild bild #xx:3,rd bild #xx:3,@erd bild #xx:3,@aa:8 bild #xx:3,@aa:16 bild #xx:3,@aa:32 1 2 2 3 4 1 1 1 1 bior bior #xx:8,rd bior #xx:8,@erd bior #xx:8,@aa:8 bior #xx:8,@aa:16 bior #xx:8,@aa:32 1 2 2 3 4 1 1 1 1 bist bist #xx:3,rd bist #xx:3,@erd bist #xx:3,@aa:8 bist #xx:3,@aa:16 bist #xx:3,@aa:32 1 2 2 3 4 2 2 2 2 bixor bixor #xx:3,rd bixor #xx:3,@erd bixor #xx:3,@aa:8 bixor #xx:3,@aa:16 bixor #xx:3,@aa:32 1 2 2 3 4 1 1 1 1 bld bld #xx:3,rd bld #xx:3,@erd bld #xx:3,@aa:8 bld #xx:3,@aa:16 bld #xx:3,@aa:32 1 2 2 3 4 1 1 1 1 bnot bnot #xx:3,rd bnot #xx:3,@erd bnot #xx:3,@aa:8 bnot #xx:3,@aa:16 bnot #xx:3,@aa:32 bnot rn,rd bnot rn,@erd bnot rn,@aa:8 bnot rn,@aa:16 1 2 2 3 4 1 2 2 3 2 2 2 2 2 2 2 appendix a instruction set rev.2.00 jan. 15, 2007 page 982 of 1174 rej09b0329-0200 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n bnot bnot rn,@aa:32 4 2 bor bor #xx:3,rd bor #xx:3,@erd bor #xx:3,@aa:8 bor #xx:3,@aa:16 bor #xx:3,@aa:32 1 2 2 3 4 1 1 1 1 bset bset #xx:3,rd bset #xx:3,@erd bset #xx:3,@aa:8 bset #xx:3,@aa:16 bset #xx:3,@aa:32 bset rn,rd bset rn,@erd bset rn,@aa:8 bset rn,@aa:16 bset rn,@aa:32 1 2 2 3 4 1 2 2 3 4 2 2 2 2 2 2 2 2 bsr bsr d:8 2 2 bsr d:16 2 2 1 bst bst #xx:3,rd bst #xx:3,@erd bst #xx:3,@aa:8 bst #xx:3,@aa:16 bst #xx:3,@aa:32 1 2 2 3 4 2 2 2 2 btst btst #xx:3,rd btst #xx:3,@erd btst #xx:3,@aa:8 btst #xx:3,@aa:16 btst #xx:3,@aa:32 btst rn,rd btst rn,@erd btst rn,@aa:8 btst rn,@aa:16 btst rn,@aa:32 1 2 2 3 4 1 2 2 3 4 1 1 1 1 1 1 1 1 bxor bxor #xx:3,rd bxor #xx:3,@erd bxor #xx:3,@aa:8 bxor #xx:3,@aa:16 bxor #xx:3,@aa:32 1 2 2 3 4 1 1 1 1 clrmac clrmac cannot be used in this lsi. cmp cmp.b #xx:8,rd cmp.b rs,rd cmp.w #xx:16,rd cmp.w rs,rd cmp.l #xx:32,erd cmp.l ers,erd 1 1 2 1 3 1 daa daa rd 1 das das rd 1 appendix a instruction set rev.2.00 jan. 15, 2007 page 983 of 1174 rej09b0329-0200 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n dec dec.b rd dec.w #1/2,rd dec.l #1/2 erd 1 1 1 divxs divxs.b rs,rd divxs.w rs,erd 2 2 11 19 divxu divxu.b rs,rd divxu.w rs,erd 1 1 11 19 eepmov eepmov.b eepmov.w 2 2 2n+2 * 2 2n+2 * 2 exts exts.w rd exts.l erd 1 1 extu extu.w rd extu.l erd 1 1 inc inc.b rd inc.w #1/2,rd inc.l #1/2,erd 1 1 1 jmp jmp @ern jmp @aa:24 2 2 1 jmp @@aa:8 2 2 1 jsr jsr @ern 2 2 jsr @aa:24 2 2 1 jsr @@aa:8 2 2 2 ldc ldc #xx:8,ccr ldc #xx:8,exr ldc rs,ccr ldc rs,exr ldc @ers,ccr ldc @ers,exr ldc @(d:16,ers),ccr ldc @(d:16,ers),exr ldc @(d:32,ers),ccr ldc @(d:32,ers),exr ldc @ers+,ccr ldc @ers+,exr ldc @aa:16,ccr ldc @aa:16,exr ldc @aa:32,ccr ldc @aa:32,exr 1 2 1 1 2 2 3 3 5 5 2 2 3 3 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ldm * 4 ldm.l @sp+,(ern ? ern+1) ldm.l @sp+,(ern ? ern+2) ldm.l @sp+,(ern ? ern+3) 2 2 2 4 6 8 1 1 1 ldmac ldmac ers,mach ldmac ers,macl cannot be used in this lsi. mac mac @ern+,@erm+ appendix a instruction set rev.2.00 jan. 15, 2007 page 984 of 1174 rej09b0329-0200 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n mov mov.b #xx:8,rd mov.b rs,rd mov.b @ers,rd mov.b @(d:16,ers),rd mov.b @(d:32,ers),rd mov.b @ers+,rd mov.b @aa:8,rd mov.b @aa:16,rd mov.b @aa:32,rd mov.b rs,@erd mov.b rs,@(d:16,erd) mov.b rs,@(d:32,erd) mov.b rs,@-erd mov.b rs,@aa:8 mov.b rs,@aa:16 mov.b rs,@aa:32 mov.w #xx:16,rd mov.w rs,rd mov.w @ers,rd mov.w @(d:16,ers),rd mov.w @(d:32,ers),rd mov.w @ers+,rd mov.w @aa:16,rd mov.w @aa:32,rd mov.w rs,@erd mov.w rs,@(d:16,erd) mov.w rs,@(d:32,erd) mov.w rs,@-erd mov.w rs,@aa:16 mov.w rs,@aa:32 mov.l #xx:32,erd mov.l ers,erd mov.l @ers,erd mov.l @(d:16,ers),erd mov.l @(d:32,ers),erd mov.l @ers+,erd mov.l @aa:16,erd mov.l @aa:32,erd mov.l ers,@erd mov.l ers,@(d:16,erd) mov.l ers,@(d:32,erd) mov.l ers,@-erd mov.l ers,@aa:16 mov.l ers,@aa:32 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 movfpe movfpe @:aa:16,rd movtpe movtpe rs,@:aa:16 cannot be used in this lsi. mulxs mulxs.b rs,rd 2 11 mulxs.w rs,erd 2 19 mulxu mulxu.b rs,rd 1 11 mulxu.w rs,erd 1 19 appendix a instruction set rev.2.00 jan. 15, 2007 page 985 of 1174 rej09b0329-0200 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n neg neg.b rd neg.w rd neg.l erd 1 1 1 nop nop 1 not not.b rd not.w rd not.l erd 1 1 1 or or.b #xx:8,rd or.b rs,rd or.w #xx:16,rd or.w rs,rd or.l #xx:32,erd or.l ers,erd 1 1 2 1 3 2 orc orc #xx:8,ccr orc #xx:8,exr 1 2 pop pop.w rn pop.l ern 1 2 1 2 1 1 push push.w rn push.l ern 1 2 1 2 1 1 rotl rotl.b rd rotl.b #2,rd rotl.w rd rotl.w #2,rd rotl.l erd rotl.l #2,erd 1 1 1 1 1 1 rotr rotr.b rd rotr.b #2,rd rotr.w rd rotr.w #2,rd rotr.l erd rotr.l #2,erd 1 1 1 1 1 1 rotxl rotxl.b rd rotxl.b #2,rd rotxl.w rd rotxl.w #2,rd rotxl.l erd rotxl.l #2,erd 1 1 1 1 1 1 rotxr rotxr.b rd rptxr.b #2,rd rotxr.w rd rotxr.w #2,rd rotxr.l erd rotxr.l #2,erd 1 1 1 1 1 1 rte rte 2 2/3 * 1 1 rts rts 2 2 1 appendix a instruction set rev.2.00 jan. 15, 2007 page 986 of 1174 rej09b0329-0200 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n shal shal.b rd shal.b #2,rd shal.w rd shal.w #2,rd shal.l erd shal.l #2,erd 1 1 1 1 1 1 shar shar.b rd shar.b #2,rd shar.w rd shar.w #2,rd shar.l erd shar.l #2,erd 1 1 1 1 1 1 shll shll.b rd shll.b #2,rd shll.w rd shll.w #2,rd shll.l erd shll.l #2,erd 1 1 1 1 1 1 shlr shlr.b rd shlr.b #2,rd shlr.w rd shlr.w #2,rd shlr.l erd shlr.l #2,erd 1 1 1 1 1 1 sleep sleep 1 1 stc stc.b ccr.rd stc.b exr,rd stc.w ccr,@erd stc.w exr,@erd stc.w ccr,@(d:16,erd) stc.w exr,@(d:16,erd) stc.w ccr,@(d:32,erd) stc.w exr,@(d:32,erd) stc.w ccr,@-erd stc.w exr,@-erd stc.w ccr,@aa:16 stc.w exr,@aa:16 stc.w ccr,@aa:32 stc.w exr,@aa:32 1 1 2 2 3 3 5 5 2 2 3 3 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 stm * 4 stm.l (ern-ern+1), @-sp stm.l (ern-ern+2), @-sp stm.l (ern-ern+3), @-sp 2 2 2 4 6 8 1 1 1 stmac stmac mach,erd stmac macl,erd cannot be used in this lsi. sub sub.b rs,rd sub.w #xx:16,rd sub.w rs,rd sub.l #xx:32,erd sub.l ers,erd 1 2 1 3 1 subs subs #1/2/4,erd 1 appendix a instruction set rev.2.00 jan. 15, 2007 page 987 of 1174 rej09b0329-0200 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n subx subx #xx:8,rd subx rs,rd 1 1 tas tas @erd * 3 2 2 trapa trapa #x:2 2 2 2/3 * 1 2 xor xor.b #xx:8,rd xor.b rs,rd xor.w #xx:16,rd xor.w rs,rd xor.l #xx:32,erd xor.l ers,erd 1 1 2 1 3 2 xorc xorc #xx:8,ccr xorc #xx:8,exr 1 2 notes: 1. 3 applies when exr is valid, and 2 applies when invalid. 2. applies when the transfer data is n bytes. 3. only register er0, er1, er4, or er5 should be used when using the tas instruction. 4. only registers er0 to er6 should be used when using the stm/ldm instruction. appendix a instruction set rev.2.00 jan. 15, 2007 page 988 of 1174 rej09b0329-0200 a.5 bus status during instruction execution table a.13 indicates execution status of each instruc tion available in this lsi. for the number of states required for each execution status, see ta ble a.11, number of states required for each execution status (cycle). interpreting the table instruction jmp@aa:24 r:w 2nd internal operation 1 state r:w ea 1 234567 8 end of instruction order of execution effective address is read by word. read/write not executed the 2nd word of the instruction currently being executed is read by word. r : b read by byte r : w read by word w : b write by byte w : w write by word : m bus not transferred immediately after this cycle 2nd address of the 2nd word (3rd and 4th bytes) 3rd address of the 3rd word (5th and 6th bytes) 4th address of the 4th word (7th and 8th bytes) 5th address of the 5th word (9th and 10th bytes) next the head address of the instruction immediately after the instruction currently being executed ea execution address vec vector address appendix a instruction set rev.2.00 jan. 15, 2007 page 989 of 1174 rej09b0329-0200 table a.13 instruction execution status instruction 1 2 3 4 5 6 7 8 9 add.b #xx:8,rd r:w next add.b rs,rd r:w next add.w #xx:16,rd r:w 2nd r:w next add.w rs,rd r:w next add.l #xx:32,erd r:w 2nd r:w 3rd r:w next add.l ers,erd r:w next adds #1/2/4,erd r:w next addx #xx:8,rd r:w next addx rs,rd r:w next and.b #xx:8,rd r:w next and.b rs,rd r:w next and.w #xx:16,rd r:w 2nd r:w next and.w rs,rd r:w next and.l #xx:32,erd r:w 2nd r:w 3rd r:w next and.l ers,erd r:w 2nd r:w next andc #xx:8,ccr r:w next andc #xx:8,exr r:w 2nd r:w next band #xx:3,rd r:w next band #xx:3,@erd r:w 2nd r:b ea r:w:m next band #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next band #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next band #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bra d:8 (bt d:8) r:w next r:w ea brn d:8 (bf d:8) r:w next r:w ea bhi d:8 r:w next r:w ea bls d:8 r:w next r:w ea bcc d:8 (bhs d:8) r:w next r:w ea bcs d:8 (blo d:8) r:w next r:w ea bne d:8 r:w next r:w ea beq d:8 r:w next r:w ea bvc d:8 r:w next r:w ea bvs d:8 r:w next r:w ea bpl d:8 r:w next r:w ea bmi d:8 r:w next r:w ea bge d:8 r:w next r:w ea appendix a instruction set rev.2.00 jan. 15, 2007 page 990 of 1174 rej09b0329-0200 instruction 1 2 3 4 5 6 7 8 9 blt d:8 r:w next r:w ea bgt d:8 r:w next r:w ea ble d:8 r:w next r:w ea bra d:16 (bt d:16) r:w 2nd internal operation 1 state r:w ea brn d:16 (bf d:16) r:w 2nd internal operation 1 state r:w ea bhi d:16 r:w 2nd internal operation 1 state r:w ea bls d:16 r:w 2nd internal operation 1 state r:w ea bcc d:16 (bhs d:16) r:w 2nd internal operation 1 state r:w ea bcs d:16 (blo d:16) r:w 2nd internal operation 1 state r:w ea bne d:16 r:w 2nd internal operation 1 state r:w ea beq d:16 r:w 2nd internal operation 1 state r:w ea bvc d:16 r:w 2nd internal operation 1 state r:w ea bvs d:16 r:w 2nd internal operation 1 state r:w ea bpl d:16 r:w 2nd internal operation 1 state r:w ea bmi d:16 r:w 2nd internal operation 1 state r:w ea bge d:16 r:w 2nd internal operation 1 state r:w ea blt d:16 r:w 2nd internal operation 1 state r:w ea bgt d:16 r:w 2nd internal operation 1 state r:w ea appendix a instruction set rev.2.00 jan. 15, 2007 page 991 of 1174 rej09b0329-0200 instruction 1 2 3 4 5 6 7 8 9 ble d:16 r:w 2nd internal operation 1 state r:w ea bclr #xx:3,rd r:w next bclr #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bclr #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bclr #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bclr #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bclr rn,rd r:w next bclr rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bclr rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bclr rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bclr rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea biand #xx:3,rd r:w next biand #xx:3,erd r:w 2nd r:b ea r:w:m next biand #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next biand #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next biand #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bild #xx:3,rd r:w next bild #xx:3,@erd r: w 2nd r:b ea r:w:m next bild #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bild #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bild #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bior #xx:3,rd r:w next bior #xx:3,@erd r:w 2nd r:b ea r:w:m next boir #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next appendix a instruction set rev.2.00 jan. 15, 2007 page 992 of 1174 rej09b0329-0200 instruction 1 2 3 4 5 6 7 8 9 boir #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next boir #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bist #xx:3,rd r:w next bist #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bixor #xx:3,rd r:w next bixor #xx:3,@erd r:w 2nd r:b ea r:w:m next bixor #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bixor #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bixor #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bld #xx:3,rd r:w next bld #xx:3,@erd r:w 2nd r:b ea r:w:m next bld #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bld #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bld #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bnot #xx:3,rd r:w next bnot #xx:3,erd r:w 2nd r:b:m ea r:w:m next w:b ea bnot #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bnot #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bnot #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bnot rn,rd r:w next bnot rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bnot rn @aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea appendix a instruction set rev.2.00 jan. 15, 2007 page 993 of 1174 rej09b0329-0200 instruction 1 2 3 4 5 6 7 8 9 bnot rn @aa:16 r:w 2nd r:w 3rd r:b:w ea r:w:m next w:b ea bnot rn @aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bor #xx:3,rd r:w next bor #xx:3,erd r:w 2nd r:b ea r:w:m next bor #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bor #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bor #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w next bset #xx:3,rd r:w next bset #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bset #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bset #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bset #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bset rn,rd r:w next bset rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bset rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bset rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bset rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bsr d:8 r:w next r:w ea w:w:m stack(h) w:w stack(l) bsr d:16 r:w 2nd internal operation 1 state r:w ea w:w:m stack(h) w:w stack(l) bst #xx:3,rd r:w next bst #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea btst #xx:3,rd r:w next appendix a instruction set rev.2.00 jan. 15, 2007 page 994 of 1174 rej09b0329-0200 instruction 1 2 3 4 5 6 7 8 9 btst #xx:3,@erd r:w 2nd r:b ea r:w:m next btst #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next btst #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next btst #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next btst rn,rd r:w next btst rn,@erd r:w 2nd r:b ea r:w:m next btst rn,@aa:8 r:w 2nd r:b ea r:w:m next btst rn,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next btst rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next boxr #xx:3,rd r:w next boxr #xx:3,@erd r:w 2nd r:b ea r:w:m next boxr #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next boxr #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next boxr #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next clrmac cannot be used in this lsi. cmp.b #xx:8,rd r:w next cmp.b rs,rd r:w next cmp.w #xx:16,rd r:w 2nd r:w next cmp.w rs,rd r:w next cmp.l #xx:32,erd r:w 2nd r:w 3rd r:w next cmp.l ers,erd r:w next daa rd r:w next das rd r:w next dec.b rd r:w next dec.w #1/2,rd r:w next dec.w #1/2,erd r:w next divxs.b rs,rd r:w 2nd r:w next internal operation 11 state divxs.w rs,erd r:w 2nd r:w next internal operation 19 state appendix a instruction set rev.2.00 jan. 15, 2007 page 995 of 1174 rej09b0329-0200 instruction 1 2 3 4 5 6 7 8 9 divxu.b rs,rd r:w next internal operation 11 state divxu.w rs,erd r:w next internal operation 19 state eepmov.b r:w 2nd r:b eas * 1 r:b ead * 1 r:b eas * 2 w:b ead * 2 r:w next eepmov.w r:w 2nd r:b eas * 1 r:b ead * 1 r:b eas * 2 w:b ead * 2 r:w next exts.w rd r:w next repeat n times * 2 exts.l erd r:w next extu.w rd r:w next extu.l erd r:w next inc.b rd r:w next inc.w #1/2,rd r:w next inc.l #1/2,erd r:w next jmp @ern r:w next r:w ea jmp @aa:24 r:w 2nd internal operation 1 state r:w ea jmp @@aa:8 r:w next r:w:m aa:8 r:w:m aa:8 internal operation 1 state r:w ea jsr @ern r:w n ext r:w ea w:w:m stack(h) w:w stack (l) jsr @aa:24 r:w 2nd internal operation 1 state r:w ea w:w:m stack(h) w:w stack (l) jsr @@aa:8 r:w next r:w:m aa:8 r:w aa:8 w:w:m stack(h) w:w stack (l) r:w ea ldc #xx.8,ccr r:w next ldc #xx.8,exr r:w 2nd r:w next ldc rs,ccr r:w next ldc rs,exr r:w next ldc @ers,ccr r:w 2nd r:w next r:w ea ldc @ers,exr r:w 2nd r:w next r:w ea ldc @(d:16,ers),ccr r:w 2nd r:w 3rd r:w next r:w ea ldc @(d:16,ers),exr r:w 2nd r:w 3rd r:w next r:w ea ldc @(d:32,ers),ccr r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next r:w ea ldc @(d:32,ers),exr r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next r:w ea ldc @ers+,ccr r:w 2nd r:w next internal operation 1 state r:w ea appendix a instruction set rev.2.00 jan. 15, 2007 page 996 of 1174 rej09b0329-0200 instruction 1 2 3 4 5 6 7 8 9 ldc @ers+,exr r:w 2nd r:w next internal operation 1 state r:w ea ldc @aa:16,ccr r:w 2nd r:w 3rd r:w next r:w ea ldc @aa:16,exr r:w 2nd r:w 3rd r:w next r:w ea ldc @aa:32,ccr r:w 2nd r:w 3rd r:w 4th r:w next r:w ea ldc @aa:32,exr r:w 2nd r:w 3rd r:w 4th r:w next r:w ea ldm.l @sp+, (ern-ern+1) * 9 r:w 2nd r:w:m next internal operation 1 state r:w:m stack(h) * 3 r:w stack(l) * 3 ldm.l @sp+, (ern-ern+2) * 9 r:w 2nd r:w:m next internal operation 1 state r:w:m stack(h) * 3 r:w stack(l) * 3 ldm.l @sp+, (ern-ern+3) * 9 r:w 2nd r:w:m next internal operation 1 state r:w:m stack(h) * 3 r:w stack(l) * 3 ldmac ers,mach cannot be used in this lsi. ldmac ers,macl mac @ern+,@erm+ mov.b #xx:8,rd r:w next mov.b rs,rd r:w next mov.b @ers,rd r:w next r:b ea mov.b @(d:16,ers),rd r:w 2nd r:w next r:b ea mov.b @(d:32,ers),rd r:w 2nd r:w 3rd r:w 4th r:w next r:b ea mov.b @ers+,rd r:w next internal operation 1 state r:b ea mov.b @aa:8,rd r:w next r:b ea mov.b @aa:16,rd r:w 2nd r:w next r:b ea mov.b @aa:32,rd r:w 2nd r:w 3rd r:w next r:b ea mov.b rs,@erd r:w next w:b ea mov.b rs,@(d:16,erd) r:w 2nd r:w next w:b ea mov.b rs,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w next w:b ea mov.b rs,@-erd r:w next internal operation 1 state w:b ea mov.b rs,@aa:8 r:w next w:b ea mov.b rs,@aa:16 r:w 2nd r:w next w:b ea mov.b rs,@aa:32 r:w 2nd r:w 3rd r:w next w:b ea mov.w #xx:16,rd r:w 2nd r:w next appendix a instruction set rev.2.00 jan. 15, 2007 page 997 of 1174 rej09b0329-0200 instruction 1 2 3 4 5 6 7 8 9 mov.w rs,rd r:w next mov.w @ers,rd r:w next r:w ea mov.w @(d:16,ers),rd r:w 2nd r:w next r:w ea mov.w @(d:32,ers),rd r:w 2nd r:w 3rd r:w 4th r:w next r:w ea mov.w @ers+,rd r:w next internal operation 1 state r:w ea mov.w @aa:16,rd r:w 2nd r:w next r:w ea mov.w @aa:32,rd r:w 2nd r:w 3rd r:w next r:b ea mov.w rs,@erd r:w next w:w ea mov.w rs,@(d:16,erd) r:w 2nd r:w next w:w ea mov.w rs,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w next w:w ea mov.w rs,@-erd r:w next internal operation 1 state w:w ea mov.w rs,@aa:16 r:w 2nd r:w next w:w ea mov.w rs,@aa:32 r:w 2nd r:w 3rd r:w next w:w ea mov.l #xx:32,erd r:w 2nd r:w 3rd r:w next mov.l ers,erd r:w next mov.l @ers,erd r:w 2nd r:w:m next r:w:m ea r:w ea+2 mov.l @(d:16,ers),erd r:w 2nd r:w:m 3rd r:w next r:w:m ea r:w ea+2 mov.l @(d:32,ers),erd r:w 2nd r:w:m 3rd r:w:m 4th r:w 5th r:w next r:w:m ea r:w ea+2 mov.l @ers+,erd r:w 2nd r:w:m next internal operation 1 state r:w:m ea r:w ea+2 mov.l @aa:16,erd r:w 2nd r:w:m 3rd r:w next r:w:m ea r:w ea+2 mov.l @aa:32,erd r:w 2nd r:w:m 3rd r:w 4th r:w next r:w:m ea r:w ea+2 mov.l ers,@erd r:w 2nd r:w:m next w:w:m ea w:w ea+2 mov.l ers,@(d:16,erd) r:w 2nd r:w:m 3rd r:w next w:w:m ea w:w ea+2 mov.l ers,@(d:32,erd) r:w 2nd r:w:w 3rd r:w:m 4th r:w 5th r:w next w:w:m ea w:w ea+2 mov.l ers,@-erd r:w 2nd r:w:m next internal operation 1 state w:w:m ea w:w ea+2 appendix a instruction set rev.2.00 jan. 15, 2007 page 998 of 1174 rej09b0329-0200 instruction 1 2 3 4 5 6 7 8 9 mov.l ers,@aa:16 r:w 2nd r:w:m 3rd r:w next w:w:m ea w:w ea+2 mov.l ers,@aa:32 r:w 2nd r:w:m 3rd r:w 4th r:w next w:w:m ea w:w ea+2 movfpe @aa:16,rd cannot be used in this lsi. movtpe rs,@aa:16 mulxs.b rs,rd r:w 2nd r:w next internal operation 11 state mulxs.w rs,rd r:w 2nd r:w next internal operation 19 state mulxu.b rs,rd r:w next internal operation 11 state mulxu.w rs,rd r:w next internal operation 19 state neg.b rd r:w next neg.w rd r:w next neg.l erd r:w next nop r:w next not.b rd r:w next not.w rd r:w next not.l erd r:w next or.b #xx:8,rd r:w next or.b rs,rd r:w next or.w #xx:16,rd r:w 2nd r:w next or.w rs,rd r:w next or.l #xx:32,erd r:w 2nd r:w 3rd r:w next or.l ers,erd r:w 2nd r:w next orc #xx:8,ccr r:w next orc #xx:8,exr r:w 2nd r:w next pop.w rn r:w next internal operation 1 state r:w ea pop.l ern r:w 2nd r:w:m next internal operation 1 state r:w:m ea r:w ea+2 push.w rn r:w next internal operation 1 state w:w ea push.l ern r:w 2nd r:w:m next internal operation 1 state w:w:m ea w:w ea+2 rotl.b rd r:w next rotl.b #2,rd r:w next rotl.w rd r:w next rotl.w #2,rd r:w next rotl.l erd r:w next rotl.l #2, erd r:w next appendix a instruction set rev.2.00 jan. 15, 2007 page 999 of 1174 rej09b0329-0200 instruction 1 2 3 4 5 6 7 8 9 rotr.b rd r:w next rotr.b #2,rd r:w next rotr.w rd r:w next rotr.w #2,rd r:w next rotr.l erd r:w next rotr.l #2,erd r:w next rotxl.b rd r:w next rotxl.b #2.rd r:w next rotxl.w rd r:w next rotxl.w #2,rd r:w next rotxl.l erd r:w next rotxl.l #2,erd r:w next rotxr.b rd r:w next rotxr.b #2,rd r:w next rotxr.w rd r:w next rotxr.w #2,rd r:w next rotxr.l erd r:w next rotxr.l #2.erd r:w next rte r:w next r:w stack (exr) r:w stack(h) r:w stack(l) internal operation 1 state r:w * 4 rts r:w next r:w:m stack(h) r:w stack(l) internal operation 1 state r:w * 4 shal.b rd r:w next shal b #2,rd r:w next shal.w rd r:w next shal.w #2,rd r:w next shal.l erd r:w next shal.l #2,erd r:w next shar.b rd r:w next shar.b #2,rd r:w next shar.w rd r:w next shar.w #2,rd r:w next shar.l erd r:w next shar.l #2,erd r:w next shll.b rd r:w next shll.b #2,rd r:w next shll.w rd r:w next shll.w #2,rd r:w next shll.l erd r:w next appendix a instruction set rev.2.00 jan. 15, 2007 page 1000 of 1174 rej09b0329-0200 instruction 1 2 3 4 5 6 7 8 9 shll.l #2,erd r:w next shlr.b rd r:w next shlr.b #2,rd r:w next shlr.w rd r:w next shlr.w #2,rd r:w next shlr.l erd r:w next shlr.l #2,erd r:w next sleep r:w next internal operation: m stc.b ccr,rd r:w next stc.b exr,rd r:w next stc.w ccr,@erd r:w 2nd r:w next w:w ea stc.w exr,@erd r:w 2nd r:w next w:w ea stc.w ccr,@(d:16,erd) r:w 2nd r:w 3rd r:w next w:w ea stc.w exr,@(d:16,erd) r:w 2nd r:w 3rd r:w next w:w ea stc.w ccr,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next w:w ea stc.w exr,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next w:w ea stc.w ccr,@- erd r:w 2nd r:w next internal operation 1 state w:w ea stc.w exr,@- erd r:w 2nd r:w next internal operation 1 state w:w ea stc.w ccr,@aa:16 r:w 2nd r:w 3rd r:w next w:w ea stc.w exr,@aa:16 r:w 2nd r:w 3rd r:w next w:w ea stc.w ccr,@aa:32 r:w 2nd r:w 3rd r:w 4th r:w next w:w ea stc.w exr,@aa:32 r:w 2nd r:w 3rd r:w 4th r:w next w:w ea stm.l (ern- ern+1),@-sp * 9 r:w 2nd r:w:m next internal operation 1 state w:w:m stack (h) * 3 w:w stack (l) * 3 stm.l (ern- ern+2),@-sp * 9 r:w 2nd r:w:m next internal operation 1 state w:w:m stack (h) * 3 w:w stack (l) * 3 stm.l (ern- ern+3),@-sp * 9 r:w 2nd r:w:m next internal operation 1 state w:w:m stack (h) * 3 w:w stack (l) * 3 appendix a instruction set rev.2.00 jan. 15, 2007 page 1001 of 1174 rej09b0329-0200 instruction 1 2 3 4 5 6 7 8 9 stmac mach,erd cannot be used in this lsi. stmac macl,erd sub.b rs,rd r:w next sub.w #xx:16,rd r:w 2nd r:w next sub.w rs,rd r:w next sub.l #xx:32,erd r:w 2nd r:w 3nd r:w next sub.l ers,erd r:w next sub #1/2/4,erd r:w next subx #xx:8,rd r:w next subx rs,rd r:w next tas @erd * 5 r:w 2nd r:w next r:b:m ea w:b ea trapa #x:2 r:w next internal operation 1 state w:w stack(l) w:w stack(h) w:w stack(exr) r:w:m vec r:w vec+2 internal operation 1 state r:w * 6 xor.b #xx:8,rd r:w next xor.b rs,rd r:w next xor.w #xx:16,rd r:w 2nd r:w next xor.w rs,rd r:w next xor.l #xx:32,erd r:w 2nd r:w 3rd r:w next xor.l ers,erd r:w 2nd r:w next xorc #xx:8,ccr r:w next xorc #xx:8,exr r:w 2nd r:w next reset exception handling r:w:m vec r:w vec+2 internal operation 1 state r:w * 6 interrupt exception handling r:w * 7 internal operation 1 state w:w stack(l) w:w stack(h) w:w stack(exr) r:w:m vec r:w vec+2 internal operation 1 state r:w * 8 notes: 1. eas is the contents of er5, and ead is the contents of er6. 2. 1 is added to eas and ead after execution. n is the initial value of r4l or r4. when 0 is set to n, r4l or r4 is not executed. 3. repeated twice for 2-unit retract/return, three times for 3-unit retract/return, and four times for 4-retract/return. 4. head address after return. 5. only register er0, er1, er4, or er5 should be used when using the tas instruction. 6. start address of the program. 7. pre-fetch address obtained by adding 2 to the pc to be retracted. when returning from sleep mode, standby mode or watch mode, internal operation is executed instead of read operation. 8. head address of the interrupt process routine. 9. only registers er0 to er6 should be used when using the stm/ldm instruction. appendix a instruction set rev.2.00 jan. 15, 2007 page 1002 of 1174 rej09b0329-0200 a.6 change of condition codes this section explains change of condition codes after instruction execution of the cpu. legend of the following tables is as follows. m = 31: longword size m = 15: word size m = 7: byte size si: bit i of source operand di: bit i of destination operand ri: bit i of result dn: specified bit of destination operand ? : no affection : changes depending on execution result 0: always cleared to 0 1: always set to 1 *: value undetermined z': z flag before execution c': c flag before execution appendix a instruction set rev.2.00 jan. 15, 2007 page 1003 of 1174 rej09b0329-0200 table a.14 change of condition code instruction h n z v c definition add h=sm-4 ? dm-4+dm-4 ? rm-4 +sm-4 ? rm-4 n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 v=sm ? dm ? rm + sm ? dm ? rm c=sm ? dm+dm ? rm +sm ? rm adds ? ? ? ? ? addx h=sm-4 ? dm-4+dm-4 ? rm-4 +sm-4 ? rm-4 n=rm z=z' ? rm ? ? ? ? ? ? ? ? r0 v=sm ? dm ? rm + sm ? dm ? rm c=sm ? dm+dm ? rm +sm ? rm and ? 0 ? n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 andc value in the bit corresponding to execution result is stored. no flag change when exr. band ? ? ? ? c=c' ? dn bcc ? ? ? ? ? bclr ? ? ? ? ? biand ? ? ? ? c=c' ? dn bild ? ? ? ? c= dn bior ? ? ? ? c=c'+ dn bist ? ? ? ? ? bixor ? ? ? ? c=c' ? dn+ c' ? dn bld ? ? ? ? c=dn bnot ? ? ? ? ? bor ? ? ? ? c=c'+dn bset ? ? ? ? ? bsr ? ? ? ? ? bst ? ? ? ? ? btst ? ? ? ? z= dn bxor ? ? ? ? c=c' ? dn + c' ? dn clrmac cannot be used in this lsi. appendix a instruction set rev.2.00 jan. 15, 2007 page 1004 of 1174 rej09b0329-0200 instruction h n z v c definition cmp h=sm-4 ? dm-4 + dm-4 ? rm-4+sm-4 ? rm-4 n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 v= sm ? dm ? rm +sm ? dm ? rm c=sm ? dm + dm ? rm+sm ? rm daa * * n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 c: decimal addition carry das * * n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 c: decimal subtraction borrow dec ? ? n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 v=dm ? rm divxs ? ? ? n=sm ? dm + sm ? dm z= sm ? sm-1 ? ? ? ? ? ? ? ? s0 divxu ? ? ? n=sm z= sm ? sm-1 ? ? ? ? ? ? ? ? s0 eepmov ? ? ? ? ? exts ? 0 ? n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 extu ? 0 0 ? z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 inc ? ? n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 v= dm ? rm jmp ? ? ? ? ? jsr ? ? ? ? ? ldc value in the bit corresponding to execution result is stored. no flag change when exr. ldm ? ? ? ? ? ldmac mac cannot be used in this lsi. mov ? 0 ? n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 appendix a instruction set rev.2.00 jan. 15, 2007 page 1005 of 1174 rej09b0329-0200 instruction h n z v c definition movfpe movtpe cannot be used in this lsi. mulxs ? ? ? n=r2m z= r2m ? r2m-1 ? ? ? ? ? ? ? ? r0 mulxu ? ? ? ? ? neg h=dm-4+rm-4 n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 v=dm ? rm c=dm+rm nop ? ? ? ? ? not ? 0 ? n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 or ? 0 ? n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 orc value in the bit corresponding to execution result is stored. no flag change when exr. pop ? 0 ? n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 push ? 0 ? n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 rotl ? 0 n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 c=dm(in case of 1 bit), c=dm-1(in case of 2 bits) rotr ? 0 n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 c=d0 (in case of 1 bit) , c=d-1 (in case of 2 bits) rotxl ? 0 n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 c=dm (in case of 1 bit) , c=dm-1 (in case of 2 bits) rotxr ? 0 n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 c=d0 (in case of 1 bit) , c=d1 (in case of 2 bits) rte value in the bit corresponding to execution result is stored. rts ? ? ? ? ? appendix a instruction set rev.2.00 jan. 15, 2007 page 1006 of 1174 rej09b0329-0200 instruction h n z v c definition shal ? n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 v=dm ? dm-1+ dm ? dm-1 (in case of 1 bit) v=dm ? dm-1 ? dm-2 ? dm ? dm-1 ? dm-2 (in case of 2bits) c=dm (in case of 1 bit) , c=dm-1 (in case of 2 bits) shar ? 0 n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 c=d0 (in case of 1 bit) , c=d1 (in case of 2 bits) shll ? 0 n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 c=dm (in case of 1 bit) , c=dm-1 (in case of 2 bits) shlr ? 0 0 n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 c=d0 (in case of 1 bit) , c=d1 (in case of 2 bits) sleep ? ? ? ? ? stc ? ? ? ? ? stm ? ? ? ? ? stmac cannot be used in this lsi. sub h=sm-4 ? dm-4 + dm-4 ? rm-4+sm-4 ? rm-4 n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 v= sm ? dm ? rm +sm ? dm ? rm c=sm ? dm + dm ? rm+sm ? rm subs ? ? ? ? ? subx h=sm-4 ? dm-4 + dm-4 ? rm-4+sm-4 ? rm-4 n=rm z=z' ? rm ? ? ? ? ? ? ? ? r0 v= sm ? dm ? rm +sm ? dm ? rm c=sm ? dm + dm ? rm+sm ? rm tas * ? 0 ? n=dm z= dm ? dm-1 ? ? ? ? ? ? ? ? d0 trapa ? ? ? ? ? xor ? 0 ? n=rm z= rm ? rm-1 ? ? ? ? ? ? ? ? r0 xorc value in the bit corresponding to execution result is stored. no flag change when exr. note: * this instruction should be used with the er0, er1, er4, or er5 general register only. appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1007 of 1174 rej09b0329-0200 appendix b internal i/o registers b.1 addresses address * 1 register name r/w access bus width 7 6 5 4 3 2 1 0 module name h'0000 to h'cfff h'd000 dgkp w 16 16 dgkp15 dgkp14 dgkp13 dgkp12 dgkp11 dgkp10 dgkp9 dgkp8 h'd001 dgkp7 dgkp6 dgkp5 dgkp4 dgkp3 dgkp2 dgkp1 dgkp0 h'd002 dgks w 16 16 dgks15 dgks14 dgks13 dgks12 dgks11 dgks10 dgks9 dgks8 h'd003 dgks7 dgks6 dgks5 dgks4 dgks3 dgks2 dgks1 dgks0 h'd004 dap w 16 16 dap15 dap14 dap13 dap12 dap11 dap10 dap9 dap8 h'd005 dap7 dap6 dap5 dap4 dap3 dap2 dap1 dap0 h'd006 dbp w 16 16 dbp15 dbp14 dbp13 dbp12 dbp11 dbp10 dbp9 dbp8 h'd007 dbp7 dbp6 dbp5 dbp4 dbp3 dbp2 dbp1 dbp0 h'd008 das w 16 16 das15 das14 das13 das12 das11 das10 das9 das8 h'd009 das7 das6 das5 das4 das3 das2 das1 das0 h'd00a dbs w 16 16 dbs15 dbs14 dbs13 dbs12 dbs11 dbs10 dbs9 dbs8 h'd00b dbs7 dbs6 dbs5 dbs4 dbs3 dbs2 dbs1 dbs0 h'd00c dofp w 16 16 dofp15 dofp14 dofp13 dofp12 dofp11 dofp10 dofp9 dofp8 h'd00d dofp7 dofp6 dofp5 dofp4 dofp3 dofp2 dofp1 dofp0 h'd00e dofs w 16 16 dofs15 dofs14 d ofs13 dofs12 dofs11 d ofs10 dofs9 dofs8 h'd00f dofs7 dofs6 dofs 5 dofs4 dofs3 d ofs2 dofs1 dofs0 drum digital filter h'd010 cgkp w 16 16 cgkp15 cgkp14 cgkp13 cgkp12 cgkp11 cgkp10 cgkp9 cgkp8 h'd011 cgkp7 cgkp6 cgkp5 cgkp4 cgkp3 cgkp2 cgkp1 cgkp0 h'd012 cgks w 16 16 cgks15 cgks14 cgks13 cgks12 cgks11 cgks10 cgks9 cgks8 h'd013 cgks7 cgks6 cgks5 cgks4 cgks3 cgks2 cgks1 cgks0 h'd014 cap w 16 16 cap15 cap14 cap13 cap12 cap11 cap10 cap9 cap8 h'd015 cap7 cap6 cap5 cap4 cap3 cap2 cap1 cap0 h'd016 cbp w 16 16 cbp15 cbp14 cbp13 cbp12 cbp11 cbp10 cbp9 cbp8 h'd017 cbp7 cbp6 cbp5 cbp4 cbp3 cbp2 cbp1 cbp0 h'd018 cas w 16 16 cas15 cas14 cas13 cas12 cas11 cas10 cas9 cas8 h'd019 cas7 cas6 cas5 cas4 cas3 cas2 cas1 cas0 h'd01a cbs w 16 16 cbs15 cbs14 cbs13 cbs12 cbs11 cbs10 cbs9 cbs8 h'd01b cbs7 cbs6 cbs5 cbs4 cbs3 cbs2 cbs1 cbs0 h'd01c cofp w 16 16 cofp15 cofp14 cofp13 cofp12 cofp11 cofp10 cofp9 cofp8 h'd01d cofp7 cofp6 cofp5 cofp4 cofp3 cofp2 cofp1 cofp0 h'd01e cofs w 16 16 cofs15 cofs14 c ofs13 cofs12 cofs11 c ofs10 cofs9 cofs8 h'd01f cofs7 cofs6 cofs 5 cofs4 cofs3 c ofs2 cofs1 cofs0 capstan digital filter h'd020 dzs w 16 16 ? ? ? ? dzs11 dzs10 dzs9 dzs8 digital filter h'd021 dzs7 dzs6 dzs5 dzs4 dzs3 dzs2 dzs1 dzs0 h'd022 dzp w 16 16 ? ? ? ? dzp11 dzp10 dzp9 dzp8 h'd023 dzp7 dzp6 dzp5 dzp4 dzp3 dzp2 dzp1 dzp0 appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1008 of 1174 rej09b0329-0200 address * 1 register name r/w access bus width 7 6 5 4 3 2 1 0 module name h'd024 czs w 16 16 ? ? ? ? czs11 czs10 czs9 czs8 h'd025 czs7 czs6 czs5 czs4 czs3 czs2 czs1 czs0 h'd026 czp w 16 16 ? ? ? ? czp11 czp10 czp9 czp8 h'd027 czp7 czp6 czp5 czp4 czp3 czp2 czp1 czp0 h'd028 dfic r/w 8 16 ? drov dpha dzpon dzso n dsg2 dsg1 dsg0 h'd029 cfic r/w 8 ? crov cpha czpon czso n csg2 csg1 csg0 h'd02a dfucr r/w 8 16 ? ? pton cp/ dp cfeps dfeps cfess dfess digital filter h'd030 dfpr w 16 16 dfpr15 dfpr14 dfpr13 dfpr12 dfpr11 dfpr10 dfpr9 dfpr8 h'd031 dfpr7 dfpr6 dfpr5 dfpr4 dfpr3 dfpr2 dfpr1 dfpr0 h'd032 dfer r/w 16 16 dfer15 dfer14 dfer13 dfer12 dfer11 dfer10 dfer9 dfer8 h'd033 dfer7 dfer6 dfer5 dfer4 dfer3 dfer2 dfer1 dfer0 h'd034 dfrudr w 16 16 dfrudr 15 dfrudr 14 dfrudr 13 dfrudr 12 dfrudr 11 dfrudr 10 dfrudr 9 dfrudr 8 h'd035 dfrudr 7 dfrudr 6 dfrudr 5 dfrudr 4 dfrudr 3 dfrudr 2 dfrudr 1 dfrudr 0 h'd036 dfrldr w 16 16 dfrldr1 5 dfrldr1 4 dfrldr1 3 dfrldr1 2 dfrldr1 1 dfrldr1 0 dfrldr9 dfrldr8 h'd037 dfrldr7 dfrldr6 dfrldr5 dfrldr4 dfrldr3 dfrldr2 dfrldr1 dfrldr0 h'd038 dfvcr r/w 8 16 dfcs1 dfcs0 dfovf dfrfon df- r/unr dpcnt dfrcs1 dfrcs0 h'd039 dpgcr r/w 8 16 dpcs1 dpcs0 dpovf n/v hswes ? ? ? h'd03a dppr2 w 16 16 dppr15 dppr14 dppr13 dppr12 dppr11 dppr10 dppr9 dppr8 h'd03b dppr7 dppr6 dppr 5 dppr4 dppr3 d ppr2 dppr1 dppr0 h'd03c dppr1 w 8 16 ? ? ? ? dppr19 dppr18 dppr17 dppr16 h'd03d dper1 r/w 8 16 ? ? ? ? dper19 dper18 dper17 dper16 h'd03e dper15 dper14 dper13 dper12 dper11 dper10 dper9 dper8 h'd03f dper2 r/w 16 16 dper7 dper6 dper5 dper4 dper3 dper2 dper1 dper0 drum error detector h'd040 to h'd04f h'd050 cfpr w 16 16 cfpr15 cfpr14 cfpr13 cfpr12 cfpr11 cfpr10 cfpr9 cfpr8 h'd051 cfpr7 cfpr6 cfpr5 cfpr4 cfpr3 cfpr2 cfpr1 cfpr0 h'd052 cfer r/w 16 16 cfer15 cfer14 cfer13 cfer12 cfer11 cfer10 cfer9 cfer8 h'd053 cfer7 cfer6 cfer5 cfer4 cfer3 cfer2 cfer1 cfer0 h'd054 cfrudr w 16 16 cfrudr 15 cfrudr 14 cfrudr 13 cfrudr 12 cfrudr 11 cfrudr 10 cfrudr 9 cfrudr 8 h'd055 cfrudr 7 cfrudr 6 cfrudr 5 cfrudr 4 cfrudr 3 cfrudr 2 cfrudr 1 cfrudr 0 h'd056 cfrldr w 16 16 cfrldr1 5 cfrldr1 4 cfrldr1 3 cfrldr1 2 cfrldr1 1 cfrldr1 0 cfrldr9 cfrldr8 h'd057 cfrldr7 cfrldr6 cfrldr5 cfrldr4 cfrldr3 cfrldr2 cfrldr1 cfrldr0 h'd058 cfvcr r/w 8 cfcs1 cfcs0 cfovf cfrfon cf- r/unr cpcnt cfrcs1 cfrcs0 h'd059 cpgcr r/w 8 16 cpcs1 cpcs0 cpovf cr/rf selcfg2 ? ? ? h'd05a cppr2 w 16 16 cph15 cph14 cp h13 cph12 cph11 cph10 cph9 cph8 h'd05b cph7 cph6 cph5 cph4 cph3 cph2 cph1 cph0 h'd05c cppr1 w 8 16 ? ? ? ? cph19 cph18 cph17 cph16 capstan error detector appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1009 of 1174 rej09b0329-0200 address * 1 register name r/w access bus width 7 6 5 4 3 2 1 0 module name h'd05d cper1 r/w 8 16 ? ? ? ? cper19 cper18 cper17 cper16 h'd05e cper2 r/w 16 16 cper15 cper14 cper13 cper12 cper11 cper10 cper9 cper8 h'd05f cper7 cper6 cper 5 cper4 cper3 c per2 cper1 cper0 capstan error detector h'd060 hsm1 r/w 8 16 flb fla empb empa ovwb ovwa clrb clra h'd061 hsm2 r/w 8 frt fgr2off lop edg isel1 sofg ofg vff/nff h'd062 hslp r/w 8 16 lob3 lob2 lob1 lob0 loa3 loa2 loa1 loa0 h'd063 h'd064 fpdra w 16 16 ? adtrga striga narrowff a vffa affa vpulsea mlevela h'd065 ppga7 ppga6 ppga5 ppga4 ppga3 ppga2 ppga1 ppga0 h'd066 ftpra * 2 w 16 16 ftpra15 ftpra14 ftpra13 ftpra12 ftpra11 ftpra10 ftpra9 ftpra8 h'd066 ftctr * 2 r 16 ftctr15 ftctr14 ftctr13 ftctr12 ftctr11 ftctr10 ftctr9 ftctr8 h'd067 ftpra * 2 w 16 16 ftpra7 ftpra6 ftpra5 ftpra4 ftpra3 ftpra2 ftpra1 ftpra0 h'd067 ftctr * 2 r 16 ftctr7 ftctr6 ftctr5 ftctr4 ftctr3 ftctr2 ftctr1 ftctr0 h'd068 fpdrb w 16 16 ? adtrgb strigb narrowff b vffb affb vpulseb mlevelb h'd069 ppgb7 ppgb6 ppgb5 ppgb4 ppgb3 ppgb2 ppgb1 ppgb0 h'd06a ftprb15 ftprb14 ftprb13 ftprb12 ftprb11 ftprb10 ftprb9 ftprb8 h'd06b ftprb w 16 16 ftprb7 ftprb6 ftprb5 ftprb4 ftprb3 ftprb2 ftprb1 ftprb0 h'd06c dfcra * 2 w 8 16 isel2 cclr cksl dfcra 4 dfcra3 dfcra2 dfcra1 dfcra0 h'd06c dfctr * 2 r 8 ? ? ? dfctr4 dfctr3 dfctr2 dfctr1 dfctr0 h'd06d dfcrb w 8 16 ? ? ? dfcrb4 dfcrb3 dfcrb2 dfcrb1 dfcrb0 hsw timing generator h'd06e chcr w 8 16 v/n hswpol crh hah sig3 sig2 sig1 sig0 4 head special- effects playback h'd06f addvr r/w 8 ? ? ? hmsk hi-z cut vpon pol additional v h'd070 xdr w 16 16 ? ? ? ? xd11 xd10 xd9 xd8 h'd071 xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 h'd072 trdr w 16 16 ? ? ? ? trd11 trd10 trd9 trd8 h'd073 trd7 trd6 trd5 trd4 trd3 trd2 trd1 trd0 h'd074 xtcr r/w 8 16 ? caprf at/ mu trk/ x exc/ref xcs dvref1 dvref0 x-value, trk-value h'd075 to h'd077 h'd078 dpwdr r/w 16 16 ? ? ? ? dpwdr1 1 dpwdr1 0 dpwdr9 dpwdr8 h'd079 dpwdr7 dpwdr6 dpwdr5 dpwdr4 dpwdr3 dpwdr2 dpwdr1 dpwdr0 h'd07a dpwcr w 8 16 dpol ddc dhiz dh/l dsf/df dck2 dck1 dck0 drum 12- bit pwm h'd07b cpwcr w 8 cpol cdc chiz ch/l csf/df cck2 cck1 cck0 h'd07c cpwdr r/w 16 16 ? ? ? ? cpwdr1 1 cpwdr1 0 cpwdr9 cpwdr8 h'd07d cpwdr7 cpwdr6 cpwdr5 cpwdr4 cpwdr3 cpwdr2 cpwdr1 cpwdr0 capstan 12-bit pwm h'd07e to h'd07f appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1010 of 1174 rej09b0329-0200 address * 1 register name r/w access bus width 7 6 5 4 3 2 1 0 module name h'd080 ctcr w 8 16 nt/pl fslc fslb fsla ccs lctl unctl slwm h'd081 ctlm r/w 8 asm rec/ pb fw/rv md4 md3 md2 md1 md0 h'd082 rcdr1 w 16 16 ? ? ? ? cmt1b cmt1a cmt19 cmt18 h'd083 cmt17 cmt16 cmt15 cmt14 cmt13 cmt12 cmt11 cmt10 h'd084 rcdr2 w 16 16 ? ? ? ? cmt2b cmt2a cmt29 cmt28 h'd085 cmt27 cmt26 cmt25 cmt24 cmt23 cmt22 cmt21 cmt20 h'd086 rcdr3 w 16 16 ? ? ? ? cmt3b cmt3a cmt39 cmt38 h'd087 cmt37 cmt36 cmt35 cmt34 cmt33 cmt32 cmt31 cmt30 h'd088 rcdr4 w 16 16 ? ? ? ? cmt4b cmt4a cmt49 cmt48 h'd089 cmt47 cmt46 cmt45 cmt44 cmt43 cmt42 cmt41 cmt40 h'd08a rcdr5 w 16 16 ? ? ? ? cmt5b cmt5a cmt59 cmt58 h'd08b cmt57 cmt56 cmt 55 cmt54 cmt53 cmt52 cmt51 cmt50 h'd08c di/o r/w 8 16 vctr2 vctr1 vctr0 ? bpon bps bpf di/o h'd08d btpr r/w 8 lsp7 lsp6 lsp5 lsp4 lsp3 lsp2 lsp1 lsp0 ctl circuit h'd08e to h'd08f h'd090 rfd w 16 16 ref15 ref14 ref 13 ref12 ref11 ref10 ref9 ref8 h'd091 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 h'd092 crf w 16 16 crf15 crf14 crf13 crf12 crf11 crf10 crf9 crf8 h'd093 crf7 crf6 crf5 crf4 crf3 crf2 crf1 crf0 h'd094 rfc r/w 16 16 rfc15 rfc14 rfc13 rfc12 rfc11 rfc10 rfc9 rfc8 h'd095 rfc7 rfc6 rfc5 rfc4 rfc3 rfc2 rfc1 rfc0 h'd096 rfm r/w 8 16 rcs vna cvs rex crd od/ev vst veg h'd097 rfm2 r/w 8 ? ? ? ? ? ? ? fds reference signal generator h'd098 ctvc r/w 8 16 cex ceg ? ? ? cfg hsw ctl h'd099 ctlr w 8 ctl7 ctl6 ctl5 ctl4 ctl3 ctl2 ctl1 ctl0 h'd09a cdvc r/w 8 16 mcgin ? cmk cmn dvtrg crf cps1 cps0 h'd09b cdivr1 w 8 ? cdv16 cdv15 cdv14 cdv 13 cdv12 cdv11 cdv10 h'd09c cdivr2 w 8 16 ? cdv26 cdv25 cdv24 cdv 23 cdv22 cdv21 cdv20 h'd09d ctmr w 8 ? ? cpm5 cpm4 cpm3 cpm2 cpm1 cpm0 h'd09e fgcr w 8 16 ? ? ? ? ? ? ? drf frequency divider h'd09f h'd0a0 spmr r/w 8 8 ctlstop ? cfgcom p ? ? ? ? ? h'd0a1 to h'd0a2 h'd0a3 svmcr r/w 8 8 ? ? svmcr5 svmcr4 svmcr3 svmcr2 svmcr1 svmcr0 h'd0a4 ctlgr r/w 8 8 ? ? ctle/ a ctlfb ctlgr3 ctlgr2 ctlgr1 ctlgr0 servo port control h'd0a5 to h'd0af h'd0b0 vtr w 8 16 ? ? vtr5 vtr4 vtr3 vtr2 vtr1 vtr0 h'd0b1 htr w 8 16 ? ? ? ? htr3 htr2 htr1 htr0 h'd0b2 hrtr w 8 16 hrtr7 hrtr6 hrtr5 hrtr4 hrtr3 hrtr2 hrtr1 hrtr0 h'd0b3 hpwr w 8 16 ? ? ? ? hpwr3 hpwr2 hpwr1 hpwr0 sync detector (servo) appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1011 of 1174 rej09b0329-0200 address * 1 register name r/w access bus width 7 6 5 4 3 2 1 0 module name h'd0b4 nwr w 8 16 ? ? nwr5 nwr4 nwr3 nwr2 nwr1 nwr0 h'd0b5 ndr w 8 16 ndr7 ndr6 ndr5 ndr4 ndr3 ndr2 ndr1 ndr0 h'd0b6 syncr r/w 8 16 ? ? ? ? nis/vd nois fld syct sync detector (servo) h'd0b7 h'd0b8 sienr1 r/w 8 16 iedrm3 iedrm2 iedrm1 iecap3 iecap2 iecap1 iehsw2 iehsw1 h'd0b9 sienr2 r/w 8 16 ? ? ? ? ? ? iesnc iectl h'd0ba sirqr1 r/w 8 16 i rrdrm3 irrdrm2 irrdrm1 irrcap3 irrcap2 irrcap1 irrhsw2 irrhsw1 h'd0bb sirqr2 r/w 8 16 ? ? ? ? ? ? irrsnc irrctl h'd0bc to h'd0e4 servo interrupt control h'd0e5 ddcswr r/w 8 8 swe sw ie if ? ? ? ? h'd0e8 iccr0 r/w 8 8 ice ieic mst trs acke bbsy iric scp h'd0e9 icsr0 r/w 8 8 estp stop irtr aasx al aas adz ackb h'd0ee icdr0 * 3 r/w 8 8 icdr7 icdr6 icdr5 i cdr4 icdr3 icdr2 icdr1 icdr0 h'd0ee sarx0 * 3 svax6 svax5 svax4 svax3 svax2 svax1 svax0 fsx h'd0ef icmr0 * 3 mls wait cks2 cks1 cks0 bc2 bc1 bc0 h'd0ef sar0 * 3 sva6 sva5 sva4 sva3 sva2 sva1 sva0 fs h'd0f0 to h'd0ff i 2 c interface h'd100 tier r/w 8 16 iciae icibe icice icide ociae ocibe ovie icsa h'd101 tcsrx r/w 8 16 icfa icfb icfc icfd ocfa ocfb ovf cclra h'd102 frch r/w 8/16 16 h'd103 frcl h'd104 ocrah * 4 r/w 8/16 16 h'd105 ocral * 4 h'd104 ocrbh * 4 r/w 8/16 16 h'd105 ocrbl * 4 h'd106 tcrx r/w 8 16 iedga iedgb iedgc iedgd bufea bufeb cks1 cks0 h'd107 tocr r/w 8 16 icsb icsc icsd ocrs oea oeb olvla olvlb h'd108 icrah r 8/16 16 timer x1 h'd109 icral h'd10a icrbh r 8/16 16 h'd10b icrbl h'd10c icrch r 8/16 16 h'd10d icrcl h'd10e icrdh r 8/16 16 h'd10f icrdl h'd110 tmb r/w 8 8 tmb17 tmbif tmbie ? ? tmb12 tmb11 tmb10 h'd111 tcb r 8 8 tcb17 tcb16 tcb15 tcb14 tcb13 tcb12 tcb11 tcb10 h'd111 tlb w 8 8 tlb17 tlb16 tlb15 tlb14 tlb13 tlb12 tlb11 tlb10 timer b h'd112 lmr r/w 8 8 lmif lmie ? ? lmr3 lmr2 lmr1 lmr0 timer l h'd113 ltc r 8 8 ltc7 ltc6 ltc5 ltc4 ltc3 ltc2 ltc1 ltc0 h'd113 rcr w 8 8 rcr7 rcr6 rcr5 rcr4 rcr3 rcr2 rcr1 rcr0 appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1012 of 1174 rej09b0329-0200 address * 1 register name r/w access bus width 7 6 5 4 3 2 1 0 module name h'd114 to h'd117 h'd118 tmrm1 r/w 8 8 clr2 ac/br rld rlck ps21 ps20 rld/cap cps h'd119 tmrm2 r/w 8 8 lat ps11 ps10 ps31 ps30 cp/slm capf slw h'd11a tmrcp1 r 8 8 tmrc17 tmrc16 tmrc15 tmrc14 tmrc13 tmrc12 tmrc11 tmrc10 h'd11b tmrcp2 r 8 8 tmrc27 tmrc26 tmrc25 tmrc24 tmrc23 tmrc22 tmrc21 tmrc20 h'd11c tmrl1 w 8 8 tmr17 tmr16 tmr15 tmr14 tmr13 tmr12 tmr11 tmr10 h'd11d tmrl2 w 8 8 tmr27 tmr26 tmr25 tmr24 tmr23 tmr22 tmr21 tmr20 h'd11e tmrl3 w 8 8 tmr37 tmr36 tmr35 tmr34 tmr33 tmr32 tmr31 tmr30 h'd11f tmrcs r/w 8 8 tmri3e tm ri2e tmri1e tmri3 tmri2 tmri1 ? ? timer r h'd120 pwdrl w 8 8 pwdrl7 pwdrl6 pwdrl5 pwdrl4 pwdrl3 pwdrl2 pwdrl1 pwdrl0 h'd121 pwdru w 8 8 ? ? pwdru5 pwdru4 pwdru3 pwdru2 pwdru1 pwdru0 h'd122 pwcr r/w 8 8 ? ? ? ? ? ? ? pwmcr0 14-bit pwm h'd123 to h'd125 h'd126 pwr0 w 8 8 pw 07 pw06 pw05 pw04 pw03 pw02 pw01 pw00 h'd127 pwr1 w 8 8 pw17 pw16 pw15 pw14 pw13 pw12 pw11 pw10 h'd128 pwr2 w 8 8 pw 27 pw26 pw25 pw24 pw23 pw22 pw21 pw20 h'd129 pwr3 w 8 8 pw 37 pw36 pw35 pw34 pw33 pw32 pw31 pw30 h'd12a pw8cr r/w 8 8 ? ? ? ? pwc3 pwc2 pwc1 pwc0 8-bit pwm h'd12b h'd12c icr1 r 8 8 icr17 icr16 icr15 icr14 icr13 icr12 icr11 icr10 h'd12d pcsr r/w 8 8 icif icie iceg ncon/off ? dcs2 dcs1 dcs0 psu h'd12e to h'd12f h'd130 adrh r 16 8 adr9 adr8 adr7 adr6 adr5 adr4 adr3 adr2 h'd131 adrl adr1 adr0 ? ? ? ? ? ? h'd132 ahrh r 16 ahr9 ahr8 ahr7 ahr6 ahr5 ahr4 ahr3 ahr2 h'd133 ahrl ahr1 ahr0 ? ? ? ? ? ? h'd134 adcr r/w 8 ck ? hch1 hch0 sch3 sch2 sch1 sch0 h'd135 adcsr r/w 8 send hend adie sst hst busy scnl ? h'd136 adtsr r/w 8 ? ? ? ? ? ? trgs1 trgs0 a/d h'd137 h'd138 tlk w 8/16 16 tlr27 tlr26 tlr25 tlr24 tlr23 tlr22 tlr21 tlr20 h'd138 tck r 8/16 tdr27 tdr26 tdr 25 tdr24 tdr23 tdr22 tdr21 tdr20 h'd139 tlj w 8/16 tlr17 tlr16 tlr15 tlr14 tlr13 tlr12 tlr11 tlr10 h'd139 tcj r 8/16 tdr17 tdr16 tdr 15 tdr14 tdr13 tdr12 tdr11 tdr10 h'd13a tmj r/w 8/16 ps11 ps10 st 8/16 ps21 ps20 tgl t/r h'd13b tmjc r/w 8/16 16 buzz1 buzz0 mon1 mon0 exn tmj2ie tmj1ie ps22 h'd13c tmjs r/w 8/16 tmj2i tmj1i ? ? ? ? ? ? timer j h'd13d to h'd147 appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1013 of 1174 rej09b0329-0200 address * 1 register name r/w access bus width 7 6 5 4 3 2 1 0 module name h'd148 smr1 r/w 8 8 c/ a chr pe o/ e stop mp cks1 cks0 h'd149 brr1 r/w 8 h'd14a scr1 r/w 8 tie rie te re mpie teie cke1 cke0 h'd14b tdr1 r/w 8 h'd14c ssr1 r/w 8 tdre rdrf orer fer per tend mpb mpbt h'd14d rdr1 r 8 h'd14e scmr1 r/w 8 ? ? ? ? sdir sinv ? smif clock synchrono us/asynchr onous sci h'd14f to h'd157 h'd158 iccr1 r/w 8 8 ice ieic mst trs acke bbsy iric scp h'd159 icsr1 r/w 8 estp stop irtr aasx al aas adz ackb h'd15a to h'd15d h'd15e icdr1 * 3 r/w 8 8 icdr7 icdr6 icdr5 i cdr4 icdr3 icdr2 icdr1 icdr0 h'd15e sarx1 * 3 r/w 8 svax6 svax5 svax4 svax3 svax2 svax1 svax0 fsx h'd15f icmr1 * 3 r/w 8 mls wait cks2 cks1 cks0 bc2 bc1 bc0 h'd15f sar1 * 3 r/w 8 sva6 sva5 sva4 sva3 sva2 sva1 sva0 fs i 2 c interface h'd160 to h'd1ff h'd200 cline1 r/w 8/16 16 bptn1 sz1 clu11 clu12 kr1 kg1 kb1 klu1 osd h'd201 cline2 r/w 8/16 16 bptn2 sz2 clu21 clu22 kr2 kg2 kb2 klu2 h'd202 cline3 r/w 8/16 16 bptn3 sz3 clu31 clu32 kr3 kg3 kb3 klu3 h'd203 cline4 r/w 8/16 16 bptn4 sz4 clu41 clu42 kr4 kg4 kb4 klu4 h'd204 cline5 r/w 8/16 16 bptn5 sz5 clu51 clu52 kr5 kg5 kb5 klu5 h'd205 cline6 r/w 8/16 16 bptn6 sz6 clu61 clu62 kr6 kg6 kb6 klu6 h'd206 cline7 r/w 8/16 16 bptn7 sz7 clu71 clu72 kr7 kg7 kb7 klu7 h'd207 cline8 r/w 8/16 16 bptn8 sz8 clu81 clu82 kr8 kg8 kb8 klu8 h'd208 cline9 r/w 8/16 16 bptn9 sz9 clu91 clu92 kr9 kg9 kb9 klu9 h'd209 cline10 r/w 8/16 16 bptn10 sz10 clu101 clu102 kr10 kg10 kb10 klu10 h'd20a cline11 r/w 8/16 16 bptn11 sz11 clu111 clu112 kr11 kg11 kb11 klu11 h'd20b cline12 r/w 8/16 16 bptn12 sz12 clu121 clu122 kr12 kg12 kb12 klu12 h'd20c vposh r/w 8/16 16 ? ? ? ? vspc2 vspc1 vspc0 vp8 h'd20d vposl r/w 8/16 16 vp7 vp6 vp5 vp4 vp3 vp2 vp1 vp0 h'd20e hpos r/w 8/16 16 hp7 hp6 hp5 hp4 hp3 hp2 hp1 hp0 h'd20f dout r/w 8/16 16 ? rgbc ycoc dobc dsel crsel ? ? h'd210 dcntlh r/w 8/16 16 vdspon dispm lacem blks osdon ? edge edgc h'd211 dcntll r/w 8/16 16 br bg bb blu1 blu0 camp kamp bamp h'd212 dformh r/w 8/16 16 tvm2 tvm1 tvm0 fscin fscext ? osdve osdvf h'd213 dforml r/w 8/16 16 ? ? ? ? ? dtmv ldreq vacs h'd214 to h'd21f appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1014 of 1174 rej09b0329-0200 address * 1 register name r/w access bus width 7 6 5 4 3 2 1 0 module name h'd220 sevfd r/w 8/16 16 evnie evnif ? stbe4 stbe3 stbe2 stbe1 stbe0 data slicer h'd221 slvle2 slvle1 slvle0 dlye4 dlye3 dlye2 dlye1 dlye0 h'd222 sodfd r/w 8/16 oddie oddif ? stbo4 stbo3 stbo2 stbo1 stbo0 h'd223 slvl02 slvl01 slvl00 dlyo4 dlyo3 dlyo2 dlyo1 dlyo0 h'd224 sline1 r/w 8/16 senbl1 sfld1 ? sline14 sline13 sline12 sline11 sline10 h'd225 sline2 r/w 8/16 senbl2 sfld2 ? sline24 sline23 sline22 sline21 sline20 h'd226 sline3 r/w 8/16 senbl3 sfld3 ? sline34 sline33 sline32 sline31 sline30 h'd227 sline4 r/w 8/16 senbl4 sfld4 ? sline44 sline43 sline42 sline41 sline40 h'd228 sdtct1 r 8/16 crdf1 sbdf1 endf1 ? cric13 cric12 cric11 cric10 h'd229 sdtct2 r 8/16 crdf2 sbdf2 endf2 ? cric23 cric22 cric21 cric20 h'd22a sdtct3 r 8/16 crdf3 sbdf3 endf3 ? cric33 cric32 cric31 cric30 h'd22b sdtct4 r 8/16 crdf4 sbdf4 endf4 ? cric43 cric42 cric41 cric40 h'd22c sdata1 r 8/16 h'd22d h'd22e sdata2 r 8/16 h'd22f h'd230 sdata3 r 8/16 h'd231 h'd232 sdata4 r 8/16 h'd233 h'd234 to h'd23f h'd240 sepimr r/w 8 16 ccmpv1 ccmpv0 ccmpsl synct vsel dlpfon ? frqsel h'd241 sepcr r/w 8 afcvie afcvif vcksl vcmpon hcksel hhkon hhkon2 fld h'd242 sepacr r/w 8 ndetie ndetif hsel ? ? arst dotcks l dsl32b h'd243 hvthr w 8 ? ? ? hvth4 hvth3 hvth2 hvth1 hvth0 h'd244 vvthr w 8 vvth7 vvth6 vvth5 vvth4 vvth3 vvth2 vvth1 vvth0 h'd245 fwidr w 8 ? ? ? ? fwid3 fwid2 fwid1 fwid0 h'd246 hcmmr w 16 hc8 hc7 hc6 hc5 hc4 hc3 hc2 hc1 h'd247 hc0 hm6 hm5 hm4 hm3 hm2 hm1 hm0 ndetc r 8 nc7 nc6 nc5 nc4 nc3 nc2 nc1 nc0 h'd248 ndetr w 8 nr7 nr6 nr5 nr4 nr3 nr2 nr1 nr0 h'd249 ddetwr w 8 srwde1 srwde0 srwds1 srwds0 crwde1 crwde0 crwds1 crwds0 h'd24a infrqr w 8 vfs2 vfs1 hfs ? ? ? ? ? sync separator h'd24b to h'ffaf h'ffb0 tar0 r/w 8 8 a23 a22 a21 a20 a19 a18 a17 a16 atc h'ffb1 a15 a14 a13 a12 a11 a10 a9 a8 h'ffb2 a7 a6 a5 a4 a3 a2 a1 ? h'ffb3 tar1 r/w 8 a23 a22 a21 a20 a19 a18 a17 a16 h'ffb4 a15 a14 a13 a12 a11 a10 a9 a8 h'ffb5 a7 a6 a5 a4 a3 a2 a1 ? appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1015 of 1174 rej09b0329-0200 address * 1 register name r/w access bus width 7 6 5 4 3 2 1 0 module name h'ffb6 tar2 r/w 8 a23 a22 a21 a20 a19 a18 a17 a16 h'ffb7 a15 a14 a13 a12 a11 a10 a9 a8 h'ffb8 a7 a6 a5 a4 a3 a2 a1 ? h'ffb9 atcr r/w 8 ? ? ? ? ? trc2 trc1 trc0 atc h'ffba tma r/w 8 8 tmaov tmaie ? ? tma3 tma2 tma1 tma0 h'ffbb tca r 8 tca7 tca6 tca5 tca4 tca3 tca2 tca1 tca0 timer a h'ffbc wtcsr r/w 8/16 16 ovf wt/ it tme ? rst/ nmi cks2 cks1 cks0 h'ffbd wtcnt * 5 r/w 8/16 wdt h'ffbe to h'ffbf h'ffc0 pdr0 r 8 8 pdr07 pdr06 pdr05 pdr04 pdr03 pdr02 pdr01 pdr00 h'ffc1 pdr1 r/w 8 pdr17 pdr16 pdr15 pdr14 pdr13 pdr12 pdr11 pdr10 h'ffc2 pdr2 r/w 8 pdr27 pdr26 pdr25 pdr24 pdr23 pdr22 pdr21 pdr20 h'ffc3 pdr3 r/w 8 pdr37 pdr36 pdr35 pdr34 pdr33 pdr32 pdr31 pdr30 h'ffc4 pdr4 r/w 8 8 pdr47 pdr46 pdr45 pdr44 pdr43 pdr42 pdr41 pdr40 port data register h'ffc5 h'ffc6 pdr6 r/w 8 pdr67 pdr66 pdr65 pdr64 pdr63 pdr62 pdr61 pdr60 h'ffc7 pdr7 r/w 8 pdr77 pdr76 pdr75 pdr74 pdr73 pdr72 pdr71 pdr70 h'ffc8 pdr8 r/w 8 8 pdr87 pdr86 pdr85 pdr84 pdr83 pdr82 pdr81 pdr80 h'ffc9 to h'ffcc h'ffcd pmr0 r/w 8 8 pmr07 pmr06 pmr05 pmr04 pmr03 pmr02 pmr01 pmr00 h'ffce pmr1 r/w 8 pmr17 pmr16 pmr15 pmr14 pmr13 pmr12 pmr11 pmr10 port mode register h'ffcf h'ffd0 pmr3 r/w 8 8 pmr37 pmr36 pmr35 pmr34 pmr33 pmr32 pmr31 pmr30 h'ffd1 pcr1 w 8 8 pcr17 pcr16 pcr15 pcr14 pcr13 pcr12 pcr11 pcr10 h'ffd2 pcr2 w 8 pcr27 pcr26 pcr25 pcr24 pcr23 pcr22 pcr21 pcr20 port control register h'ffd3 pcr3 w 8 pcr37 pcr36 pcr35 pcr34 pcr33 pcr32 pcr31 pcr30 h'ffd4 pcr4 w 8 pcr47 pcr46 pcr45 pcr44 pcr43 pcr42 pcr41 pcr40 h'ffd5 h'ffd6 pcr6 w 8 8 pcr67 pcr66 pcr65 pcr64 pcr63 pcr62 pcr61 pcr60 h'ffd7 pcr7 w 8 pcr77 pcr76 pcr75 pcr74 pcr73 pcr72 pcr71 pcr70 h'ffd8 pcr8 w 8 pcr87 pcr86 pcr85 pcr84 pcr83 pcr82 pcr81 pcr80 h'ffd9 pmra r/w 8 8 pmra7 pmra6 ? ? ? ? ? ? h'ffda pmrb r/w 8 pmrb7 pmrb6 pmrb5 pmrb4 ? ? ? ? h'ffdb pmr4 r/w 8 pmr47 ? ? ? ? ? ? pmr40 h'ffdc h'ffdd pmr6 r/w 8 8 pmr67 pmr66 pmr65 pmr64 pmr63 pmr62 pmr61 pmr60 h'ffde pmr7 r/w 8 pmr77 pmr76 pmr75 pmr74 pmr73 pmr72 pmr71 pmr70 h'ffdf pmr8 r/w 8 pmr87 pmr86 pmr85 pmr84 pmr83 pmr82 pmr81 pmr80 h'ffe0 pmrc r/w 8 ? ? pmrc5 pmrc4 pmrc3 ? pmrc1 ? port mode register appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1016 of 1174 rej09b0329-0200 address * 1 register name r/w access bus width 7 6 5 4 3 2 1 0 module name h'ffe1 pur1 r/w 8 8 pur17 pur16 pur15 pur14 pur13 pur12 pur11 pur10 h'ffe2 pur2 r/w 8 pur27 pur26 pur25 pur24 pur23 pur22 pur21 pur20 h'ffe3 pur3 r/w 8 pur37 pur36 pur35 pur34 pur33 pur32 pur31 pur30 port pull- up select register h'ffe4 rtpegr r/w 8 ? ? ? ? ? ? rtpegr 1 rtpegr 0 h'ffe5 rtpsr1 r/w 8 rtpsr17 rtpsr16 rtpsr15 rtpsr14 rtpsr13 rtpsr12 rtpsr11 rtpsr10 h'ffe6 rtpsr2 r/w 8 rtpsr27 rtpsr26 rtpsr25 rtpsr24 ? ? ? ? realtime port h'ffe7 h'ffe8 syscr r/w 8 8 ? ? intm1 intm0 xrst ? ? ? h'ffe9 m dcr r 8 ? ? ? ? ? ? ? mds0 h'ffea sbycr r/w 8 ssby sts2 sts1 sts0 ? ? sck1 sck0 h'ffeb lpwrcr r/w 8 dton lson nesel ? ? ? sa1 sa0 h'ffec mstpcr h r/w 8 mstp15 mstp14 mstp13 mstp12 mstp11 mstp10 mstp9 mstp8 h'ffed mstpcr l r/w 8 mstp7 mstp6 mstp5 mstp4 mstp3 mstp2 mstp1 mstp0 h'ffee stcr r/w 8 ? iicx1 iicx0 ? flshe osrome ? ? system control register h'ffef h'fff0 iegr r/w 8 8 ? irq5eg irq4eg irq3eg irq2eg irq1eg irq0eg1 irq0eg0 irq edge h'fff1 ienr r/w 8 ? ? irq5e irq4e irq3e ir q2e irq1e irq0e irq enable h'fff2 irqr r/w 8 ? ? irq5f irq4f irq3f irq2f irq1f irq0f irq status h'fff3 icra r/w 8 icra7 icra6 i cra5 icra4 icra3 i cra2 icra1 icra0 h'fff4 icrb r/w 8 icrb7 icrb6 i crb5 icrb4 icrb3 i crb2 icrb1 icrb0 h'fff5 icrc r/w 8 icrc7 icrc6 icrc5 icrc4 icrc3 icrc2 icrc1 icrc0 irq priority control h'fff6 icrd r/w 8 icrd7 icrd6 icrd5 icrd4 i crd3 icrd2 icrd1 icrd0 h'fff7 ? ? ? ? ? ? ? ? ? ? ? ? h'fff8 flmcr1 r/w 8 8 fwe swe1 esu1 psu1 ev1 pv1 e1 p1 h'fff9 flmcr2 r/w 8 8 fler swe2 esu2 psu2 ev2 pv2 e2 p2 h'fffa ebr1 r/w 8 8 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 h'fffb ebr2 r/w 8 8 eb15 eb14 eb13 eb12 eb11 eb10 eb9 eb8 flash memory h'fffc ? ? ? ? ? ? ? ? ? ? ? ? h'fffd ? ? ? ? ? ? ? ? ? ? ? ? h'fffe ? ? ? ? ? ? ? ? ? ? ? ? h'ffff ? ? ? ? ? ? ? ? ? ? ? ? notes: 1. lower 16bits of the address. 2. assigned to the same address. 3. access varies depending on the ice bit. 4. ocra and ocrb address are the same, which can be switched by the ocsr bit in tocr. 5. the address is h'ffbc when written to. wtcnt and wtcsr are assigned to the same address. refer to section 17.2.4, notes on register access. appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1017 of 1174 rej09b0329-0200 b.2 function list h'd000 and h'd001: drum phase gain constant dgkp: drum digital filter bit initial value r/w * w 13 * w 14 * w 15 10 32 54 7 * w 6 * w 9 * w 8 * w 11 * w 10 * w * www ww ww 12 * * * * * * : : : dgkp15 dgkp14 dgkp13 dgkp12 dgkp11 dgkp10 dgkp9 dgkp8 dgkp7 dgkp6 dgkp5 dgkp4 dgkp3 dgkp2 dgkp1 dgkp0 h'd002 and h'd003: drum speed gain constant dgks: drum digital filter * w 13 * w 14 * w 15 10 32 54 7 * w 6 * w 9 * w 8 * w 11 * w 10 * w * www ww ww 12 * * * * * * dgks15 dgks14 dgks13 dgks12 dgks11 dgks10 dgks9 dgks8 dgks7 dgks6 dgks5 dgks4 dgks3 dgks2 dgks1 dgks0 bit initial value r/w : : : h'd004 and h'd005: drum phase coefficient a dap: drum digital filter * w 13 * w 14 * w 15 10 32 54 7 * w 6 * w 9 * w 8 * w 11 * w 10 * w * www ww ww 12 * * * * * * dap15 dap14 dap13 dap12 dap11 dap10 dap9 dap8 dap7 dap6 dap5 dap4 dap3 dap2 dap1 dap0 bit initial value r/w : : : h'd006 and h'd007: drum phase coefficient b dbp: drum digital filter * w 13 * w 14 * w 15 10 32 54 7 * w 6 * w 9 * w 8 * w 11 * w 10 * w * www ww ww 12 * * * * * * dbp15 dbp14 dbp13 dbp12 dbp11 dbp10 dbp9 dbp8 dbp7 dbp6 dbp5 dbp4 dbp3 dbp2 dbp1 dbp0 bit initial value r/w : : : h'd008 and h'd009: drum speed coefficient a das: drum digital filter * w 13 * w 14 * w 15 10 32 54 7 * w 6 * w 9 * w 8 * w 11 * w 10 * w * www ww ww 12 * * * * * * das15 das14 das13 das12 das11 das10 das9 das8 das7 das6 das5 das4 das3 das2 das1 das0 bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1018 of 1174 rej09b0329-0200 h'd00a and h'd00b: drum speed coeffici ent b dbs: drum digital filter * w 13 * w 14 * w 15 10 32 54 7 * w 6 * w 9 * w 8 * w 11 * w 10 * w * www ww ww 12 * * * * * * dbs15 dbs14 dbs13 dbs12 dbs11 dbs10 dbs9 dbs8 dbs7 dbs6 dbs5 dbs4 dbs3 dbs2 dbs1 dbs0 bit initial value r/w : : : h'd00c and h'd00d: drum phase offset dofp: drum digital filter * w 13 * w 14 * w 15 10 32 54 7 * w 6 * w 9 * w 8 * w 11 * w 10 * w * www ww ww 12 * * * * * * dofp15 dofp14 dofp13 dofp12 dofp11 dofp10 dofp9 dofp8 dofp7 dofp6 dofp5 dofp4 dofp3 dofp2 dofp1 dofp0 bit initial value r/w : : : h'd00e and h'd00f: capstan speed offset dofs: drum digital filter * w 13 * w 14 * w 15 10 32 54 7 * w 6 * w 9 * w 8 * w 11 * w 10 * w * www ww ww 12 * * * * * * dofs15 dofs14 dofs13 dofs12 dofs11 dofs10 dofs9 dofs8 dofs7 dofs6 dofs5 dofs4 dofs3 dofs2 dofs1 dofs0 bit initial value r/w : : : h'd010 and h'd011: capstan phase gain constant cgkp: capstan digital filter * w 13 * w 14 * w 15 10 32 54 7 * w 6 * w 9 * w 8 * w 11 * w 10 * w * www ww ww 12 * * * * * * cgkp15 cgkp14 cgkp13 cgkp12 cgkp11 cgkp10 cgkp9 cgkp8 cgkp7 cgkp6 cgkp5 cgkp4 cgkp3 cgkp2 cgkp1 cgkp0 bit initial value r/w : : : h'd012 and h'd013: capstan speed gain constant cgks: capstan digital filter * w 13 * w 14 * w 15 10 32 54 7 * w 6 * w 9 * w 8 * w 11 * w 10 * w * www ww ww 12 * * * * * * cgks15 cgks14 cgks13 cgks12 cgks11 cgks10 cgks9 cgks8 cgks7 cgks6 cgks5 cgks4 cgks3 cgks2 cgks1 cgks0 bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1019 of 1174 rej09b0329-0200 h'd014 and h'd015: capstan phase coefficient a cap: capstan digital filter * w 13 * w 14 * w 15 10 32 54 7 * w 6 * w 9 * w 8 * w 11 * w 10 * w * www ww ww 12 * * * * * * cap15 cap14 cap13 cap12 cap11 cap10 cap9 cap8 cap7 cap6 cap5 cap4 cap3 cap2 cap1 cap0 bit initial value r/w : : : h'd016 and h'd017: capstan phase coefficient b cbp: capstan digital filter * w 13 * w 14 * w 15 10 32 54 7 * w 6 * w 9 * w 8 * w 11 * w 10 * w * www ww ww 12 * * * * * * cbp15 cbp14 cbp13 cbp12 cbp11 cbp10 cbp9 cbp8 cbp7 cbp6 cbp5 cbp4 cbp3 cbp2 cbp1 cbp0 bit initial value r/w : : : h'd018 and h'd019: capstan speed coefficient a cas: capstan digital filter * w 13 * w 14 * w 15 10 32 54 7 * w 6 * w 9 * w 8 * w 11 * w 10 * w * www ww ww 12 * * * * * * cas15 cas14 cas13 cas12 cas11 cas10 cas9 cas8 cas7 cas6 cas5 cas4 cas3 cas2 cas1 cas0 bit initial value r/w : : : h'd01a and h'd01b: capstan speed coefficient b cbs: capstan digital filter * w 13 * w 14 * w 15 10 32 54 7 * w 6 * w 9 * w 8 * w 11 * w 10 * w * www ww ww 12 * * * * * * cbs15 cbs14 cbs13 cbs12 cbs11 cbs10 cbs9 cbs8 cbs7 cbs6 cbs5 cbs4 cbs3 cbs2 cbs1 cbs0 bit initial value r/w : : : h'd01c and h'd01d: capstan phase offset cofp: capstan digital filter * w 13 * w 14 * w 15 10 32 54 7 * w 6 * w 9 * w 8 * w 11 * w 10 * w * www ww ww 12 * * * * * * cofp15 cofp14 cofp13 cofp12 cofp11 cofp10 cofp9 cofp8 cofp7 cofp6 cofp5 cofp4 cofp3 cofp2 cofp1 cofp0 bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1020 of 1174 rej09b0329-0200 h'd01e and h'd01f: capstan speed offset cofs: capstan digital filter * w 13 * w 14 * w 15 10 32 54 7 * w 6 * w 9 * w 8 * w 11 * w 10 * w * www ww ww 12 * * * * * * cofs15 cofs14 cofs13 cofs12 cofs11 cofs10 cofs9 cofs8 cofs7 cofs6 cofs5 cofs4 cofs3 cofs2 cofs1 cofs0 bit initial value r/w : : : h'd020 and h'd021: drum system speed delay initialization register dzs: digital filter 1 ? 13 1 ? 14 1 ? 15 10 32 54 7 0 w 6 0 w 9 0 w 8 0 w 11 0 w 10 0 w 1 ? ww ww ww 12 0 0 0 0 0 0 dzs15 dzs14 dzs13 dzs12 dzs11 dzs10 dzs9 dzs8 dzs7 dzs6 dzs5 dzs4 dzs3 dzs2 dzs1 dzs0 bit initial value r/w : : : h'd022 and h'd023: drum system phase delay initialization register dzp: digital filter 1 ? 13 1 ? 14 1 ? 15 10 32 54 7 0 w 6 0 w 9 0 w 8 0 w 11 0 w 10 0 w 1 ? ww ww ww 12 0 0 0 0 0 0 dzp15 dzp14 dzp13 dzp12 dzp11 dzp10 dzp9 dzp8 dzp7 dzp6 dzp5 dzp4 dzp3 dzp2 dzp1 dzp0 bit initial value r/w : : : h'd024 and h'd025: capstan system speed delay initialization register czs: digital filter 1 ? 13 1 ? 14 1 ? 15 10 32 54 7 0 w 6 0 w 9 0 w 8 0 w 11 0 w 10 0 w 1 ? ww ww ww 12 0 0 0 0 0 0 czs15 czs14 czs13 czs12 czs11 czs10 czs9 czs8 czs7 czs6 czs5 czs4 czs3 czs2 czs1 czs0 bit initial value r/w : : : h'd026 and h'd027: capstan system phase delay initialization register czp: digital filter 1 ? 13 1 ? 14 1 ? 15 10 32 54 7 0 w 6 0 w 9 0 w 8 0 w 11 0 w 10 0 w 1 ?ww ww ww 12 0 0 0 0 0 0 czp15 czp14 czp13 czp12 czp11 czp10 czp9 czp8 czp7 czp6 czp5 czp4 czp3 czp2 czp1 czp0 bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1021 of 1174 rej09b0329-0200 h'd028: drum system digital filter control register dfic: digital filter 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 5 0 6 0 7 r/w r/w r/(w) dpha r/(w) * 1 drov dzpon dzson dsg2 dsg1 dsg0 1 notes: 1. only 0 can be written. 2. optional. drum system ran g e over fla g 0 filter computation result does not exceed 12 bits. (initial value) 1 filter computation result exceeds 12 bits. drum phase system filter computation start bit 0 phase system filter computation is off. (initial value) phase system computation result y is not added to es. 1 phase system filter computation is on drum phase system z -1 initialization bit 0 phase system z -1 does not reflect dzp value. (initial value) 1 phase system z -1 reflects dzp value drum speed system z -1 initialization bit 0 speed system z -1 does not reflect dzs value. (initial value) 1 speed system z -1 reflects dzs value. drum system g ain control bit dsg2 dsg1 dsg0 description 0 0 0 1 (initial value) 1 2 1 0 4 1 8 1 0 0 16 1 ( 32) * 2 1 0 ( 64) * 2 1 invalid (do not set) bit : initial value : r/w : ? ? appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1022 of 1174 rej09b0329-0200 h'd029: capstan system digital filter control register cfic: digital filter 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 5 0 6 0 7 r/w r/w r/(w) cpha r/(w) * 1 crov czpon czson csg2 csg1 csg0 1 notes: 1. only 0 can be written. 2. optional. capstan system ran g e over fla g 0 filter computation result does not exceed 12 bits. (initial value) 1 filter computation result exceeds 12 bits. capstan phase system filter computation start bit 0 phase system filter computation is off. (initial value) phase system computation result y is not added to es. 1 phase system filter computation is on. capstan phase system z -1 initialization bit 0 phase system z -1 does not reflect cz p value. (initial value) 1 phase system z -1 reflects cz p value. capstan speed system z -1 initialization bit 0 speed system z -1 does not reflect czs value. (initial value) 1 speed system z -1 reflects czs value. capstan system g ain control bit csg2 csg1 csg0 description 0 0 0 1 (initial value) 1 2 1 0 4 1 8 1 0 0 16 1 ( 32) * 2 1 0 ( 64) * 2 1 invalid (do not set) bit : initial value : r/w : ? ? appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1023 of 1174 rej09b0329-0200 h'd02a: digital filter control register dfucr: digital filter 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 5 0 6 7 r/w r/w r/w pton cp/dp cfeps dfeps cfess dfess 11 phase system computation result pwm output bit 0 output normal filter computation result to pwm pin. (initial value) 1 output only phase system computation result to pwm pin. pwm output select bit 0 output drum phase system computation result (cappwm) (initial value) 1 output capstan phase system computation result (drmpwm) drum phase system error data transfer bit 0 transfer data by hsw (nhsw) si g nal latch. (initial value) 1 transfer data at the time of error data write. capstan phase system error data transfer bit 0 transfer data by dvcfg2 si g nal latch. (initial value) 1 transfer data at the time of error data write. capstan speed system error data transfer bit 0 transfer data by dvcfg si g nal latch. (initial value) 1 transfer data at the time of error data write. drum speed system error data transfer bit 0 transfer data by ncdfg si g nal latch. (initial value) 1 transfer data at the time of error data write. bit : initial value : r/w : ?? ?? appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1024 of 1174 rej09b0329-0200 h'd030 and h'd031: specified dfg speed preset data register dfpr: drum speed error detector 0 w 13 0 w 14 0 w 15 10 32 54 7 0 w 6 0 w 9 0 w 8 0 w 11 0 w 10 0 w 0 www ww ww 12 0 0 0 0 0 0 dfpr15 dfpr14 dfpr13 dfpr12 dfpr11 dfpr10 dfpr9 dfpr8 dfpr7 dfpr6 dfpr5 dfpr4 dfpr3 dfpr2 dfpr1 dfpr0 bit initial value r/w : : : h'd032 and h'd033: dfg speed error data register dfer: drum speed error detector 0 * r/w 13 0 * r/w 14 0 * r/w 15 10 32 54 7 0 * r/w 6 0 * r/w 9 0 * r/w 8 0 * r/w 11 0 * r/w 10 0 * r/w 0 * r/w * r/w * r/w * r/w * r/w * r/w * r/w 12 0 0 0 0 0 0 dfer15 dfer14 dfer13 dfer12 dfer11 dfer10 dfer9 dfer8 dfer7 dfer6 dfer5 dfer4 dfer3 dfer2 dfer1 dfer0 bit initial value r/w : : : note: * only the detected error data can be read. h'd034 and h'd035: dfg lock upper data register dfrudr: drum speed error detector 1 w 13 1 w 14 0 w 15 10 32 54 7 1 w 6 1 w 9 1 w 8 1 w 11 1 w 10 1 w 1 www ww ww 12 1 1 1 1 1 1 dfrudr15 dfrudr14 dfrudr13 dfrudr12 dfrudr11 dfrudr10 dfrudr9 dfrudr8 dfrudr7 dfrudr6 dfrudr5 dfrudr4 dfrudr3 dfrudr2 dfrudr1 dfrudr0 bit initial value r/w : : : h'd036 and h'd037: dfg lock lower data register dfrldr: drum speed error detector 0 w 13 0 w 14 1 w 15 10 32 54 7 0 w 6 0 w 9 0 w 8 0 w 11 0 w 10 0 w 0 www ww ww 12 0 0 0 0 0 0 dfrldr15 dfrldr14 dfrldr13 dfrldr12 dfrldr11 dfrldr10 dfrldr9 dfrldr8 dfrldr7 dfrldr6 dfrldr5 dfrldr4 dfrldr3 dfrldr2 dfrldr1 dfrldr0 bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1025 of 1174 rej09b0329-0200 h'd038: drum speed error detection control register dfvcr: drum speed error detector 0 0 1 0 (r)/w * 2 2 0 r/w 3 0 4 0 r/w 0 r/(w) * 1 5 6 0 7 dfrfon df-r/unr dpcnt dfrcs1 dfrcs0 0 r/w dfcs1 (r)/w * 2 r r/w dfcs0 dfovf notes: clock source select bit dfcs1 dfcs0 0 0 s (initial value) 1 s/2 1 0 s/4 1 s/8 counter overflow fla g 0 normal status (initial value) 1 counter overflows. error data limit function select bit 0 limit function off (initial value) 1 limit function on drum lock fla g 0 drum speed system is not locked. (initial value) 1 drum speed system is locked. drum phase system filter computation auto start bit 0 filter computation by drum lock detection is not excuted. (initial value) 1 filter computation of phase system is executed at the time of drum lock detection. drum lock counter settin g bit dfrcs1 dfrcs0 description 0 0 underflow by 1 lock detection (initial value) 1 underflow by 2 lock detections 1 0 underflow by 3 lock detections 1 underflow by 4 lock detections description bit : initial value : r/w : 1. only 0 can be written. 2. when read, counter value is read. appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1026 of 1174 rej09b0329-0200 h'd039: drum phase error detection control register dpgcr: drum phase error detector 0 1 1 2 1 3 0 4 0 r/w 5 0 6 0 7 r/w r/(w) * dpovf r/w dpcs0 0 r/w dpcs1 n/v hswes 1 note: * only 0 can be written. error data latch si g nal select bit 0 hsw (videoff) si g nal (initial value) 1 nhsw (narrowff) si g nal ed g e select bit 0 latch at risin g ed g e (initial value) 1 latch at fallin g ed g e bit : initial value : r/w : clock source select bit dpcs1 dpcs0 0 0 s (initial value) 1 s/2 1 0 s/4 1 s/8 counter overflow fla g 0 normal status (initial value) 1 counter overflows. description ? ? ? ??? appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1027 of 1174 rej09b0329-0200 h'd03a and h'd03b: specified drum phase preset data register 2 dppr2: drum phase error detector 0 w 13 0 w 14 0 w 15 10 32 54 7 0 w 6 0 w 9 0 w 8 0 w 11 0 w 10 0 w 0 www ww ww 12 0 0 0 0 0 0 dppr15 dppr14 dppr13 dppr12 dppr11 dppr10 dppr9 dppr8 dppr7 dppr6 dppr5 dppr4 dppr3 dppr2 dppr1 dppr0 bit initial value r/w : : : h'd03c: specified drum phase preset data register 1 dppr1: drum phase error detector 0 0 1 0 w 2 0 w 3 0 4 1 5 1 6 1 7 w w 1 bit : initial value : r/w : ? ? ? ? dppr19 dppr18 dppr17 dppr16 ???? h'd03d: drum phase error data register 1 dper1: drum phase error detector 0 0 1 0 * r/w 2 0 * r/w 3 0 4 ? ? 1 5 ? ? 1 6 ? ? 1 7 ? ? * r/w * r/w 1 dper19 dper18 dper17 dper16 bit initial value r/w : : : note: * only the detected error data can be read. h'd03e and h'd03f: drum phase error data register 2 dper2: drum phase error detector 0 * r/w 13 0 * r/w 14 0 * r/w 15 10 32 54 7 0 * r/w 6 0 * r/w 9 0 * r/w 8 0 * r/w 11 0 * r/w 10 0 * r/w 0 * r/w * r/w * r/w * r/w * r/w * r/w * r/w 12 0 0 0 0 0 0 dper15 dper14 dper13 dper12 dper11 dper10 dper9 dper8 dper7 dper6 dper5 dper4 dper3 dper2 dper1 dper0 bit initial value r/w : : : note: * only the detected error data can be read. appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1028 of 1174 rej09b0329-0200 h'd050 and h'd051: specified cfg speed preset data register cfpr: capstan speed error detector 0 w 13 0 w 14 0 w 15 10 32 54 7 0 w 6 0 w 9 0 w 8 0 w 11 0 w 10 0 w 0 www ww ww 12 0 0 0 0 0 0 cfpr15 cfpr14 cfpr13 cfpr12 cfpr11 cfpr10 cfpr9 cfpr8 cfpr7 cfpr6 cfpr5 cfpr4 cfpr3 cfpr2 cfpr1 cfpr0 bit initial value r/w : : : h'd052 and h'd053: cfg speed error data register cfer: capstan speed error detector 0 * r/w 13 0 * r/w 14 0 * r/w 15 10 32 54 7 0 * r/w 6 0 * r/w 9 0 * r/w 8 0 * r/w 11 0 * r/w 10 0 * r/w 0 * r/w * r/w * r/w * r/w * r/w * r/w * r/w 12 0 0 0 0 0 0 cfer15 cfer14 cfer13 cfer12 cfer11 cfer10 cfer9 cfer8 cfer7 cfer6 cfer5 cfer4 cfer3 cfer2 cfer1 cfer0 bit initial value r/w : : : note: * only the detected error data can be read. h'd054 and h'd055: cfg lock upper data register cfrudr: capstan speed error detector 1 w 13 1 w 14 0 w 15 10 32 54 7 1 w 6 1 w 9 1 w 8 1 w 11 1 w 10 1 w 1 www ww ww 12 1 1 1 1 1 1 cfrudr15 cfrudr14 cfrudr13 cfrudr12 cfrudr11 cfrudr10 cfrudr9 cfrudr8 cfrudr7 cfrudr6 cfrudr5 cfrudr4 cfrudr3 cfrudr2 cfrudr1 cfrudr0 bit initial value r/w : : : h'd056 and h'd057: cfg lock lower data register cfrldr: capstan speed error detector 0 w 13 0 w 14 1 w 15 10 32 54 7 0 w 6 0 w 9 0 w 8 0 w 11 0 w 10 0 w 0 www ww ww 12 0 0 0 0 0 0 cfrldr15 cfrldr14 cfrldr13 cfrldr12 cfrldr11 cfrldr10 cfrldr9 cfrldr8 cfrldr7 cfrldr6 cfrldr5 cfrldr4 cfrldr3 cfrldr2 cfrldr1 cfrldr0 bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1029 of 1174 rej09b0329-0200 h'd058: capstan speed error detection control register cfvcr: capstan speed error detector 0 0 1 0 (r)/w * 2 2 0 r/w 3 0 4 0 r/w 0 r/(w) * 1 5 6 0 7 cfrfon cf-r/unr cpcnt cfrcs1 cfrcs0 0 r/w cfcs1 (r)/w * 2 r r/w cfcs0 cfovf notes: capstan phase system filter computation auto start bit 0 filter computation by capstan lock detection is not excuted. (initial value) 1 filter computation of phase system is executed at the time of drum lock detection. bit : initial value : r/w : capstan lock counter settin g bit cfrcs1 cfrcs0 description 0 0 underflow by 1 lock detection (initial value) 1 underflow by 2 lock detections 1 0 underflow by 3 lock detections 1 underflow by 4 lock detections clock source select bit cfcs1 cfcs0 0 0 s (initial value) 1 s/2 1 0 s/4 1 s/8 counter overflow fla g 0 normal status (initial value) 1 counter overflows. error data limit function select bit 0 limit function off (initial value) 1 limit function on capstan lock fla g 0 capstan speed system is not locked. (initial value) 1 capstan speed system is locked. description 1. only 0 can be written. 2. when read, counter value is read. appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1030 of 1174 rej09b0329-0200 h'd059: capstan phase error detection control register cpgcr: capstan phase error detector 0 1 1 2 1 3 0 4 0 r/w 5 0 6 0 7 r/w r/(w) * cpovf r/w cpcs0 0 r/w cpcs1 cr/rf selcfg2 1 note: * only 0 can be written. preset si g nal select bit 0 preset by ref30p si g nal (initial value) 1 preset by cref si g nal preset, latch si g nal select bit 0 preset by capref30 si g nal and latch by dvctl si g nal (initial value) 1 preset by ref30p (cref) si g nal and latch by dvcfg2 si g nal bit : initial value : r/w : clock source select bit cpcs1 cpcs0 0 0 s (initial value) 1 s/2 1 0 s/4 1 s/8 counter overflow fla g 0 normal status (initial value) 1 counter overflows. description ??? ??? appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1031 of 1174 rej09b0329-0200 h'd05a and h'd05b: specified capsta n phase preset data register 2 cppr2: capstan phase error detector 0 w 13 0 w 14 0 w 15 10 32 54 7 0 w 6 0 w 9 0 w 8 0 w 11 0 w 10 0 w 0 www ww ww 12 0 0 0 0 0 0 cppr15 cppr14 cppr13 cppr12 cppr11 cppr10 cppr9 cppr8 cppr7 cppr6 cppr5 cppr4 cppr3 cppr2 cppr1 cppr0 bit initial value r/w : : : h'd05c: specified capstan phas e preset data register 1 cppr1: capstan phase error detector 0 0 1 0 w 2 0 w 3 0 4 ? ? 1 5 ? ? 1 6 ? ? 1 7 ? ? w w 1 cppr19 cppr18 cppr17 cppr16 bit initial value r/w : : : h'd05d: capstan phase error data register 1 cper1: capstan phase error detector 0 0 1 0 r/w * 2 0 r/w * 3 0 4 ? ? 1 5 ? ? 1 6 ? ? 1 7 ? ? r/w * r/w * 1 bit note: * only the detected error data can be read. initial value r/w : : : cper19 cper18 cper17 cper16 h'd05e and h'd05f: capstan phase error data register 2 cper2: capstan phase error detector 0 r/w * 13 0 r/w * 14 0 r/w * 15 10 32 54 7 0 r/w * 6 0 r/w * 9 0 r/w * 8 0 r/w * 11 0 r/w * 10 0 r/w * 0 r/w * r/w * r/w * r/w * r/w * r/w * r/w * 12 0 0 0 0 0 0 cper15 cper14 cper13 cper12 cper11 cper10 cper9 cper8 cper7 cper6 cper5 cper4 cper3 cper2 cper1 cper0 bit note: * only the detected error data can be read. initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1032 of 1174 rej09b0329-0200 h'd060: hsw mode register 1 hsm1: hsw timing generator 0 0 1 0 r/w 2 0 r/(w) * 3 0 4 1 r 1 r 5 6 0 7 empa ovwb ovwa clrb clra 0 r flb r/w r/(w) * r fla empb note: * only 0 can be written. fifo2 full fla g 0 fifo2 is not full (initial value) 1 fifo2 is full fifo1 full fla g 0 fifo1 is not full (initial value) 1 fifo1 is full fifo2 empty fla g 0 data remains in fifo2 1 fifo2 is empty (initial value) fifo1 empty fla g 0 data remains in fifo1 1 fifo1 is empty (initial value) fifo2 overwrite fla g 0 normal operation (initial value) 1 data is written to fifo2 while it is full. write 0 to clear the fla g . fifo1 overwrite fla g 0 normal operation (initial value) 1 data is written to fifo1 while it is full. write 0 to clear the fla g . fifo2 pointer clear 0 normal operation (initial value) 1 clear fifo2 pointer fifo1 pointer clear 0 normal operation (initial value) 1 clear fifo1 pointer bit : initial value : r/w : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1033 of 1174 rej09b0329-0200 h'd061: hsw mode register 2 hsm2: hsw timing generator 0 0 1 0 r 2 0 r/w 3 0 4 0 r/w 0 r/w 5 6 0 7 edg isel1 sofg ofg vff/nff 0 r/w frt r/w r/w r/w fgr20ff lop free-run bit 0 5-bit dfg counter and 16-bit timer counter (initial value) 1 16-bit frc frg2 clear stop bit 0 16-bit timer counter clearin g by dfg reference re g ister 2 is enabled (initial value) 1 16-bit timer counter clearin g by dfg reference re g ister 2 is disabled mode select bit 0 si g nal mode (initial value) 1 loop mode dfg ed g e select bit 0 calculated by dfg risin g ed g e (initial value) 1 calculated by dfg fallin g ed g e interrupt select bit 0 interrupt request is g enerated by risin g of fifo strig si g nal (initial value) 1 interrupt request is g enerated by fifo match si g nal fifo output g roup select bit 0 20-sta g e output by fifo1 and fifo2 (initial value) 1 10-sta g e output by fifo1 only output fifo g roup fla g 0 outputtin g pattern by fifo1 (initial value) 1 outputtin g pattern by fifo2 videoff/nallowff output switchover bit 0 videoff output (initial value) 1 narrowff output bit : initial value : r/w : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1034 of 1174 rej09b0329-0200 h'd062: hsw loop stage setting register hslp: hsw timing generator 0 * 1 * r/w 2 * r/w 3 * 4 * r/w 5 * 6 * 7 r/w r/w r/w lob1 r/w lob2 * r/w lob3 lob0 loa3 loa2 loa1 loa0 fifo1 stage setting bit hsm2 hslp description bit 5 bit 3 bit 2 bit 1 bit 0 lop loa3 loa2 loa1 loa0 0 single mode (initial value) 1 0 0 0 0 output stage 0 of fifo1 1 output stage 0 and 1 of fifo1 1 0 output stage 0 to 2 of fifo1 1 output stage 0 to 3 of fifo1 1 0 0 output stage 0 to 4 of fifo1 1 output stage 0 to 5 of fifo1 1 0 output stage 0 to 6 of fifo1 1 output stage 0 to 7 of fifo1 1 0 0 0 output stage 0 to 8 of fifo1 1 output stage 0 to 9 of fifo1 1 0 setting disabled 1 1 0 0 1 1 0 1 legend: * don't care. fifo2 stage setting bit hsm2 hslp description bit 5 bit 7 bit 6 bit 5 bit 4 lop lob3 lob2 lob1 lob0 0 single mode (initial value) 1 0 0 0 0 output stage 0 of fifo2 1 output stage 0 and 1 of fifo2 1 0 output stage 0 to 2 of fifo2 1 output stage 0 to 3 of fifo2 1 0 0 output stage 0 to 4 of fifo2 1 output stage 0 to 5 of fifo2 1 0 output stage 0 to 6 of fifo2 1 output stage 0 to 7 of fifo2 1 0 0 0 output stage 0 to 8 of fifo2 1 output stage 0 to 9 of fifo2 1 0 setting disabled 1 1 0 0 1 1 0 1 legend: * don't care. bit initial value r/w : : : ** * * ** * * appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1035 of 1174 rej09b0329-0200 h'd064 and h'd065: fifo output pattern register 1 fpdra: hsw timing generator 8 * 9 * w 10 * w 11 * 12 * w * w 13 14 * 15 narrowffa vffa affa vpulsea mlevela 1 w mlevela bit used for generating an additional v signal. for details, refer to section 26.12, additional v signal generator. vpulsea bit used for generating an additional v signal. for details, refer to section 26.12, additional v signal generator. audioffa bit controls the audio head. videoffa bit controls the video head. narrowffa bit controls the narrow video head. a/d trigger a bit indicates a hardware trigger signal for the a/d converter. reserved cannot be read or modified s-triga bit indicates a signal that generates an interrupt. when the striga is selected by the isel, modifying this bit from 0 to 1 generates an interrupt. mlevela bit used for generating an additional v signal. for details, refer to section 26.12, additional v signal generator. vpulsea bit used for generating an additional v signal. for details, refer to section 26.12, additional v signal generator. audioffa bit controls the audio head. videoffa bit controls the video head. narrowffa bit controls the narrow video head. a/d trigger a bi indicates a hardware trigger signal for the a/d converter. reserved cannot be read or modified s-triga bit indicates a signal that generates an interrupt. when the striga is selected by the isel, modifying this bit from 0 to 1 generates an interrupt. w w adtrga striga bit initial value r/w bit initial value r/w 0 * 1 * w 2 * w 3 * 4 * w * w 5 6 * 7 ppga4 ppga3 ppga2 ppga1 ppga0 * w ppga7 w w w ppga6 ppga5 : : : : : : ppg output signal a bits used for outputting a timing control signal from port 7 (ppg). appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1036 of 1174 rej09b0329-0200 h'd066 and h'd067: fifo timing pattern register 1 ftpra * : hsw timing generator 8 * 9 * w 10 * w 11 * 12 * w * w 13 14 * 15 ftpra12 ftpra11 ftpra10 ftpra9 ftpra8 w w w * w ftpra14 ftpra15 ftpra13 bit initial value r/w : : : 0 * 1 * w 2 * w 3 * 4 * w * w 5 6 * 7 ftpra4 ftpra3 ftpra2 ftpra1 ftpra0 w w w * w ftpra6 ftpra7 ftpra5 bit initial value r/w : : : note: * ftpra and ftctr are assigned to the same address. h'd066 and h'd067: fifo timer capture register 1 ftctr * : hsw timing generator 8 9 10 11 12 13 14 15 ftctr12 ftctr11 ftctr10 ftctr9 ftctr8 ftctr14 ftctr15 ftctr13 bit initial value r/w : : : 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 1 2 3 4 5 6 7 ftctr4 ftctr3 ftctr2 ftctr1 ftctr0 ftctr6 ftctr7 ftctr5 bit initial value note: * ftpra and ftctr are assigned to the same address. r/w : : : 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1037 of 1174 rej09b0329-0200 h'd068 to h'd069: fifo output pattern register 2 fpdrb: hsw timing generator 8 * 9 * w 10 * w 11 * 12 * w * w 13 14 * 15 ? 1 ? narrowffb vffb affb vpulseb mlevelb w w w adtrgb strigb 0 * 1 * w 2 * w 3 * 4 * w * w 5 6 * 7 ppgb4 ppgb3 ppgb2 ppgb1 ppgb0 * ppgb7 w w w w ppgb6 ppgb5 : : : : : : bit initial value r/w bit initial value r/w ppg output signal b bits (ppgb7 to ppgb0) used for outputting a timing control signal from port 7 (ppg). legend: * don't care. mlevelb bit used for generating an additional v signal. for details, refer to section 26.12, additional v signal generator. vpulseb bit used for generating an additional v signal. for details, refer to section 26.12, additional v signal generator. audioffb bit controls the audio head. videoffb bit controls the video head. narrowffb bit controls the narrow video head. a/d trigger b bit indicates a hardware trigger signal for the a/d converter. reserved cannot be read or modified s-trigb bit indicates a signal that generates an interrupt. when the striga is selected by the isel, modifying this bit from 0 to 1 generates an interrupt. appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1038 of 1174 rej09b0329-0200 h'd06a and h'd06b: fifo timing pattern register 2 ftprb: hsw timing generator 8 * 9 * w 10 * w 11 * 12 * w * w 13 14 * 15 ftprb12 ftprb11 ftprb10 ftprb9 ftprb8 w w w * w ftprb14 ftprb15 ftprb13 bit initial value r/w : : : 0 * 1 * w 2 * w 3 * 4 * w * w 5 6 * 7 ftprb4 ftprb3 ftprb2 ftprb1 ftprb0 w w w * w ftprb6 ftprb7 ftprb5 bit initial value r/w : : : h'd06c: dfg reference register 1 dfcra * : hsw timing generator 0 * 1 * w 2 * w 3 * 4 * w 0 w 5 6 0 7 dfcra4 dfcra3 dfcra2 dfcra1 dfcra0 0 w isel2 w w w cclr cksl interrupt select bit 0 interrupt request is generated by clear signal of 16-bit timer counter (initial value) 1 interrupt request is generated by vd signal in pb mode dfg counter clear bit 0 normal operation (initial value) 1 5-bit dfg counter is cleared 16-bit counter clock source select bit 0 s/4 (initial value) 1 s/8 bit initial value r/w : : : fifo1 output timing setting bits (dfcra4 to dfcra0) these bits determine the start point of fifo1 timing. legend: * don't care. appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1039 of 1174 rej09b0329-0200 h'd06c: dfg reference count register dfctr * : hsw timing generator 0 * 1 * r 2 * r 3 * 4 * r 5 6 1 7 dfctr4 dfctr3 dfctr2 dfctr1 dfctr0 r r 11 ??? ??? note: * dfcra and dfctr are assigned to the same address. bit initial value r/w : : : dfg pulse count bits (dfctr4 to dfctr0) these bits count dfg pulses. h'd06d: dfg reference register 2 dfcrb: hsw timing generator 0 * 1 * w 2 * w 3 * 4 * w 5 6 1 7 dfcrb4 dfcrb3 dfcrb2 dfcrb1 dfcrb0 w w 11 ??? ??? bit initial value r/w : : : fifo2 output timing setting bits (dfcrb4 to dfcrb0) these bits determine the start point of fifo2 timing. legend: * don't care. appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1040 of 1174 rej09b0329-0200 h'd06e: special playback control register chcr: 4-head special playback circuit 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 hah sig3 sig2 sig1 sig0 0 w v/n w w w hswpol crh hsw output signal select bit 0 videoff signal output (initial value) 1 nallow ff signal output comp polarity select bit 0 positive (initial value) 1 negative c.rotary synchronization control bit 0 synchronous (initial value) 1 asynchronous h.ampsw synchronization control bit 0 synchronous (initial value) 1 asynchronous signal control bits sig3 sig2 sig1 sig0 output pin c.rotary h.amp sw 0 0 l l (initial value) 1 0 0 hsw l 1 hsw h 1 0 l hsw 1 h hsw 1 0 0 hsw ex-or comp comp 1 hsw ex-nor comp comp 1 0 hsw ex-or rtp0 rtp0 1 hsw ex-nor rtp0 rtp0 legend: * don't care. bit : initial value : r/w : * * * appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1041 of 1174 rej09b0329-0200 h'd06f: additional v control register addvr: additional v signal generator 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 5 1 6 7 r/w r/w hmsk hi-z cut vpom pol 11 legend : * don't care. osch mask bit 0 osch added (initial value) 1 osch not added high impedance bit 0 3-level output from vpulse pin (initial value) 1 vpulse pin is set as 3-state (h/l/hi-z) pin additional v output control bits cut vpon pol description 0 0 low level (initial value) 1 0 negative polarity 1 positive polarity 1 0 immediate level (high-impedance when hi-z bit = 1) 1 high level ??? ??? bit initial value r/w : : : * * h'd070 and h'd071: x-value data register xdr: x-value, trk-value adjustment circuit 1 13 1 14 1 15 10 32 54 7 0 w 6 0 w 9 0 w 8 0 w 11 0 w 10 0 w 1 ww ww ww 12 xd1 xd0 xd3 xd2 xd5 xd4 xd7 xd6 xd9 xd8 xd11 xd10 0 0 0 0 0 0 bit initial value r/w : : : ???? ???? h'd072 and h'd073: trk-value data register trdr: x-value, trk-value adjustment circuit 1 13 1 14 1 15 10 32 54 7 0 w 6 0 w 9 0 w 8 0 w 11 0 w 10 0 w 1 ww ww ww 12 trd1 trd0 trd3 trd2 trd5 trd4 trd7 trd6 trd9 trd8 trd11 trd10 0 0 0 0 0 0 : : : bit initial value r/w ???? ???? appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1042 of 1174 rej09b0329-0200 h'd074: x-value/trk-value control register xtcr: x-value, trk-value adjustment circuit 0 0 1 0 r/w 2 0 w 3 0 4 0 w 5 0 6 0 7 r/w w w at/mu w caprf trk/x exc/ref xcs dvref1 dvref0 1 capstan phase adjustment auto/manual select bit 0 manual mode (initial value) 1 auto mode external sync signal edge select bit 0 generated at excap rising edge (initial value) 1 generated at excap rising and falling edge capstan phase adjustment register select bit 0 capref30 is generated only by xdr setting value (initial value) 1 capref30 is generated by xdr and trdr setting values reference signal select bit 0 generated by ref30p signal (initial value) 1 generated by external referece signal clock source select bit 0 s (initial value) 1 s/2 ref30p frequency division rate select bit dvref1 dvref0 description 0 0 1-division (initial value) 1 2-division 1 0 3-division 1 4-division ? ? bit initial value r/w : : : h'd078: drum 12-bit pwm data register dpwdr: drum 12-bit pwm 1 0 r/w dpwdr1 0 0 r/w dpwdr0 3 0 r/w dpwdr3 2 0 r/w dpwdr2 5 0 r/w dpwdr5 4 0 r/w dpwdr4 7 0 r/w dpwdr7 6 0 r/w dpwdr6 9 0 r/w dpwdr9 8 0 r/w dpwdr8 11 0 r/w dpwdr11 10 0 r/w dpwdr10 12 1 13 1 14 1 15 1 : : : bit initial value r/w ???? ???? appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1043 of 1174 rej09b0329-0200 h'd07a: drum 12-bit pwm control registor dpwcr: drum 12-bit pwm 0 0 1 1 w 2 0 w 3 0 4 0 w 0 w 5 6 1 7 dh/l dsf/df dck2 dck1 dck0 0 w dpol w w w ddc dhiz positive polarity output (initial value) negative polarity output 0 1 polarity switchover bit fixed output bit, pwm pin output bit 0 1 0 low level output from pwm pin (initial value) dhiz dh/l ddc description 1 high level output form pwm pin 1 0 * high impedance from pwm pin ** pwm modulated signal output legend: * don't care. modulate error data from digital filter circuit (initial value) modulate data written in data register 0 1 output data select bit note: when pwms output data from the digital filter circuit, the data consisting of the speed and phase filtering results are modulated by pwms and output from the drmpwm pin. however, it is possible to output only capstan phase filter result from drmpwm pin, by dfucr settings of the digital filter circuit. see the section explaining the digital filter computation circuit. carrier frequency select bits description 0 0 0 carrier frequency is /2 dck1 dck0 dck2 1 carrier frequency is /4 1 0 carrier frequency is /8 (initial value) 1 carrier frequency is /16 0 1 0 carrier frequency is /32 1 carrier frequency is /64 1 0 carrier frequency is /128 1 (do not set) bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1044 of 1174 rej09b0329-0200 h'd07b: capstan 12-bit pwm control register cpwcr: capstan 12-bit pwm 0 0 1 1 w 2 0 w 3 0 4 0 w 0 w 5 6 1 7 ch/l csf/df cck2 cck1 cck0 0 w cpol w w w cdc chiz positive polarity (initial value) negative polarity output 0 1 polarity switchover bit fixed output bit, pwm pin output bit 0 1 0 low level output from pwm pin (initial value) chiz ch/l cdc description 1 high level output form pwm pin 1 0 * high impedance from pwm pin ** pwm modulated signal output legend: * don't care. modulate error data from digital filter circuit (initial value) modulate data written in data register 0 1 output data select bit note: when pwms output data from the digital filter circuit, the data consisting of the speed and phase filtering results are modulated by pwms and output from the cappwm pin. however, it is possible to output only drum phase filter results from cappwm pin, by dfucr settings of the digital filter circuit. see the section 26.11, digital filters, explaining the digital filter computation circuit. carrier frequency select bits description 0 0 0 carrier frequency is /2 cck1 cck0 cck2 1 carrier frequency is /4 1 0 carrier frequency is /8 (initial value) 1 carrier frequency is /16 0 1 0 carrier frequency is /32 1 carrier frequency is /64 1 0 carrier frequency is /128 1 (do not set) bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1045 of 1174 rej09b0329-0200 h'd07c: capstan 12-bit pwm data register cpwdr: capstan 12-bit pwm 1 0 r/w cpwdr1 0 0 r/w cpwdr0 3 0 r/w cpwdr3 2 0 r/w cpwdr2 5 0 r/w cpwdr5 4 0 r/w cpwdr4 7 0 r/w cpwdr7 6 0 r/w cpwdr6 9 0 r/w cpwdr9 8 0 r/w cpwdr8 11 0 r/w cpwdr11 10 0 r/w cpwdr10 12 1 13 1 14 1 15 1 : : : bit initial value r/w ???? ???? h'd080: ctl control register ctcr: ctl circuit 0 0 1 0 r 2 0 w 3 0 4 1 w 5 1 6 0 7 w w w fslb w fslc 0 w nt/pl fsla ccs lctl unctl slwm ntsc/pal select bit 0 ntsc mode (frame rate: 30 hz) (initial value) 1 pal mode (frame rate: 25 hz) long ctl bit 0 clock source (ccs) operates at the setting value (initial value) 1 clock source (ccs) operates for further 8-division after operating at the setting value ctl undetected bit 0 detected (initial value) 1 undetected mode select bit 0 normal mode (initial value) 1 slow mode clock source select bit 0 s (initial value) 1 s/2 operating frequency select bits fslc fslb fsla description 0 0 0 reserved (do not set) 1 reserved (do not set) 1 0 fosc = 8 mhz 1 fosc = 10 mhz (initial value) 1 reserved (do not set) legend : * don't care. bit initial value r/w : : : * * appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1046 of 1174 rej09b0329-0200 h'd081: ctl mode register ctlm: ctl circuit 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 5 0 6 0 7 r/w r/w r/w fw/rv r/w rec/ pb 0 r/w asm md4 md3 md2 md1 md0 note: * refer to the description of the ctl mode register in section 26.13.5, register description. asm rec/ pb description 0 0 playback mode (initial value) 1 record mode 1 0 assemble mode 1 invalid (do not set) direction bit 0 forward (initial value) 1 reverse ctl mode select bits * bit initial value r/w : : : record /playback mode bits appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1047 of 1174 rej09b0329-0200 h'd082 and h'd083: rec-ctl duty da ta register 1 rcdr1: ctl circuit 1111 13 14 15 10 32 54 76 98 11 10 cmt11 w 12 0 cmt10 w 0 cmt13 w 0 cmt12 w 0 cmt15 w 0 cmt14 w 0 cmt17 w 0 cmt16 w 0 cmt19 w 0 cmt18 w 0 cmt1b w 0 cmt1a w 0 : : : bit initial value r/w ???? ???? h'd084 and h'd085: rec-ctl duty da ta register 2 rcdr2: ctl circuit 1111 13 14 15 10 32 54 76 98 11 10 cmt21 w 12 0 cmt20 w 0 cmt23 w 0 cmt22 w 0 cmt25 w 0 cmt24 w 0 cmt27 w 0 cmt26 w 0 cmt29 w 0 cmt28 w 0 cmt2b w 0 cmt2a w 0 : : : bit initial value r/w ???? ???? h'd086 and h'd087: rec-ctl duty da ta register 3 rcdr3: ctl circuit 1111 13 14 15 10 32 54 76 98 11 10 cmt31 w 12 0 cmt30 w 0 cmt33 w 0 cmt32 w 0 cmt35 w 0 cmt34 w 0 cmt37 w 0 cmt36 w 0 cmt39 w 0 cmt38 w 0 cmt3b w 0 cmt3a w 0 : : : bit initial value r/w ???? ???? h'd088 and h'd089: rec-ctl duty da ta register 4 rcdr4: ctl circuit 1111 13 14 15 10 32 54 76 98 11 10 cmt41 w 12 0 cmt40 w 0 cmt43 w 0 cmt42 w 0 cmt45 w 0 cmt44 w 0 cmt47 w 0 cmt46 w 0 cmt49 w 0 cmt48 w 0 cmt4b w 0 cmt4a w 0 : : : bit initial value r/w ???? ???? h'd08a and h'd08b: rec-ctl duty data register 5 rcdr5: ctl circuit 1111 13 14 15 10 32 54 76 98 11 10 cmt51 w 12 0 cmt50 w 0 cmt53 w 0 cmt52 w 0 cmt55 w 0 cmt54 w 0 cmt57 w 0 cmt56 w 0 cmt59 w 0 cmt58 w 0 cmt5b w 0 cmt5a w 0 bit : initial value : r/w : ???? ???? appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1048 of 1174 rej09b0329-0200 h'd08c: duty i/o regist er di/o: ctl circuit 0 1 1 0 r/(w) * 1 2 0 w 3 0 4 5 1 6 7 r/w w w vctr0 1 w vctr1 1 w vctr2 bpon bps bpf di/o 1 notes: 1. only 0 can be written. 2. refer to the description of the duty i/o register in section 26.13.5, register description. bit pattern detection on/off bit 0 bit pattern detection off (initial value) 1 bit pattern detection on bit pattern detection start bit 0 normal status (initial value) 1 starts 8-bit bit pattern detection duty i/o register * 2 bit pattern detection flag 0 bit pattern (8 bit) is not detected (initial value) 1 bit pattern (8 bit) is detected vctr2 vctr1 vctr0 description 0 0 0 number of 1-pulse for detection = 2 1 number of 1-pulse for detection = 4 (sync mark) 1 0 number of 1-pulse for detection = 6 1 number of 1-pulse for detection = 8 (mark a, short) 1 0 0 number of 1-pulse for detection = 12 (mark a, long) 1 number of 1-pulse for detection = 16 1 0 number of 1-pulse for detection = 24 (mark b) 1 number of 1-pulse for detection = 32 (initial value) viss interrupt setting bits ? ? bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1049 of 1174 rej09b0329-0200 h'd08d: bit pattern regi ster btpr: ctl circuit 0 1 1 1 r * /w 2 1 r * /w 3 1 4 5 1 6 7 r * /w r * /w r * /w lsp5 1 r * /w lsp4 1 r * /w lsp6 1 r * /w lsp7 lsp3 lsp2 lsp1 lsp0 note: * writes are disabled during bit pattern detection. bit initial value r/w : : : h'd090 and h'd091: reference frequency regi ster 1 rfd: reference signal generator 15 1 ref15 w 14 1 ref14 w 13 1 ref13 w 12 1 ref12 w 11 1 ref11 w 10 1 ref10 w 9 1 ref9 w 8 1 ref8 w 7 1 ref7 w 6 1 ref6 w 5 1 ref5 w 4 1 ref4 w 3 1 ref3 w 2 1 ref2 w 1 1 ref1 w 0 1 ref0 w bit : initial value : r/w : h'd092 and h'd093: reference frequency re gister 2 crf: reference signal generator 15 1 crf15 w 14 1 crf14 w 13 1 crf13 w 12 1 crf12 w 11 1 crf11 w 10 1 crf10 w 9 1 crf9 w 8 1 crf8 w 7 1 crf7 w 6 1 crf6 w 5 1 crf5 w 4 1 crf4 w 3 1 crf3 w 2 1 crf2 w 1 1 crf1 w 0 1 crf0 w bit : initial value : r/w : h'd094 and h'd095: ref30 counter regist er rfc: reference signal generator 15 0 rfc15 14 0 rfc14 13 0 rfc13 12 0 rfc12 11 0 rfc11 10 0 rfc10 9 0 rfc9 8 0 rfc8 7 0 rfc7 6 0 rfc6 5 0 rfc5 4 0 rfc4 3 0 rfc3 2 0 rfc2 1 0 rfc1 0 0 rfc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit : initial value : r/w : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1050 of 1174 rej09b0329-0200 h'd096: reference frequency mode register rfm: reference signal generator 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 rex crd od/ev vst veg 0 w rcs w w w vna cvs clock source select bit 0 s/2 (initial value) 1 s/4 mode select bit 0 manual mode (initial value) 1 auto mode manual select bit 0 vd sync (initial value) 1 free-run external signal synchronization select bit 0 vd signal or free-run (initial value) 1 external signal sync dvcfg2 synchronization select bit 0 at mode switching (initial value) 1 dvcfg2 signal synchronized odd/even edge switchoverselect bit 0 generated at field signal rising (even) (initial value) 1 generated at field signal rising (odd) videoff counter set 0 videoff signal turns counter set off (initial value) 1 videoff signal turns counter set on videoff edge select bit 0 set at videoff signal rising (initial value) 1 set at videoff signal falling bit initial value r/w : : : h'd097: reference frequency mode register 2 rfm2: reference signal generator 0 0 1 1 2 1 3 1 4 1 5 6 7 fds 1 11 r/w field select bit 0 generated by selected odd or even vd signal (initial value) 1 generated by vd signal within mode transition phase error of 90? tbc select bit 0 reference signal is generated by vd signal 1 reference signal is generated by free-running counter tbc?????? r/w?????? bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1051 of 1174 rej09b0329-0200 h'd098: dvctl control register ctvc: frequency divider 0 * 1 * r 2 * r 3 4 5 6 7 r cfg hsw 0 w 0 w cex ceg ctl 1 1 1 dvctl signal generation select bit 0 generated by pb-ctl signal (initial value) 1 generated by external input signal external sync signal edge select bit 0 rising edge (initial value) 1 falling edge cfg flag 0 cfg level is low (initial value) 1 cfg level is high hsw flag 0 hsw level is low (initial value) 1 hsw level is high ctl flag 0 rec or pb-ctl level is low (initial value) 1 rec or pb-ctl level is high ??? ??? bit initial value r/w : : : h'd099: ctl frequency division register ctlr: frequency divider 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 ctl4 ctl3 ctl2 ctl1 ctl0 0 w ctl7 w w w ctl6 ctl5 bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1052 of 1174 rej09b0329-0200 h'd09a: dvcfg control register cdvc: frequency divider 0 0 1 0 w 2 0 w 3 4 0 w 5 1 6 1 7 w r cmk cmn w dvtrg 0 r/w * mcgin crf cps1 cps0 0 note: * only 0 can be written mask cfg flag 0 cfg normal operation (initial value) 1 dvcfg is detected while mask is set (race detection) cfg mask status bit 0 mask is released by capstan mask timer 1 mask is set by capstan mask timer (initial value) cfg mask select bit 0 capstan mask timing function on (initial value) 1 capstan mask timing function off pb (asm)-to-rec transition timing sync on/off select bit 0 pb (asm)-to-rec transition timing sync on (initial value) 1 pb (asm)-to-rec transition timing sync off cfg frequency division edge select bit 0 execute frequency division operation at cfg rising edge (initial value) 1 execute frequency division operation at cfg rising cfg mask timer clock select bit cps1 cps0 description 0 0 s/1024 (initial value) 1 s/512 1 0 s/256 1 s/128 ? ? bit initial value r/w : : : h'd09b: cfg frequency division register 1 cdivr1: frequency divider 0 0 1 0 w 2 0 w 3 4 0 w 5 0 6 7 w w cdv15 cdv14 0 w cdv16 0 w cdv13 cdv12 cdv11 cdv10 1 bit : initial value : r/w : ? ? appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1053 of 1174 rej09b0329-0200 h'd09c: cfg frequency division register 2 cdivr2: frequency divider 0 0 1 0 w 2 0 w 3 4 0 w 5 0 6 7 w w cdv25 cdv24 0 w cdv26 0 w cdv23 cdv22 cdv21 cdv20 1 bit : initial value : r/w : ? ? h'd09d: dvcfg mask interval register ctmr: frequency divider 0 1 1 1 w 2 1 w 3 4 1 w 5 1 6 7 w w cpm5 cpm4 1 w cpm3 cpm2 cpm1 cpm0 11 bit : initial value : r/w : ?? ?? h'd09e: fg control register fgcr: frequency divider 0 0 1 1 2 1 3 1 4 1 5 1 6 1 7 w drf 1 dfg edge select bit 0 ncdfg signal rising edge is selected (initial value) 1 ncdfg signal falling edge is selected bit : initial value : r/w : ?????? ? ?????? ? h'd0a0: servo port mode re gister spmr: servo port 0 1 1 1 ? 2 1 ? 3 1 4 1 ? 0 r/w 5 6 7 ????? 0 r/w ctlstop ? ? cfgcomp 1 cfg input method switch bit 0 zero cross type comparator method for cfg signal input (initial value) 1 digital signal input method for cfg signal input ctlstop bit 0 ctl circuit operates (initial value) 1 ctl circuit does not operate bit : initial value : r/w : ? ? appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1054 of 1174 rej09b0329-0200 h'd0a3: servo monitor control re gister svmcr: servo port 0 0 1 0 2 0 3 0 4 0 5 6 7 svmcr4 svmcr3 svmcr2 svmcr1 svmcr0 1 1 r/w r/w r/w 0 svmcr5 r/w r/w r/w svmcr5 svmcr4 svmcr3 description 0 0 0 ref30 signal is output from sv2 output pin (initial value) 1 capref30 signal is output from sv2 output pin 1 0 cref signal is output from sv2 output pin 1 ctlmoni signal is output from sv2 output pin 1 0 0 dvcfg signal is output from sv2 output pin 1 cfg signal is output from sv2 output pin 1 0 dfg signal is output from sv2 output pin 1 dpg signal is output from sv2 output pin svmcr2 svmcr1 svmcr0 description 0 0 0 ref30 signal is output from sv1 output pin (initial value) 1 capref30 signal is output from sv1 output pin 1 0 cref signal is output from sv1 output pin 1 ctlmoni signal is output from sv1 output pin 1 0 0 dvcfg signal is output from sv1 output pin 1 cfg signal is output from sv1 output pin 1 0 dfg signal is output from sv1 output pin 1 dpg signal is output from sv1 output pin ?? ?? sv2 pin servo monitor output control sv1 pin servo monitor output control bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1055 of 1174 rej09b0329-0200 h'd0a4: ctl gain control register ctlgr: servo port 0 0 1 0 2 0 3 0 4 0 5 6 7 ctlfb ctlgr3 ctlgr2 ctlgr1 ctlgr0 1 1 r/w r/w r/w 0 ctle/a r/w r/w r/w ctl select bit 0 amp output 1 exctl ctl amp feedback sw bit 0 ctlfb sw is off 1 ctlfb sw is on ctl amp gain setting bit ctlgr3 ctlgr2 ctlgr1 ctlgr0 ctl outpu gain 0 0 0 0 35.0 db (initial value) 1 37.5 db 1 0 40.0 db 1 42.5 db 1 0 0 45.0 db 1 47.5 db 1 0 50.0 db 1 52.5 db 1 0 0 0 55.0 db 1 57.5 db 1 0 60.0 db 1 62.5 db 1 0 0 65.0 db 1 67.5 db 1 0 70.0 db 1 72.5 db ?? ?? bit initial value r/w : : : h'd0b0: vertical sync signal threshold va lue register vtr: sync detector (servo) 0 0 1 0 w 2 0 w 3 0 4 0 w 5 0 6 1 7 w w w vtr5 vtr4 vtr3 vtr2 vtr1 vtr0 1 initial value : ?? ?? bit r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1056 of 1174 rej09b0329-0200 h'd0b1: horizontal sync signal threshold va lue register htr: sync detector (servo) 0 0 1 0 w 2 0 w 3 0 4 5 6 1 7 w w htr3 htr2 htr1 htr0 11 1 initial value : ???? ???? bit r/w : : : h'd0b2: h pulse adjustment start time setting register hrtr: sync detector (servo) 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 hrtr4 hrtr3 hrtr2 hrtr1 hrtr0 0 w hrtr7 w w w hrtr6 hrtr5 bit : initial value : r/w : h'd0b3: h pulse width setting regist er hpwr: sync detector (servo) 0 0 1 0 w 2 0 w 3 0 4 5 6 1 7 w w hpwr3 hpwr2 hpwr1 hpwr0 11 1 bit : initial value : r/w : ???? ???? h'd0b4: noise detection window setting re gister nwr: sync detector (servo) 0 0 1 0 w 2 0 w 3 0 4 0 w 5 0 6 1 7 w w w nwr5 nwr4 nwr3 nwr2 nwr1 nwr0 1 bit : initial value : r/w : ?? ?? h'd0b5: noise detection register ndr: sync detector (servo) 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 ndr4 ndr3 ndr2 ndr1 ndr0 0 w ndr7 w w w ndr6 ndr5 bit : initial value : r/w : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1057 of 1174 rej09b0329-0200 h'd0b6: sync signal control register syncr: sync detector (servo) 0 0 1 0 r 2 0 r/(w) * 3 1 4 5 6 1 7 r/w r/w nis/vd nois fld syct 11 1 note: * only 0 can be written. interrupt select bit 0 noise level interrupt 1 vd interrupt (initial value) noise detection flag 0 noise count is less than four times of ndr setting value (initial value) 1 noise count is equal to or greater than four times of ndr setting value field detection flag 0 odd field (initial value) 1 even field sync signal polarity select bit syct description polarity 0 positive 1 negative initial value : ???? ???? bit r/w : : (initial value) appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1058 of 1174 rej09b0329-0200 h'd0b8: servo interrupt enable regi ster 1 sienr1: servo interrupt 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 6 0 7 iecap3 iecap2 iecap1 iehsw2 iehsw1 0 r/w iedrm3 r/w r/w r/w iedrm2 iedrm1 drum phase error detection interrupt enable bit 0 interrupt request is disabled by irrdrm3 (initial value) 1 interrupt request is enabled by irrdrm3 drum speed error detection (lock detection) interrupt enable bit 0 interrupt request is disabled by irrdrm2 (initial value) 1 interrupt request is enabled by irrdrm2 drum speed error detection (ovf, latch) interrupt enable bit 0 interrupt request is disabled by irrdrm1 (initial value) 1 interrupt request is enabled by irrdrm1 capstan phase error detection interrupt enable bit 0 interrupt request is disabled by irrcap3 (initial value) 1 interrupt request is enabled by irrcap3 capstan speed error detection (lock detection) interrupt enable bit 0 interrupt request is disabled by irrcap2 (initial value) 1 interrupt request is enabled by irrcap2 capstan speed error detection (ovf, latch) interrupt enable bit 0 interrupt request is disabled by irrcap1 (initial value) 1 interrupt request is enabled by irrcap1 hsw timing generation (counter clear, capture) interrupt enable bit 0 interrupt request is disabled by irrhsw2 (initial value) 1 interrupt request is enabled by irrhsw2 hsw timing generator (ovw, match, strig) interrupt enable bit 0 interrupt request is disabled by irrhsw1 (initial value) 1 interrupt request is enabled by irrhsw1 initial value : bit r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1059 of 1174 rej09b0329-0200 h'd0b9: servo interrupt enable regi ster 2 sienr2: servo interrupt 0 0 1 0 r/w 2 3 4 5 6 1 7 r/w iesnc iectl 11 11 1 vertical sync signal interrupt enable bit 0 interrupt (vertical sync signal interrupt) request is disabled by irrsnc (initial value) 1 interrupt (vertical sync signal interrupt) request is enabled by irrsnc ctl interrupt enable bit 0 interrupt request is disabled by irrctl (initial value) 1 interrupt request is enabled by irrctl initial value : ?????? ?????? bit r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1060 of 1174 rej09b0329-0200 h'd0ba: servo interrupt request register 1 sirqr1: servo interrupt 0 0 1 0 r/(w) * 2 0 r/(w) * 3 0 4 0 r/(w) * 0 r/(w) * 5 6 0 7 irrcap3 irrcap2 irrcap1 irrhsw2 irrhsw1 0 r/(w) * irrdrm3 r/(w) * r/(w) * r/(w) * irrdrm2 irrdrm1 note: * only 0 can be written to clear the flag. drum phase error detector interrupt request bit 0 drum phase error detector interrupt request is not generated (initial value) 1 drum phase error detector interrupt request is generated drum speed error detector (lock detection) interrupt request bit 0 drum speed error detector (lock detection) interrupt request is not generated (initial value) 1 drum speed error detector (lock detection) interrupt request is generated drum speed error detector (ovf, latch) interrupt request bit 0 drum speed error detector (ovf, latch) interrupt request is not generated (initial value) 1 drum speed error detector (ovf, latch) interrupt request is generated capstan phase error detector interrupt request bit 0 capstan phase error detector interrupt request is not generated (initial value) 1 capstan phase error detector interrupt request is generated capstan speed error detector (lock detection) intrerrupt request bit 0 capstan speed error detector (lock detection) interrupt request is not generated (initial value) 1 capstan speed error detector (lock detection) interrupt request is generated capstan speed error detector (ovf, latch) interrupt request bit 0 capstan speed error detector (ovf, latch) interrupt request in not generated (initial value) 1 capstan speed error detector (ovf, latch) interrupt request is generated hsw timing generator (counter clear, capture) interrupt request bit 0 hsw timing generator (counter clear, capture) interrupt request is not generated (initial value) 0 hsw timing generator (counter clear, capture) interrupt request is generated hsw timing generator (ovw, match, strig) interrupt request bit 0 hsw timing generator (ovm, match, strig) interrupt request is not generated (initial value) 1 hsw timing generator (ovm, match, strig) interrupt request is generated bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1061 of 1174 rej09b0329-0200 h'd0bb: servo interrupt request register 2 sirqr2: servo interrupt 0 0 1 0 r/(w) * 2 3 4 5 6 1 7 r/(w) * irrsnc irrctl 11 11 1 note: * only 0 can be written to clear the flag. vertical sync signal interrupt request bit 0 sync signal detector (vd, noise) interrupt request is not generated (initial value) 1 sync signal detector (vd, noise) interrupt request is generated ctl interrupt request bit 0 ctl interrupt request is not generated (initial value) 1 ctl interrupt request is generated ? ????? ? ????? bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1062 of 1174 rej09b0329-0200 h'd0e5: ddc switch register ddcswr: i 2 c bus interface 0 1 1 1 w * 2 2 1 w * 2 3 1 4 0 r/(w) * 1 0 r/w 5 7 if * 3 clr3 clr2 clr1 clr0 0 r/w swe * 3 6 0 r/w sw * 3 w * 2 w * 2 ie * 3 ddc mode switch interrupt enable bit 0 disables an interrupt at automatic format switching (initial value) 1 enables an interrupt at automatic format switching ddc mode switch 0 i 2 c bus format is selected for iic channel 0. (initial value) [clearing conditions] (1) when 0 is written by software (2) when an scl falling edge is detected when swe = 1 1 formatless transfer is selected for iic channel 0. [setting condition] when 1 is written after sw = 0 is read ddc mode switch enable 0 disables automatic switching from formatless transfer to i 2 c bus format transfer for iic channel 0. (initial value) 1 enables automatic switching from formatless transfer to i 2 c bus format transfer for iic channel 0. ddc mode switch interrupt flag 0 interrupt has not been requested (initial value) [clearing condition] when 0 is written after if = 1 is read 1 interrupt has been requested [setting condition] when an scl falling edge is detected when swe = 1 : : : bit initial value r/w notes: 1. only 0 can be written to clear the flag. 2. always read as 1. 3. these bits are not provided for the h8s/2197s and h8s/2196s. i 2 c clear control appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1063 of 1174 rej09b0329-0200 h'd0e8: i 2 c bus control register iccr0: i 2 c bus interface 7 ice 0 r/w 6 ieic 0 r/w 5 mst 0 r/w 4 trs 0 r/w 3 acke 0 r/w 0 scp 1 w 2 bbsy 0 r/w 1 iric 0 r/(w) * note: * only 0 can be written to clear the flag. i 2 c bus interface enable 0 i 2 c bus interface module disabled, with scl and sda signal pins (initial value) set to port function. the internal status of the iic is initialized sar and sarx can be accessed. 1 i 2 c bus interface module enabled for transfer operation (pins scl and sca are driving the bus). icmr and icdr can be accessed. i 2 c bus interface interrupt enable 0 interrupt request is disab led (initial value) 1 interrupt request is enabled acknowledge bit judgment selection 0 the value of the acknowledge bit is ignored, and continuous transfer is performed (initial value) 1 if the acknowledge bit is 1, continuous transfer is interrupted bus busy 0 bus is free (initial value) [clearing condition] when a stop condition is detected 1 bus is busy [setting condition] when a start condition is detected i 2 c bus interface interrupt request flag 0 waiting for transfer, or transfer in progress (initial value) [clearing condition] when 0 is written in iric after reading iric = 1 (1) interrupt requested [setting conditions] ?i 2 c bus format master mode (1) when a start condition is detected in the bus line state after a start condition is issued (when the tdre flag is set to 1 because of first frame transmission) (2) when a wait is inserted between the data and acknowledge bit when wait = 1 (3) at the end of data transfer (at the rise of the 9th transmit clock pulse, or at the fall of the 8th transmit/receive clock pulse when using wait insertion) (4) when a slave address is received after bus arbitration is lost (when the al flag is set to 1) (5) when 1 is received as the acknowledge bit when the acke bit is 1 (when the ackb bit is set to 1) ?i 2 c bus format slave mode (1) when the slave address (sva, svax) matches (when the aas and aasx flags are set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the tdre or rdrf flag is set to 1) (2) when the general call address is detected (when fs=0 and the adz flag is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the tdre or rdrf flag is set to 1) (3) when 1 is received as the acknowledge bit when the acke bit is 1 (when the ackb bit is set to 1) (4) when a stop condition is detected (when the stop or estp flag is set to 1) ?synchronous serial format and formatless (1) at the end of data transfer (when the tdre or rdrf flag is set to 1) (2) when a start condition is detected with serial format selected ?when a condition, other than the above, that sets the tdre or rdrf flag to 1 is detected start condition/stop condition prohibit 0 writing 0 issues a start or stop condition, in combination with the bbsy flag 1 reading always returns a value of 1 (initial value) writing is ignored master/slave select transmit/receive select mst trs description 0 0 slave receive mode (initial value) 1 slave transmit mode 1 0 master receive mode 1 master transmit mode bit : initial value : r/w : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1064 of 1174 rej09b0329-0200 h'd0e9: i 2 c bus status register icsr0: i 2 c bus interface 7 estp 0 r/(w) * 6 stop 0 r/(w) * 5 irtr 0 r/(w) * 4 aasx 0 r/(w) * 3 al 0 r/(w) * 0 ackb 0 r/w 2 aas 0 r/(w) * 1 adz 0 r/(w) * note: * only 0 can be written to clear the flag. error stop condition detection flag 0 no error stop condition (initial value) [clearing conditions] (1) when 0 is written in estp after reading estp = 1 (2) when the iric flag is cleared to 0 1 ? in i 2 c bus format slave mode error stop condition detected [setting condition] ? when a stop condition is detected during frame transfer ?in other mode no meaning normal stop condition detection flag 0 no normal stop condition (initial value) [clearing conditions] (1) when 0 is written in stop after reading stop = 1 (2) when the iric flag is cleared to 0 1 ? in i 2 c bus format slave mode normal stop condition detected [setting condition] ? when a stop condition is detected after completion of frame transfer ?in other mode no meaning i 2 c bus interface continuous transmission/reception interrupt request flag 0 waiting for transfer, or transfer in progress (initial value) [clearing conditions] (1) when 0 is written in irtr after reading irtr = 1 (2) when the iric flag is cleared to 0 1 continuous transfer state [setting conditions] ?i 2 c bus interface slave mode ? when the tdre or rdrf flag is set to 1 when aasx = 1 ?in other mode ? when the tdre or rdrf flag is set to 1 second slave address recognition flag 0 second slave address not recognized (initial value) [clearing conditions] (1) when 0 is written in aasx after reading aasx = 1 (2) when a start condition is detected (3) in master mode 1 second slave address recognized [setting condition] ? when the second slave address is detected in slave receive mode while fsx = 0 arbitration lost flag 0 bus arbitration won (initial value) [clearing conditions] (1) when icdr data is written (transmit mode) or read (receive mode) (2) when 0 is written in al after reading al = 1 1 arbitration lost [setting conditions] (1) if the internal sda and sda pin disagree at the rise of scl in master transmit mode (2) if the internal scl line is high at the fall of scl in master transmit mode slave address recognition flag 0 slave address or general call address not recognized (initial value) [clearing conditions] (1) when icdr data is written (transmit mode) or read (receive mode) (2) when 0 is written in aas after reading aas = 1 (3) in master mode 1 slave address or general call address recognized [setting condition] ? when the slave address or general call address is detected when fs = 0 in slave receive mode general call address recognition flag 0 general call address not recognized (initial value) [clearing conditions] (1) when icdr data is written (transmit mode) or read (receive mode) (2) when 0 is written in adz after reading adz = 1 (3) in master mode 1 general call address recognized [setting condition] ? when the general call address is detected when fsx = 0 or fs = 0 in slave receive mode acknowledge bit 0 receive mode: 0 is output at acknowledge output timing (initial value) transmit mode: indicates that the receiving device has acknowldeged the data (signal is 0) 1 receive mode; 1 is output at acknowledge output timing transmit mode: indicates that the receiving device has not acknowldeged the data (signal is 1) bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1065 of 1174 rej09b0329-0200 h'd0ee: i 2 c bus data register icdr0: i 2 c bus interface 7 icdr7 ? r/w 6 icdr6 ? r/w 5 icdr5 ? r/w 4 icdr4 ? r/w 3 icdr3 ? r/w 0 icdr0 ? r/w 2 icdr2 ? r/w 1 icdr1 ? r/w initial value : note: refer to section 23.2.1, i 2 c bus data register (icdr). bit r/w : : h'd0ee: second slave address register sarx0: i 2 c bus interface 7 svax6 0 r/w 6 svax5 0 r/w 5 svax4 0 r/w 4 svax3 0 r/w 3 svax2 0 r/w 0 fsx 1 r/w 2 svax1 0 r/w 1 svax0 0 r/w format select used combined fs bit in sar. initial value : note: refer to section 23.2.3, second slave address register (sarx), and section 23.2.2, slave address register (sar). bit r/w : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1066 of 1174 rej09b0329-0200 h'd0ef: i 2 c bus mode register icmr0: i 2 c bus interface 7 mls 0 r/w 6 wait 0 r/w 5 cks2 0 r/w 4 cks1 0 r/w 3 cks0 0 r/w 0 bc0 0 r/w 2 bc2 0 r/w 1 bc1 0 r/w msb-first/lsb-first select note: * see bit 6 in the serial timer control register (stcr) 0 msb-first (initial value) 1 lsb-first wait insertion bit 0 data and acknowledge bits transferred consecutively (initial value) 1 wait inserted between data and acknowledge bits transfer clock select bits bit counter bit/frame bc2 bc1 bc0 clock sync i 2 c bus format serial format 0 0 0 8 9 (initial value) 1 1 2 1 0 2 3 1 3 4 0 0 0 4 5 1 5 6 1 0 6 7 1 7 8 iicx * cks2 cks1 cks0 clock transfer rate =8 mhz =10 mhz 0 0 0 0 /28 286 khz 357 khz 1 /40 200 khz 250 khz 1 0 /48 167 khz 208 khz 1 /64 125 khz 156 khz 1 0 0 /80 100 khz 125 khz 1 /100 80.0 khz 100 khz 1 0 /112 71.4 khz 89.3 khz 1 /128 62.5 khz 78.1 khz 1 0 0 0 /56 143 khz 179 khz 1 /80 100 khz 125 khz 1 0 /96 83.3 khz 104 khz 1 /128 62.5 khz 78.1 khz 1 0 0 /160 50.0 khz 62.5 khz 1 /200 40.0 khz 50.0 khz 1 0 /224 35.7 khz 44.6 khz 1 /256 31.3 khz 39.1 khz bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1067 of 1174 rej09b0329-0200 h'd0ef: slave address register sar0: i 2 c bus interface 7 sva6 0 r/w 6 sva5 0 r/w 5 sva4 0 r/w 4 sva3 0 r/w 3 sva2 0 r/w 0 fs 0 r/w 2 sva1 0 r/w 1 sva0 0 r/w format select bit ddcswr sar sarx format select bit 6 bit 0 bit 0 sw fs fx 0 0 0 i 2 c bus format ? sar and sarx slave addresses recognized 1 i 2 c bus format (initial value) ? sar slave address recognized ? sarx slave address ignored 1 0 i 2 c bus format ? sar slave address ignored ? sarx slave address recognized 1 i 2 c bus format ? sar and sarx slave addresses ignored 1 0 0 formatless transfer (start and stop conditions are not detected) 1 ? with acknowledge bit 0 0 formatless transfer * (start and stop conditions are not detected) 1 ? without acknowledge bit bit initial value r/w : : : note: * do not use this setting when automatically switching the made from formatless transfer to i 2 c bus format by setting ddcswr. appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1068 of 1174 rej09b0329-0200 h'd100: timer interrupt enable register tier: timer x1 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 5 0 6 0 7 r/w r/w r/w icice r/w icibe 0 r/w iciae icide ociae ocibe ovie icsa icfa interrupt request (icia) is disabled (initial value) icfa interrupt request (icia) is enabled 0 1 input capture a interrupt enable bit ftia pin input is selected for input capture a input (initial value) hsw is selected for input capture a input 0 1 input capture input select a bit icfb interrupt request (icib) is disabled (initial value) icfb interrupt request (icib) is enabled 0 1 input capture b interrupt enable bit icfc interrupt request (icic) is disabled (initial value) icfc interrupt request (icic) is enabled 0 1 input capture c interrupt enable bit icfd interrupt request (icid) is disabled (initial value) icfd interrupt request (icid) is enabled 0 1 input capture d interrupt enable bit interrupt request (fovi) is disabled (initial value) interrupt request (fovi) is enabled 0 1 timeout overflow interrupt enable bit 0 ocfb interrupt request (ocib) is disabled (initial value) ocfb interrupt request (ocib) is enabled 1 output compare interrupt b enable bit ocfa interrupt request (ocia) is disabled (initial value) ocfa interrupt request (ocia) is enabled 0 1 output compare interrupt a enable bit bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1069 of 1174 rej09b0329-0200 h'd101: timer control/status register x tcsrx: timer x1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 r/ w r/(w) * icfb 0 r/(w) * icfa r/(w) * icfd r/(w) * icfc r/(w) * ocfb r/(w) * ocfa cclra r/(w) * ovf note: * only 0 can be written to bits 7 to 1 to clear the flags. output compare flag a [clearing condition] when 0 is written to ocfa after reading ocfa = 1 (initial value) [setting condition] when frc = ocra 0 1 output compare flag b [clearing condition] when 0 is written to ocfb after reading ocfb = 1 (initial value) [setting condition] when frc = ocrb 0 1 timer overflow [clearing condition] when 0 is written to ovf after reading ovf = 1 (initial value) [setting condition] when frc changes from h'ffff to h'0000 0 1 input capture flag d [clearing condition] when 0 is written to icfd after reading icfd = 1 (initial value) [setting condition] when input capture signal is generated 0 1 input capture flag c [clearing condition] when 0 is written to icfc after reading icfc = 1 (initial value) [setting condition] when input capture signal is generated 0 1 input capture flag b [clearing condition] when 0 is written to icfb after reading icfb = 1 (initial value) [setting condition] when frc value is transferred to icrb by input capture signal 0 1 input capture flag a [clearing condition] when 0 is written to icfa after reading icfa = 1 (initial value) [setting condition] when frc value is transferred to icra by input capture signal 0 1 counter clear frc clearing is disabled (initial value) frc clearing is enabled 0 1 initial value : bit r/w : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1070 of 1174 rej09b0329-0200 h'd102: free running counter h frch: timer x1 h'd103: free running counter l frcl: timer x1 0 3 0 r/w 5 0 r/w 7 0 9 0 r/w 11 0 13 0 15 r/w r/w r/w 0 r/w r/w 1 0 2 0 r/w 4 0 r/w 6 0 8 0 r/w 10 0 12 0 14 frc frch frcl r/w r/w r/w r/w 0 r/w 0 bit : initial value : r/w : h'd104: output compare register ah , bh ocrah, ocrbh: timer x1 h'd105: output compare register al, bl ocral, ocrbl: timer x1 1 3 1 r/w 5 1 r/w 7 1 9 1 r/w 11 1 13 1 15 r/w r/w r/w 1 r/w r/w 1 1 2 1 r/w 4 1 r/w 6 1 8 1 r/w 10 1 12 1 14 ocra, ocrb ocrah, ocrbh ocral, ocrbl r/w r/w r/w r/w 1 r/w 0 bit : initial value : r/w : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1071 of 1174 rej09b0329-0200 h'd106: timer control register x tcrx: timer x1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 r/w r/w iedgb 0 r/w iedga r/w iedgd r/w iedgc r/w bufeb r/w bufea cks0 r/w cks1 capture at falling edge of input capture input a (initial value) capture at rising edge of input capture input a 0 1 input capture edge select a capture at falling edge of input capture input b (initial value) capture at rising edge of input capture input b 0 1 input capture edge select b capture at falling edge of input capture input c (initial value) capture at rising edge of input capture input c 0 1 input capture edge select c capture at falling edge of input capture input d (initial value) capture at rising edge of input capture input d 0 1 input capture edge select d icrd is not used as buffer register for icrb (initial value) icrd is used as buffer register for icrb 0 1 buffer enable b icrc is not used as buffer register for icra (initial value) icrc is used as buffer register for icra 0 1 buffer enable a clock selct bit clock select 0 0 cks0 cks1 1 0 0 1 internal clock: count at /4 (initial value) internal clock: count at /16 internal clock: count at /64 1 1 dvcfg: edge detection pulse selected by cfg frequency division timer bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1072 of 1174 rej09b0329-0200 h'd107: timer output compare control register tocr: timer x1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 r/w r/w icsc 0 r/w icsb r/w osrs r/w icsd r/w oeb r/w oea olvlb r/w olvla ftib pin is selected for input capture b input (initial value) vd is selected for input capture b input 0 1 input capture input select b low level (initial value) high level 0 1 output level b ftic pin is selected for input capture c input (initial value) dvctl is selected for input capture c input 0 1 input capture input select c ftid pin is selected for input capture d input (initial value) nhsw is selected for input capture d input 0 1 input capture input select d ocra register is selected (initial value) ocrb register is selected 0 1 output compare register select low level (initial value) high level 0 1 output level a output compare a output is disabled (initial value) output compare a output is enabled 0 1 output enable a initial value : 0 1 output enable b output compare b output is disabled (initial value) output compare b output is enabled bit r/w : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1073 of 1174 rej09b0329-0200 h'd108: input capture register ah icrah: timer x1 h'd109: input capture register al icral: timer x1 h'd10a: input capture register bh icrbh: timer x1 h'd10b: input capture register bl icrbl: timer x1 h'd10c: input capture register ch icrch: timer x1 h'd10d: input capture register cl icrcl: timer x1 h'd10e: input capture register dh icrdh: timer x1 h'd10f: input capture register dl icrdl: timer x1 0 3 0 r 5 0 r 7 0 9 0 r 11 0 13 0 15 r r r 0 rr 1 0 2 0 r 4 0 r 6 0 8 0 r 10 0 12 0 14 icra, icrb, icrc, icrd icrah, icrbh, icrch, icrdh icral, icrbl, icrcl, icrdl r r r r 0 r 0 bit : initial value : r/w : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1074 of 1174 rej09b0329-0200 h'd110: timer mode register b tmb: timer b 0 0 1 0 r/w 2 0 r/w 3 1 4 1 5 0 6 0 7 r/w r/w tmbie r/(w) * tmbif 0 r/w tmb17 tmb12 tmb11 tmb10 note: * only 0 can be written to clear the flag. interval function is selected (initial value) auto reload function is selected 0 1 auto reload function select bit [setting condition] when tcb overflows [clearing condition] (initial value) when 0 is written after reading 1 0 1 timer b interrupt request flag timer b interrupt request is disabled (initial value) timer b interrupt request is enabled 0 1 timer b interrupt enable bit 0 0 0 internal clock: count at /16384 (initial value) tmb11 tmb10 tmb12 clock select 0 1 internal clock: count at /4096 1 0 0 0 0 internal clock: count at /1024 1 1 internal clock: count at /512 0 1 0 internal clock: count at /128 0 1 internal clock: count at /32 1 1 1 1 0 internal clock: count at /8 1 1 count at rising/falling edge of external event (tmbi) * note: * external event edge selection is set at pmra6 in port mode register a (pmra). see section 12.2.4, port mode register a (pmra). clock select bit initial value : ?? ?? bit r/w : : h'd111: timer counter b tcb: timer b 0 0 1 0 r 2 0 r 3 4 5 0 6 0 7 r r tcb15 0 r tcb14 0 r tcb13 r tcb16 0 r tcb17 tcb12 tcb11 tcb10 bit : initial value : r/w : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1075 of 1174 rej09b0329-0200 h'd111: timer load registerb tlb: timerb 0 0 1 0 w 2 0 w 3 4 5 0 6 0 7 w w tlb15 0 w tlb14 0 w tlb13 w tlb16 0 w tlb17 tlb12 tlb11 tlb10 bit : initial value : r/w : h'd112: timer l mode register lmr: timer l 0 0 1 0 r/w 2 0 r/w 3 0 4 1 5 1 6 0 7 r/w r/w r/w lmie 0 r/(w) * lmif lmr3 lmr2 lmr1 lmr0 note: * only 0 can be written to clear the flag. timer l interrupt request flag [clearing condition] (initial value) when 0 is written after reading 1 [setting condition] when ltc overflow, underflow or compare match clear occurs 0 1 timer l interrupt enable bit timer l interrupt request is disabled (initial value) timer l interrupt request is enabled 0 1 up count control (initial value) down count control 0 1 up/down count control clock select bit clock select 0 0 0 count at rising edge of pb and rec-ctl (initial value) lmr1 lmr0 lmr2 1 count at falling edge of pb and rec-ctl 1 * count dvcfg2 0 1 * internal clock: count at /128 1 * internal clock: count at /64 note: * don't care. ?? ?? bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1076 of 1174 rej09b0329-0200 h'd113: linear time counter ltc: timer l 0 0 1 0 r 2 0 3 0 4 5 6 0 7 r rr r ltc6 0 r ltc5 0 r ltc4 0 r ltc7 ltc3 ltc2 ltc1 ltc0 bit : initial value : r/w : h'd113: reload/compare match register rcr: timer l 0 0 1 0 w 2 0 3 0 4 5 6 0 7 w ww w rcr6 0 w rcr5 0 w rcr4 0 w rcr7 rcr3 rcr2 rcr1 rcr0 bit : initial value : r/w : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1077 of 1174 rej09b0329-0200 h'd118: timer r mode register 1 tmrm1: timer r 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 5 0 6 0 7 r/w r/w r/w rld r/w ac/br 0 r/w clr2 rlck ps21 ps20 rld/cap cps tmru-2 is not cleard at the time of capture (initial value) tmru-2 is cleard at the time of capture 0 1 tmru-2 clear select bit deceleration (initial value) acceleration 0 1 acceleration/deceleration select bit tmru-2 is not used as reload timer (initial value) tmru-2 is used as reload timer 0 1 execution/non-execution of reload by tmru-2 reload at cfg rising edge (initial value) reload at tmru-2 underflow 0 1 tmru-2 reload timing select bit 0 0 count at tmru-1 underflow (initial value) ps20 ps21 1 pss, count at /256 0 1 pss, count at /128 pss, count at /64 1 tmru-2 clock source select bits description capture signal at cfg rising edge (initial value) capture signal at irq3 edge 0 1 tmru-1 capture signal select bit tmru-1 functions as reload timer (initial value) tmru-1 functions as capture timer 0 1 tmru-1 operation mode select bit initial value : bit r/w : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1078 of 1174 rej09b0329-0200 h'd119: timer r mode register 2 tmrm2: timer r 0 0 1 0 r/(w) * 2 0 r/w 3 0 4 0 r/w 5 0 6 0 7 r/(w) * r/w r/w ps10 r/w ps11 0 r/w lat ps31 ps30 cp/slm capf slw tmru-1 clock source select bits description 0 0 count at cfg rising edge (initial value) ps10 ps11 1 pss, count at /4 0 1 pss, count at /256 1 pss, count at /512 tmru-3 clock source select bits description 0 0 count at rising edge of dvctl from frequency divider (initial value) ps30 ps31 1 pss, count at /4096 0 1 pss, count at /2048 1 pss, count at /1024 interrupt select bit interrupt request by tmru-2 capture signal is enabled (initial value) interrupt request by slow tracking mono-multi end is enabled 0 1 capture signal flag [clearing condition] (initial value) when 0 is written after reading 1 [setting condition] when tmru-2 capture signal is generated while cp/slm bit = 0 0 1 slow tracking mono-multi flag [clearing condition] (initial value) when 0 is written after reading 1 [setting condition] when slow tracking mono-multi ends while cp/slm bit = 1 0 1 tmru-2 captrue signal select bits * 0 capture at tmru-3 underflow (initial value) cps lat 0 1 capture at cfg rising edge 1 capture at irq3 edge description legend: * don't care. initial value : bit r/w : : note: * the capf bit and the slw bit, respectively, works to latch the interrupt causes and writing 0 only is valid. consequently, when these bits are being set to 1, respective interrupt requests will not be issued. therefore, it is necessary to check these bits during the course of the interrupt processing routine to have them cleared. also priority is given to the set and, when an interrupt cause occur while the a clearing command (bclr, mov, etc.) is being executed, the capf bit and the slw bit will not be cleared respectively and it thus becomes necessary to pay attention to the clearing timing. appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1079 of 1174 rej09b0329-0200 h'd11a: timer r capture register 1 tmrcp1: time r 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 r tmrc17 r tmrc16 r tmrc15 r tmrc14 r tmrc13 r tmrc12 r tmrc11 r tmrc10 bit : initial value : r/w : h'd11b: timer r capture register 2 tmrcp2: time r 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 r tmrc27 r tmrc26 r tmrc25 r tmrc24 r tmrc23 r tmrc22 r tmrc21 r tmrc20 bit : initial value : r/w : h'd11c: timer r load register 1 tmrl1: timer r 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 w tmr17 w tmr16 w tmr15 w tmr14 w tmr13 w tmr12 w tmr11 w tmr10 bit : initial value : r/w : h'd11d: timer r load register 2 tmrl2: timer r 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 w tmr27 w tmr26 w tmr25 w tmr24 w tmr23 w tmr22 w tmr21 w tmr20 bit : initial value : r/w : h'd11e: timer r load register 3 tmrl3: timer r 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 w tmr37 w tmr36 w tmr35 w tmr34 w tmr33 w tmr32 w tmr31 w tmr30 bit : initial value : r/w : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1080 of 1174 rej09b0329-0200 h'd11f: timer r control/statu s register tmrcs: timer r 0 1 1 1 2 0 r/(w) * 3 0 4 0 r/(w) * 5 0 6 0 7 r/(w) * r/w tmri1e r/w tmri2e 0 r/w tmri3e tmri3 tmri2 tmri1 note: * only 0 can be written to clear the flag. tmri3 interrupt request is disabled (initial value) tmri3 interrupt request is enabled 0 1 tmri3 interrupt enable bit tmri2 interrupt request is disabled (initial value) tmri2 interrupt request is enabled 0 1 tmri2 interrupt enable bit tmri1 interrupt request is disabled (initial value) tmri1 interrupt request is enabled 0 1 tmri1 interrupt enable bit tmri1 interrupt request flag [clearing condition] (initial value) when 0 is written after reading 1 [setting condition] when tmru-1 underflows 0 1 tmri2 interrupt request flag [clearing condition] (initial value) when 0 is written after reading 1 [setting condition] when tmru-2 underflows or when capstan motor acceleration/deceleration operation ends 0 1 tmri3 interrupt request flag [clearing condition] (initial value) when 0 is written after reading 1 [setting condition] when interrupt source selected at cp/slm bit in tmrm2 is generated 0 1 initial value : ?? ? ? bit r/w : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1081 of 1174 rej09b0329-0200 h'd120: pwm data register l pwdrl: 14-bit pwm 0 0 1 0 2 0 3 0 4 0 5 0 6 7 w pwdrl0 w pwdrl1 w pwdrl2 w pwdrl3 w pwdrl4 w pwdrl5 0 w pwdrl6 w pwdrl7 0 bit : initial value : r/w : h'd121: pwm data register u pwdru: 14-bit pwm 0 0 1 0 2 0 3 0 4 0 5 0 6 1 7 w pwdru0 w pwdru1 w pwdru2 w pwdru3 w pwdru4 w pwdru5 1 bit : initial value : r/w : ?? ?? h'd122: pwm control register pwcr: 14-bit pwm 0 0 1 1 2 1 3 1 4 1 5 1 6 1 7 r/w pwcr0 1 clock select bit note: t : pwm input clock frequency input clock is /2 (t = 2/ ) (initial value) generate pwm waveform with conversion frequency of 16384/ and minimum pulse width of 1/ input clock is /4 (t = 4/ ) generate pwm waveform with conversion frequency of 32768/ and minimum pulse width of 2/ 0 1 initial value : ??????? ??????? bit r/w : : h'd126: 8-bit pwm data register 0 pwr0: 8-bit pwm 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 pw04 pw03 pw02 pw01 pw00 0 w pw07 w w w pw06 pw05 bit : initial value : r/w : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1082 of 1174 rej09b0329-0200 h'd127: 8-bit pwm data register 1 pwr1: 8-bit pwm 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 pw14 pw13 pw12 pw11 pw10 0 w pw17 w w w pw16 pw15 bit : initial value : r/w : h'd128: 8-bit pwm data register 2 pwr2: 8-bit pwm 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 pw24 pw23 pw22 pw21 pw20 0 w pw27 w w w pw26 pw25 bit : note: the h8s/2197s and h8s/2196s do not have pwr2 and pwr3. initial value : r/w : h'd129: 8-bit pwm data register 3 pwr3: 8-bit pwm 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 pw34 pw33 pw32 pw31 pw30 0 w pw37 w w w pw36 pw35 bit : initial value : r/w : note: the h8s/2197s and h8s/2196s do not have pwr2 and pwr3. h'd12a: 8-bit pwm control register pw8cr: 8-bit pwm 0 0 1 0 r/w 2 0 r/w 3 0 4 5 6 7 pwc3 pwc2 pwc1 pwc0 r/w r/w 1111 output polarity select bits positive polarity (initial value) negative polarity 0 1 note: n = 3 to 0 (h8s/2197s and h8s/2196s: n = 1 and 0.) bit : initial value : r/w : ???? ???? appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1083 of 1174 rej09b0329-0200 h'd12c: input capture register 1 icr1: psu 0 0 1 0 r 2 0 r 3 0 4 0 r 0 r 5 6 0 7 icr14 icr13 icr12 icr11 icr10 0 r icr17 r r r icr16 icr15 bit : initial value : r/w : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1084 of 1174 rej09b0329-0200 h'd12d: prescaler unit contro l/status register pcsr: psu 0 0 1 0 r/w 2 0 r/w 3 1 4 0 r/w 5 0 6 0 7 r/w r/w iceg r/w icie 0 r/(w) * icif ncon/off dcs2 dcs1 dcs0 note: * only 0 can be written to clear the flag. interrupt request by input capture is disabled (initial value) interrupt request by input capture is enabled 0 1 input capture interrupt enable bit frequency division clock output select bits description 0 0 0 pss, output /32 (initial value) dcs1 dcs0 dcs2 1 pss, output /16 1 0 pss, output /8 1 pss, output /4 0 1 0 psw, output w/32 1 psw, output w/16 1 0 psw, output w/8 1 psw, output w/4 input capture interrupt flag [clearing condition] (initial value) when 0 is written after reading 1 [setting condition] when input capture is executed at ic pin edge 0 1 noise cancel function of ic pin is disabled (initial value) noise cancel function of ic pin is enabled 0 1 noise cancel on/off bit ic pin edge select bit falling edge of ic pin input is detected (initial value) rising edge of ic pin input is detected 0 1 initial value : ? ? bit r/w : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1085 of 1174 rej09b0329-0200 h'd130: software trigger a/d result register h adrh: a/d converter h'd131: software trigger a/d result register l adrl: a/d converter adrh adrl 10 32 54 7 0 r 6 0 r 9 0 r 8 0 r 11 0 r 10 0 r 0 r 0 r 0 r adr9 adr8 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 0 r 12 13 14 15 0 0 0 0 0 0 bit : initial value : r/w : ?????? ?????? h'd132: hardware trigger a/d result register h ahrh: a/d converter h'd133: hardware trigger a/d result register l ahrl: a/d converter ahrh ahrl 10 32 54 7 0 r 6 0 r 9 0 r 8 0 r 11 0 r 10 0 r 0 r 0 r 0 r ahr9 ahr8 ahr7 ahr6 ahr5 ahr4 ahr3 ahr2 ahr1 ahr0 0 r 12 13 14 15 0 0 0 0 0 0 bit : initial value : r/w : ? ????? ? ????? appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1086 of 1174 rej09b0329-0200 h'd134: a/d control register adcr: a/d converter 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 5 0 6 1 7 r/w r/w r/w hch1 0 r/w ck hch0 sch3 sch2 sch1 sch0 clock select 0 conversion frequency = 266 states (initial value) 1 conversion frequency = 134 states hardware channel select bits hch1 hch2 analog input channel 0 0 an8 (initial value) 1 an9 1 0 ana 1 anb software channel select bits sch3 sch2 sch1 sch0 analog input channel 0 0 0 0 an0 (initial value) 1 an1 1 0 an2 1 an3 1 0 0 an4 1 an5 1 0 an6 1 an7 1 0 0 0 an8 1 an9 1 0 ana 1 anb 1 software-triggered conversion channel is not selected legend: * don't care. note: if conversion is started by software when sch3 to sch0 are set to 11xx, the conversion result is undetermined. hardware- or external-triggered conversion, however, will be performed on the channel selected by hch1 and hch0. initial value : ? ? bit r/w : : * * appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1087 of 1174 rej09b0329-0200 h'd135: a/d control/status register adcsr: a/d converter 0 0 1 0 r 2 0 r 3 0 4 0 r/w 5 0 6 7 r/(w) * r r/w adie 0 r/(w) * send sst hst busy scnl hend 1 a/d interrupt enable bit 0 interrupt (adi) upon a/d conversion end is disabled (initial value) 1 interrupt (adi) upon a/d conversion end is enabled software a/d start flag 0 read: indicates that software-triggered a/d conversion has ended or been stopped (initial value) write: software-triggered a/d conversion is aborted 1 read: indicates that software-triggered a/d conversion is in progress write: starts software-triggered a/d conversion busy flag 0 no contention for a/d conversion (initial value) 1 indicates an attempt to execute software-triggered a/d conversion while hardware- or external-triggered a/d conversion was in progress. software-triggered a/d conversion cancel flag 0 no contention for a/d conversion (initial value) 1 indicates that software-triggered a/d conversion was canceled by the start of hardware-triggered a/d conversion. hardware a/d status flag 0 read: hardware- or external-triggered a/d conversion is not in progress (initial value) write: hardware- or external-triggered a/d conversion is aborted 1 hardware- or external-triggered a/d conversion is in progress. software a/d end flag 0 [clearing condition] (initial value) when 0 is written after reading 1 1 [setting condition] when software-triggered a/d conversion has ended hardware a/d end flag 0 [clearing condition] (initial value) when 0 is written after reading 1 1 [setting condition] when hardware- or external-triggered a/d conversion has ended initial value : ? ? note: * only 0 can be written to clear the flag. bit r/w : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1088 of 1174 rej09b0329-0200 h'd136: a/d trigger select register adtsr: a/d converter 0 1 2 3 0 4 r/w 5 6 7 trgs1 0 r/w trgs0 11111 1 trigger select bits trgs1 trgs0 0 0 hardware- or external-triggered a/d conversion is disabled (initial value) 1 hardware-triggered (adtrg) a/d conversion is selected 1 0 hardware-triggered (dfg) a/d conversion is selected 1 external-triggered (adtrg) a/d conversion is selected initial value : ?????? ????? ? bit r/w : : h'd138: timer load register k tlk: timer j 0 1 1 1 w 2 1 w 3 1 4 1 w 5 1 6 1 7 w w w tlr25 w tlr26 1 w tlr27 tlr24 tlr23 tlr22 tlr21 tlr20 bit : initial value : r/w : h'd138: timer counter k tck: timer j 0 1 1 1 r 2 1 r 3 1 4 1 r 5 1 6 1 7 r r r tdr25 r tdr26 1 r tdr27 tdr24 tdr23 tdr22 tdr21 tdr20 bit : initial value : r/w : h'd139: timer load register j tlj: timer j 0 1 1 1 w 2 1 w 3 1 4 1 w 5 1 6 1 7 w w w tlr15 w tlr16 1 w tlr17 tlr14 tlr13 tlr12 tlr11 tlr10 bit : initial value : r/w : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1089 of 1174 rej09b0329-0200 h'd139: timer counter j tcj: timer j 0 1 1 1 r 2 1 r 3 1 4 1 r 5 1 6 1 7 r r r tdr15 r tdr16 1 r tdr17 tdr14 tdr13 tdr12 tdr11 tdr10 bit : initial value : r/w : h'd13a: timer mode register j tmj: timer j 0 0 1 0 r 2 0 r/w 3 0 4 0 r/w 5 0 6 0 7 r/w r/w r/w st r/w ps10 0 r/w ps11 8/16 ps21 ps20 tgl t/r tmj-2 toggle flag tmj-2 toggle output is 0 (initial value) tmj-2 toggle output is 1 0 1 timer output/remote-controller output select bit tmj-1 timer output (initial value) tmj-1 toggle output (data transmitted from remote controller) 0 1 tmj-1 and tmj-2 operate separately (initial value) tmj-1 and tmj-2 operate together as 16-bit 0 1 8-bit/16-bit operation select bit stop tmj-1 clock supply in remote control mode (initial value) start tmj-1 clock supply in remote control mode 0 1 remote-controlled operation start bit note: * external clock edge selection is set in the irq edge select register (iegr). see section 6.2.4, irq edge select register (iegr). when using external clock in remote control mode, set opposite edges for irq1 and irq2 edges (eg. when falling edge is set for irq1, set rising edge for irq2. when rising edge is set for irq1, set falling edge for irq2). 0 0 ps10 ps11 1 0 1 pss, count at /512 (initial value) pss, count at /256 pss, count at /4 1 count at rising/falling edge of external clock ( irq1 ) * tmj-1 input clock select bits description note: * external clock edge selection is set in the irq edge select register (iegr). see section 6.2.4, irq edge select register (iegr). 0 0 ps20 ps21 1 0 1 pss, count at /16384 (initial value) pss, count at /2048 count at tmj-1 underflow 1 count at rising/falling edge of external clock ( irq2 ) * tmj-2 input clock select bits description initial value : bit r/w : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1090 of 1174 rej09b0329-0200 h'd13b: timer j control register tmjc: timer j 0 1 0 2 0 r/w 3 4 0 r/w 5 0 6 0 7 r/w r/w mon1 r/w buzz0 0 r/w buzz1 mon0 tmj2ie tmj1ie 1 1 /4096 (initial value) buzz0 output signal buzz1 frequency when = 10 mhz /8192 2.44 khz 1.22 khz output monitor signal 00 1 10 1 output timer j buzz signal buzzer output select bits tmj2i interrupt request is disabled (initial value) tmj2i interrupt request is enabled 0 1 tmj2i interrupt enable bit ps22 used in combination with bits ps21 and ps20 to select the tmj-2 input clock. tmj1i interrupt request is disabled (initial value) tmj1i interrupt request is enabled 0 1 tmj1i interrupt enable bit pb or rec-ctl (initial value) mon0 mon1 dvctl output tca7 00 1 1 * monitor output select bits monitor output select note: * don't care. tmj-2 expansion function is enabled exn tmj-2 expansion function is disabled (initial value) 0 1 expansion function control bit description initial value : exn ps22 r/w r/w bit r/w : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1091 of 1174 rej09b0329-0200 h'd13c: timer j status register tmjs: timer j 0 1 2 3 4 5 6 0 7 r/(w) * tmj1i 0 r/(w) * tmj2i 11 1 1 11 note: * only 0 can be written to clear the flag. tmj1i interrupt request flag [clearing condition] (initial value) when 0 is written after reading 1 [setting condition] when tmj-1 underflows 0 1 tmj2i interrupt request flag [clearing condition] (initial value) when 0 is written after reading 1 [setting condition] when tmj-2 underflows 0 1 initial value : ?????? ?????? bit r/w : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1092 of 1174 rej09b0329-0200 h'd148: serial mode register smr1: sci1 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w asynchronous mode (initial value) clock synchronous mode 0 1 communication mode multiprocessor function is disabled (initial value) multiprocessor format is selected 0 1 multiprocessor mode clock select clock select 0 0 cks0 cks1 1 0 1 clock (initial value) /4 clock /16 clock 1 /64 clock 8-bit data 7-bit data * 0 1 character length note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted, and lsb-first/msb-first selection is not available. even parity * 1 odd parity * 2 0 1 parity mode notes: 1. when even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. when odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. 1 stop bits * 1 2 stop bits * 2 0 1 stop bit length notes: 1. in transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. 2. in transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. parity bit addition and checking disabled parity bit addition and checking enabled * 0 1 parity enable note: * when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in reception, the parity bit is checked for the parity (even or odd) specified by the o/ e bit. initial value : (initial value) (initial value) (initial value) (initial value) bit r/w : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1093 of 1174 rej09b0329-0200 h'd149: bit rate register brr1: sci1 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit : initial value : r/w : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1094 of 1174 rej09b0329-0200 h'd14a: serial control register scr1: sci1 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w transmit-data-empty interrupt (txi) request is disabled * (initial value) transmit-data-empty interrupt (txi) request is enabled 0 1 transmit interrupt enable bit note: * txi interrupt request cancellation can be performed by reading 1 from the tdre flag, then clearing it to 0, or clearing the tie bit to 0. receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request is disabled * (initial value) receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request is enabled 0 1 receive interrupt enable bit note: * rxi and eri interrupt request cancellation can be performed by reading 1 from the rdrf, fer, per, or orer flag, then clearing the flag to 0, or clearing the rie bit to 0. transmission is disabled * 1 (initial value) transmission is enabled * 2 0 1 transmit enable bit notes: 1. the tdre flag in ssr is fixed at 1. 2. in this state, serial transmission is started when transmit data is written to tdr and tdre flag in ssr is cleared to 0. smr setting must be performed to decide the transmission format before setting the te bit to 1. reception is disabled * 1 (initial value) reception is enabled * 2 0 1 receive enable bit notes: 1. clearing the re bit to 0 does not affect the rdrf, fer, per, and orer flags, which retain their states. 2. serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. smr setting must be performed to decide the reception format before setting the re bit to 1. multiprocessor interrupts are disabled (normal reception performed) (initial value) [clearing conditions] (1) when the mpie bit is cleared to 0 (2) when data with mpb = 1 is received multiprocessor interrupt are enabled * receive interrupt (rxi) requests, receive-error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr1 are disabled until data with the multiprocessor bit set to 1 is received. 0 1 multiprocessor interrupt enable bit note: * when receive data including mpb = 0 is received, receive data transfer from rsr to rdr, receive error detection, and setting of the rdrf, fer, and orer flags in ssr, is not performed. when receive data with mpb = 1 is received, the mpb bit in ssr is set to 1, the mpie bit is cleared to 0 automatically, and generation of rxi and eri interrup ts (when the tie and rie bits in scr are set to 1) and fer and orer flag setting is enabled. clock enable bits notes: 1. initial value 2. outputs a clock of the same frequency as the bit rate. 3. inputs a clock with a frequency 16 times the bit rate. clock select 0 0 internal clock/sck pin functions as i/o port * 1 (initial value) cke0 cke1 internal clock/sck pin functio ns as syn chronous cloc k output * 1 1 internal clock/sck pin functions as cl ock output * 2 internal clock/sck pin functio ns as syn chronous cloc k output 0 1 external clock/sck pin functions as clock input * 3 external clock/sck pin functions as synchronous clock input 1 external clock/sck pin functions as clock input * 3 asynchronous mode clock synchronous mode asynchronous mode clock synchronous mode asynchronous mode clock synchronous mode asynchronous mode clock synchronous mode external clock/sck pin functions as synchronous clock input transmit-end interrupt (tei) request is disabled * (initial value) transmit-end interrupt (tei) request is enabled * 0 1 transmit end interrupt enable bit note: * tei cancellation can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0 and clearing the tend flag to 0, or clearing the teie bit to 0. bit : initial value : r/w : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1095 of 1174 rej09b0329-0200 h'd14b: transmit data register tdr1: sci1 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit : initial value : r/w : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1096 of 1174 rej09b0329-0200 h'd14c: serial status register ssr1: sci1 data with a 0 multiprocessor bit is transmitted (initial value) data with a 1 multiprocessor bit is transmitted 0 1 multiprocessor bit transfer transmit data register empty [clearing condition] when 0 is written in tdre after reading tdre = 1 [setting conditions] (1) when the te bit in scr1 is 0 (2) when data is transferred from tdr1 to tsr1 and data can be written to tdr1 0 1 transmit end 0 [clearing condition] when 0 is written in tdre after reading tdre = 1 [setting conditions] (1) when the te bit in scr1 is 0 (2) when tdre = 1 at trasmission of the last bit of a 1-byte serial transmit character 1 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r multiprocessor bit 0 [clearing condition] * when data with a 0 multiprocessor bit is received [setting condition] when data with a 1 multiprocessor bit is reveived 1 note: * retains its previous state when the re bit in scr1 is cleared to 0 with multiprocessor format. [clearing condition] when 0 is written in per after reading per = 1 * 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr * 2 0 1 parity error notes: 1. the per flag is not affected and retains its previous state when the re bit in scr1 is cleared to 0. 2. if a parity error occurs, the receive data is transferred to rdr1 but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the per flag is set to 1. in synchronous mode, serial transmission cannot be continued, either. receive data register full [clearing condition] when 0 is written in rdrf after reading rdrf = 1 [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr 0 1 note: rdr and the rdrf flag are not affected and retain their previous values when an error is detected during reception or when the re bit in scr1 is cleared to 0. if reception of the next data is completed while the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost. overrun error [clearing condition] when 0 is written in orer after reading orer = 1 * 1 [setting condition] when the next serial reception is completed while rdrf = 1 * 2 0 1 notes: 1. the orer flag is not affected and retains its previous state when the re bit in scr1 is cleared to 0. 2. the receive data prior to the overrun error is retained in rdr1, and the data received subsequently is lost. also, subsequent serial reception cannot be continued while the orer flag is set to 1. in synchronous mode, serial transmission cannot be continued, either. framing error [clearing condition] when 0 is written in fer after reading fer = 1 * 1 [setting condition] when the sci checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0. * 2 0 1 notes: 1. the fer flag is not affected and retains its previous state when the re bit in scr1 is cleared to 0. 2. in 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. if a framing error occurs, the receive data is transferred to rdr1 but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the fer flag is set to 1. in synchronous mode, serial transmission cannot be continued, either. initial value : note: * only 0 can be written to clear the flag. (initial value) (initial value) (initial value) (initial value) (initial value) (initial value) (initial value) bit r/w : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1097 of 1174 rej09b0329-0200 h'd14d: receive data register rdr1: sci1 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit : initial value : r/w : h'd14e: serial interface mo de register scmr1: sci1 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 sdir 0 r/w 0 ? 0 ? 2 sinv 0 r/w 1 ? 1 ? data inversion tdr contents are transmitted (initial value) without modification. receive data is stored in rdr without modification. tdr contents are inverted before being transmitted. receive data is stored in rdr1 in inverted form. 0 1 tdr contents are transmitted lsb-first. (initial value) receive data is stored in rdr lsb-first. tdr contents are transmitted msb-first. receive data is stored in rdr msb-first. 0 1 data transfer direction initial value : bit r/w : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1098 of 1174 rej09b0329-0200 h'd158: i 2 c bus control register iccr1: i 2 c bus interface 7 ice 0 r/w 6 ieic 0 r/w 5 mst 0 r/w 4 trs 0 r/w 3 acke 0 r/w 0 scp 1 w 2 bbsy 0 r/w 1 iric 0 r/(w) * note: * only 0 can be written to clear the flag. i 2 c bus interface enable 0 i 2 c bus interface module disabled, with scl and sda signal pins (initial value) set to port function. sar and sarx can be accessed. 1 i 2 c bus interface module enabled for transfer operation (pins scl and sca are driving the bus). icmr and icdr can be accessed. i 2 c bus interface interrupt enable 0 interrupt request is disab led (initial value) 1 interrupt request is enabled acknowledge bit judgment selection 0 the value of the acknowledge bit is ignored, and continuous transfer is performed (initial value) 1 if the acknowledge bit is 1, continuous transfer is interrupted bus busy 0 bus is free (initial value) [clearing condition] when a stop condition is detected 1 bus is busy [setting condition] when a start condition is detected i 2 c bus interface interrupt request flag 0 waiting for transfer, or transfer in progress (initial value) [clearing condition] when 0 is written in iric after reading iric = 1 1 interrupt requested [setting conditions] ?i 2 c bus format master mode ? when a start condition is detected in the bus line state after a start condition is issued (when the tdre flag is set to 1 because of first frame transmission) ? when a wait is inserted between the data and acknowledge bit when wait = 1 ? at the end of data transfer (when the tdre or rdrf flag is set to 1) ? when a slave address is received after bus arbitration is lost (when the al flag is set to 1) ? when 1 is received as the acknowledge bit when the acke bit is 1 (when the ackb bit is set to 1) ?i 2 c bus format slave mode ? when the slave address (sva, svax) matches (when the aas and aasx flags are set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the tdre or rdrf flag is set to 1) ? when the general call address is detected (when the adz flag is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the tdre or rdrf flag is set to 1) ? when 1 is received as the acknowledge bit when the acke bit is 1 (when the ackb bit is set to 1) ? when a stop condition is detected (when the stop or estp flag is set to 1) ?synchronous serial format ? at the end of data transfer (when the tdre or rdrf flag is set to 1) ? when a start condition is detected with serial format selected ? when a condition, other than the above, that sets the tdre or rdrf flag to 1 is detected start condition/stop condition prohibit 0 writing 0 issues a start or stop condition, in combination with the bbsy flag 1 reading always returns a value of 1 (initial value) writing is ignored master/slave select transmit/receive select mst trs description 0 0 slave reveive mode (initial value) 1 slave transmit mode 1 0 master receive mode 1 master transmit mode bit : initial value : r/w : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1099 of 1174 rej09b0329-0200 h'd159: i 2 c bus status register icsr1: i 2 c bus interface 7 estp 0 r/(w) * 6 stop 0 r/(w) * 5 irtr 0 r/(w) * 4 aasx 0 r/(w) * 3 al 0 r/(w) * 0 ackb 0 r/w 2 aas 0 r/(w) * 1 adz 0 r/(w) * note: * only 0 can be written to clear the flag. error stop condition detection flag 0 no error stop condition (initial value) [clearing conditions] (1) when 0 is written in estp after reading estp = 1 (2) when the iric flag is cleared to 0 1 ? in i 2 c bus format slave mode error stop condition detected [setting condition] ? when a stop condition is detected during frame transfer ? in other mode no meaning normal stop condition detection flag 0 no normal stop condition (initial value) [clearing conditions] (1) when 0 is written in stop after reading stop = 1 (2) when the iric flag is cleared to 0 1 ? in i 2 c bus format slave mode normal stop condition detected [setting condition] ? when a stop condition is detected after completion of frame transfer ? in other mode no meaning i 2 c bus interface continuous transmission/reception interrupt request flag 0 waiting for transfer, or transfer in progress (initial value) [clearing conditions] (1) when 0 is written in irtr after reading irtr = 1 (2) when the iric flag is cleared to 0 1 continuous transfer state [setting conditions] ? in i 2 c bus interface slave mode ? when the tdre or rdrf flag is set to 1 when aasx = 1 ? in other mode ? when the tdre or rdrf flag is set to 1 second slave address recognition flag 0 second slave address not recognized (initial value) [clearing con ditions] (1) when 0 is written in aasx after reading aasx = 1 (2) when a start condition is detected (3) in master mode 1 second slave address recognized [setting condition] when the second slave address is detected in slave receive mode arbitration lost flag 0 bus arbitration won (initial value) [clearing conditions] (1) when icdr data is written (transmit mode) or read (receive mode) (2) when 0 is written in al after reading al = 1 1 arbitration lost [setting conditions] (1) if the internal sda and sda pin disagree at the rise of scl in master transmit mode (2) if the internal scl line is high at the fall of scl in master transmit mode slave address recognition flag 0 slave address or general call address not recognized (initial value) [clearing conditions] (1) when icdr data is written (transmit mode) or read (receive mode) (2) when 0 is written in aas after reading aas = 1 (3) in master mode 1 slave address or general call address recognized [setting condition] when the slave address or general call address is detected when fs = 0 in slave receive mode general call address recognition flag 0 general call address not recognized (initial value) [clearing conditions] (1) when icdr data is written (transmit mode) or read (receive mode) (2) when 0 is written in adz after reading adz = 1 (3) in master mode 1 general call address recognized [setting condition] when the general call address is detected when fsx = 0 or fs = 0 in slave receive mode acknowledge bit 0 receive mode: 0 is output at acknowledge output timing (initial value) transmit mode: indicates that the receiving device has acknowldeged the data (signal is 0) 1 receive mode; 1 is output at acknowledge output timing transmit mode: indicates that the receiving device has not acknowldeged the data (signal is 1) bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1100 of 1174 rej09b0329-0200 h'd15e: i 2 c bus data register icdr1: i 2 c bus interface 7 icdr7 ? r/w 6 icdr6 ? r/w 5 icdr5 ? r/w 4 icdr4 ? r/w 3 icdr3 ? r/w 0 icdr0 ? r/w 2 icdr2 ? r/w 1 icdr1 ? r/w : : : bit note: refer to section 23.2.1, i 2 c bus data register (icdr). initial value r/w h'd15e: second slave address register sarx1: i 2 c bus interface 7 svax6 0 r/w 6 svax5 0 r/w 5 svax4 0 r/w 4 svax3 0 r/w 3 svax2 0 r/w 0 fsx 1 r/w 2 svax1 0 r/w 1 svax0 0 r/w : : : bit note: refer to section 23.2.3, second slave address register (sarx), and section 23.2.2, slave address register (sar). initial value r/w format select used combined with fs bit in sar. appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1101 of 1174 rej09b0329-0200 h'd15f: i 2 c bus mode register icmr1: i 2 c bus interface 7 mls 0 r/w 6 wait 0 r/w 5 cks2 0 r/w 4 cks1 0 r/w 3 cks0 0 r/w 0 bc0 0 r/w 2 bc2 0 r/w 1 bc1 0 r/w msb-first/lsb-first select 0 msb-first (initial value) 1 lsb-first wait insertion bit 0 data and acknowledge bits transferred consecutively (initial value) 1 wait inserted between data and acknowledge bits transfer clock select bits bit counter bit/frame bc2 bc1 bc0 clock sync i 2 c bus format serial format 0 0 0 8 9 (initial value) 1 1 2 1 0 2 3 1 3 4 0 0 0 4 5 1 5 6 1 0 6 7 1 7 8 bit : initial value : r/w : note: * see bit 6 in stcr. iicx * cks2 cks1 cks0 clock transfer rate = 8 mhz = 10 mhz 0 0 0 0 /28 286 khz 357 khz 1 /40 200 khz 250 khz 1 0 /48 167 khz 208 khz 1 /64 125 khz 156 khz 1 0 0 /80 100 khz 125 khz 1 /100 80.0 khz 100 khz 1 0 /112 71.4 khz 89.3 khz 1 /128 62.5 khz 78.1 khz 1 0 0 0 /56 143 khz 179 khz 1 /80 100 khz 125 khz 1 0 /96 83.3 khz 104 khz 1 /128 62.5 khz 78.1 khz 1 0 0 /160 50.0 khz 62.5 khz 1 /200 40.0 khz 50.0 khz 1 0 /224 35.7 khz 44.6 khz 1 /256 31.3 khz 39.1 khz appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1102 of 1174 rej09b0329-0200 h'd15f: slave address register sar1: i 2 c bus interface 7 sva6 0 r/w 6 sva5 0 r/w 5 sva4 0 r/w 4 sva3 0 r/w 3 sva2 0 r/w 0 fs 0 r/w 2 sva1 0 r/w 1 sva0 0 r/w format select bit ddcswr sar sarx format select bit 6 bit 0 bit 0 sw fs fx 0 0 0 i 2 c bus format ? sar and sarx slave addresses recognized 1 i 2 c bus format (initial value) ? sar slave address recognized ? sarx slave address ignored 1 0 i 2 c bus format ? sar slave address ignored ? sarx slave address recognized 1 i 2 c bus format ? sar and sarx slave addresses ignored 1 0 0 formatless transfer (start and stop conditions are not detected) 1 ? with acknowledge bit 1 0 formatless transfer * (start and stop conditions are not detected) 1 ? without acknowledge bit bit initial value r/w : : : note: * do not use this setting when automatically switching the made from formatless transfer to i 2 c bus format by setting ddcswr. appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1103 of 1174 rej09b0329-0200 h'd200 to h'd20b: row registers 1 to 12 cline1 to cline12: osd 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 7 clun0 krn kgn kbn klun 0 r/w bptnn 6 0 r/w szn r/w r/w clun1 bit initial value r/w character size specification bit 0 character display size: single height single width (initial value) 1 character display size: double height double width button pattern specification bit 0 pattern causing buttons in the nth row to appear to be raised (initial value) 1 pattern causing buttons in the nth row to appear to be lowered cursor brightness/halftone level specification bit (cursor colors in text display mode) (cursor brightness in text display mode) (cursor colors in superimposed mode) character brightness specification bits bit 0 cursor color cursor brightness level klun 0 black 1 0 blue, green, cyan, 1 red, yellow, magenta 0 white 1 bit 5 bit 4 character color character brightness level clun1 clun0 0 0 black 1 1 0 1 0 0 blue, green, 1 cyan, red, 1 0 yellow, 1 magenta 0 0 white 1 1 0 1 bit 0 character brightness level klun 0 1 : : : note: all brightness levels are with reference to the pedestal level (5 ire). brightness levels are reference values. n = 1 to 12 note: all brightness levels are with reference to the pedestal level (5 ire). brightness levels are reference values. (halftone levels in superimposed mode) cursor color specification bits bit 3 bit 2 bit 1 character brightness level krn kgn kbn cursor color (c.video output) cursor color (r, g, b output) 0 0 0 1 1 0 specification invalid 1 (halftone display in 1 0 0 superimposed mode) 1 1 0 1 bit 3 bit 2 bit 1 character brightness level krn kgn kbn cursor color (c.video output) cursor color (r, g, b output) ntsc pal 0 0 0 black black black (initial value) 1 blue 1 0 7 /4 7 /4 1 3 /2 3 /2 1 0 0 /2 /2 1 3 /4 3 /4 1 0 same phase 0 0 ire (initial value) 10 ire 20 ire 30 ire 25 ire (initial value) 45 ire 55 ire 65 ire 45 ire (initial value) 70 ire 80 ire 90 ire green cyan red magenta yellow white black (initial value) blue green cyan red magenta yellow white 0 ire (initial value) 25 ire 25 ire (initial value) 45 ire 45 ire (initial value) 55 ire 50% halftone (initial value) 30% halftone 1 white white note: n = 1 to 12 appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1104 of 1174 rej09b0329-0200 h'd20c: vertical display position register vpos: osd 8 0 9 0 r/w 10 0 r/w 11 0 12 1 ? 1 ? 13 15 ? vspc2 vspc1 vspc0 vp8 1 ? ? 14 1 ? ? r/w r/w ? bit initial value r/w vertical row interval specification bits vertical display start position specification bits vspc2 vspc1 vspc0 description 0 0 0 no row interval 1 row interval: one scanning line 1 0 row interval: two scanning lines 1 row interval: three scanning lines 1 0 0 row interval: four scanning lines 1 row interval: five scanning lines 1 0 row interval: six scanning lines 1 row interval: seven scanning lines : : : 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 7 vp4 vp3 vp2 vp1 vp0 0 r/w vp7 6 0 r/w vp6 r/w r/w vp5 bit initial value r/w : : : h'd20e: horizontal display position register hpos: osd 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 7 hp4 hp3 hp2 hp1 hp0 0 r/w hp7 6 0 r/w hp6 r/w r/w hp5 bit initial value r/w : : : horizontal display start position specification bits appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1105 of 1174 rej09b0329-0200 h'd20f: digital output specifi cation register dout: osd 0 0 1 1 ? 2 0 r/w 3 0 4 0 r/w 0 r/w 5 7 dobc dsel crsel ? ? 0 ? ? 6 0 r/w rgbc ? r/w ycoc r, g, b digital output specification bit 0 1 yco digital output specification bit 0 1 monitor signal switching bit 0 1 digital output blink control bit ram dout description bit 15 bit 4 blnk dobc 0 0 does not blink (initial value) 1 does not blink 1 0 does not blink 1 blinks : : : r, g, b, yco, ybo pin function select bit 0 r, g, b, yco, ybo output function is selected (initial value) 1 data slicer monitor output function is selected bit initial value r/w character output is specified (initial value) combined character, border, cursor, background, and button output is specified character output is specified (initial value) combined character and border output is specified r pin = signal selected by bit 2 (crsel) g pin = slice data signal analog-compared with cvin2 b pin = sampling clock generated within data slicer yco pin = external hsync signal (afch) synchronized within the lsi ybo pin = external vsync signal (afcv) synchronized within the lsi clock run-in detection window signal output is selected (initial value) start bit detection window signal output is selected appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1106 of 1174 rej09b0329-0200 h'd210: screen control register dcntl: osd 8 0 9 0 r/w 10 0 ? 11 0 12 0 r/w 0 r/w 13 14 15 blks osdon ? edge edgc 0 r/w r/w vdspon dispm r/w r/w lacem 0 osd display start bit cdspon osdon description 0/1 0 0 1 1 1 osd c. video display enable bit 0 osd c.video display is off (initial value) 1 osd c.video display is on border specification bit 0 no character border (initial value) 1 character border superimposed/text display mode select bit 0 superimposed mode is selected (initial value) 1 text display mode is selected blinking period select bit tvm2 blks description 0 0 1 1 0 1 interlaced/noninterlaced display select bit 0 0 noninterlaced display is selected (initial value) 1 interlaced display is selected border color specification bit bit 8 border color (in text display mode) edgc border color (c.video output) border color (r,g,b output) 0 black black (initial value) 1 white white bit 8 border color (in superimposed mode) edgc c.video output r,g,b output 0 specification invalid (black) black (initial value) 1 white : : : (tvm2 is bit15 in dform) approx. 0.5 sec (32/fv = 0.53 sec) (initial value) approx. 1.0 sec (64/fv = 1.07 sec) approx. 0.5 sec (32/fv = 0.64 sec) approx. 1.0 sec (64/fv = 1.28 sec) osd display is stopped (c.video output and digital output both off) (initial value) osd display is started (digital output only) osd display is started (both c.video output and digital output enabled) bit initial value r/w appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1107 of 1174 rej09b0329-0200 h'd211: screen control register dcntl: osd 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 7 blu1 blu0 camp kamp bamp 0 r/w br 6 0 r/w bg r/w r/w bb background chroma select bit 0 1 cursor chroma select bit 0 1 character chroma select bit 0 character chroma amplitude: 60 ire (initial value) 1 character chroma amplitude: 80 ire background brightness select bits bul1 bul0 description 0 0 background brightness, 10ire (initial value) 1 background brightness, 30ire 1 0 background brightness, 50ire 1 background brightness, 70ire : : : background color specification (background colors in text display mode) (background colors in superimposed mode) bit 7 bit 6 bit 5 description br bg bb background color ( c.video output) background color ( r, g, b outputs) 0 0 0 1 1 0 1 specification 1 0 0 invalid 1 1 0 1 bit 7 bit 6 bit5 description br bg bb background color ( c.video output) background color ( r, g, b outputs) ntsc pal 0 0 0 black black 1 1 0 7 /4 7 /4 1 3 /2 3 /2 1 0 0 /2 /2 1 3 /4 3 /4 1 0 same phase 0 1 white white black (initial value) blue green cyan red magenta yellow white black (initial value) blue green cyan red magenta yellow white cursor chroma amplitude: 60 ire (initial value) cursor chroma amplitude: 80 ire background chroma amplitude: 60 ire (initial value) background chroma amplitude: 80 ire bit initial value r/w appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1108 of 1174 rej09b0329-0200 h'd212: osd format register dform: osd 8 0 9 0 r/w 10 0 ? 11 0 12 0 r/w 0 r/w 13 15 fscin fscext ? osdve osdvf 0 r/w tvm2 14 0 r/w tvm1 r/(w) * 1 r/w tvm0 notes: 1. only 0 can be written to clear the flag. 2. the 4fsc and 2fsc frequencies for secam do not conform to the secam tv format specifications. bit 15 bit 14 bit 13 bit 12 description tvm2 tvm1 tvm0 fscin tv format 4fsc (mhz) 2fsc (mhz) 0 0 0 0 m/ntsc 14.31818 ? 1 ? ? 7.15909 0 17.734475 0 0 1 4.43-ntsc (17.734470) 1 ? 8.867235 (8.867238) 0 1 0 0 m/pal 14.302446 ? (14.302444) 1 ? 7.15122298 0 1 1 0/1 must not be specified 1 0 0 0 n/pal 14.328225 (14.28244) ? 1 ? 7.1641125 1 0 1 0/1 must not be specified 0 b,g,h/pal 17.734475 ? 1 1 0 i/pal (17.734476) 1 d,k/pal ? 8.867235 (8.867238) 0 b,g,h/secam * 2 17.734475 ? 1 1 1 l/secam (17.734470) 1 d,k,k1/secam ? 8.867235 (8.867238) osdv interrupt enable bit 0 1 4/2fsc external input select bit 0 1 4/2fsc input select bit tv format select bits 0 1 osdv interrupt flag : : : 0 1 bit initial value r/w ? 4fsc input is selected (initial value) 2fsc input is selected 4/2fsc oscillator uses a crystal oscillator (initial value) 4/2fsc uses a dedicated amplifier circuit for external clock signal input the osdv interrupt is disabled (initial value) the osdv interrupt is enabled [clearing condition] when 0 is written after reading 1 (initial value) [setting condition] when osd detects the vsync signal appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1109 of 1174 rej09b0329-0200 h'd213: osd format register dform: osd 0 0 1 0 r/w 2 0 r/w 3 1 4 1 ? 1 ? 5 7 ? ? dtmv ldreq vacs 1 ? ? 6 1 ? ? r/(w) * ? ? writing: 0 1 reading: 0 1 osd display update timing control bit 0 1 : : : master slave ram transfer state bit master slave ram transfer state bit 0 1 after the ldreq bit is written to 1, data is transferred from master ram to slave ram regardless of the vsync signal (osdv). the osd display is updated simultaneously with register * rewriting. note: * when transferring data using this setting, do not have the osd display data (initial value) after the ldreq bit is written to 1, data is transferred from master ram to slave ram synchronously with the vsync signal (osdv). after rewriting the register, the osd display is updated synchronously with the vsync signal (osdv). note: * the registers and register bits whose settings are reflected in the osd display are the row registers (cline), vertical display position register (vpos), horizontal display position register (hpos), screen control register (dcntl) except bit 13, and the rgbc, ycoc, and dobc bits of the digital output specification register (dout). data is not being transferred from master ram to slave ram (initial value) data is being transferred from master ram to slave ram, or is being prepared for transfer. after transfer is completed, this bit is cleared to 0 requests abort of data transfer from master ram to slave ram requests transfer of data from master ram to slave ram. after transfer is completed, this bit is cleared to 0 the cpu did not access osdram during data transfer (initial value) the cpu accessed osdram during data transfer; the access is invalid bit initial value r/w appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1110 of 1174 rej09b0329-0200 h'd800 to h'daff: display data ram osdram: osd 8 * 9 * r/w 10 * r/w 11 * 12 * r/w * r/w 13 15 bon0 cr cg cb c8 * r/w blnk 14 * r/w ht/cr r/w r/w bon1 halftone/cursor display specification bit dispm ht/cr 0 0 1 1 0 1 button specification bits bptnn bon1 bon0 description 0 0 0 1 1 0 1 1 0 0 1 1 0 1 : : : character color specification bits character codes specification cr cg cb character color (c.video output) character color (r, g, b output) ntsc pal 0 0 0 black black black 1 blue 1 0 7 /4 7 /4 green 1 3 /2 3 /2 cyan 1 0 0 /2 /2 red 1 3 /4 3 /4 magenta 1 0 same phase 0 yellow 1 white white white rgbc ht/cr 0 0/1 1 0 1 blinking specification bit 0 1 dobc blnk 0 0 1 1 0 1 (dobc is bit 4 in dout) (rgbc is bit 6 in dout) (dispm is bit 14 in dcntl) bit initial value r/w 0 * 1 * r/w 2 * r/w 3 * 4 * r/w * r/w 5 7 c4 c3 c2 c1 c0 * r/w c7 6 * r/w c6 r/w r/w c5 : : : character codes bit initial value r/w blinking is off blinking is on digital output (yco, r, g, b) blinking is off blinking is off blinking is off blinking is on c.video output halftone is off halftone is on cursor display is off cursor display is on digital output (r, g, b) character is output (halftone/cursor specification invalid) character is output (halftone/cursor display off) cursor color data specified by the cursor color specification bit of row register is output no button is displayed button is displayed (start) button is displayed (end) button is displayed (one character) no button is displayed button is displayed (start) button is displayed (end) button is displayed (one character) appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1111 of 1174 rej09b0329-0200 h'd220: slice even-field mode register sevfd: data slicer 8 0 9 0 r/w 10 0 r/w 11 0 12 0 r/w 1 ? 13 15 stbe4 stbe3 stbe2 stbe1 stbe0 0 r/w evnie 14 0 r/(w) * evnif r/w r/w ? even field slice completion interrupt enable flag 0 1 even field slice interrupt completion flag 0 1 : : : start bit detection starting position bits 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 7 dlye4 dlye3 dlye2 dlye1 dlye0 0 r/w slvle2 6 0 r/w slvle1 r/w r/w slvle0 slice level setting bits slvle2 slvle1 slvle0 description 0 0 0 1 1 0 1 1 0 0 1 1 0 1 : : : even field data sampling clock delay time slice level is 0 ire (initial value) slice level is 5 ire slice level is 15 ire slice level is 20 ire slice level is 25 ire slice level is 35 ire slice level is 40 ire must not be specified note: all slice levels are with reference to the pedestal level (5 ire). slice level values are provided for reference. note: * only 0 can be written to clear the flag. bit initial value r/w bit initial value r/w disables even-field slice completion interrupt (initial value) enables even-field slice completion interrupt [clearing condition] when 0 is written after reading 1 (initial value) [setting condition] when data slicing is completed for all specified lines of even field appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1112 of 1174 rej09b0329-0200 h'd222: slice odd-field mode re gister sodfd: data slicer 8 0 9 0 r/w 10 0 r/w 11 0 12 0 r/w 1 ? 13 15 stbo4 stbo3 stbo2 stbo1 stbo0 0 r/w oddie 14 0 r/(w) * oddif r/w r/w ? 0 1 0 1 : : : 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 7 dlyo4 dlyo3 dlyo2 dlyo1 dlyo0 0 r/w slvlo2 6 0 r/w slvlo1 r/w r/w slvlo0 : : : odd field data sampling clock delay time start bit detection starting position bits slice level setting bits slvlo2 slvlo1 slvlo0 description 0 0 0 1 1 0 1 1 0 0 1 1 0 1 note: * only 0 can be written to clear the flag. note: all slice levels are with reference to the pedestal level (5 ire). slice level values are provided for reference. bit initial value r/w slice level is 0 ire (initial value) slice level is 5 ire slice level is 15 ire slice level is 20 ire slice level is 25 ire slice level is 35 ire slice level is 40 ire must not be specified odd field slice completion interrupt enable flag odd field slice interrupt completion flag disables odd-field slice completion interrupt (initial value) enables odd-field slice completion interrupt [clearing condition] when 0 is written after reading 1 (initial value) [setting condition] when data slicing is completed for all specified lines of odd field bit initial value r/w appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1113 of 1174 rej09b0329-0200 h'd224 to h'd227: slice line setting registers 1 to 4 sline1 to sline4: data slicer 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 1 ? 5 7 slinen4 * slinen3 * slinen2 * slinen1 * slinen0 * 0 r/w senbln * 6 0 r/w sfldn * r/w r/w ? field setting bit 0 1 slice enable bit 0 1 : : : slice line setting bit bit initial value r/w [when read] disables data slice operation for the specified lines [clearing condition] when the data slice operation for the line has been completed enables data slice operation for the specified lines even field (initial value) odd field note: n = 1 to 4 (h8s/2197s and h8s/2196s: n=1 and 0.) appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1114 of 1174 rej09b0329-0200 h'd228 to h'd22b: slice detect ion registers 1 to 4 sdtct1 to sdtct4: data slicer 0 0 1 0 r 2 0 r 3 0 4 1 ? 0 r 5 7 ? cricn3 * cricn2 * cricn1 * cricn0 * 0 r crdfn * 6 0 r sbdfn * r r endfn * data end detection flag 0 1 start bit detection flag 0 1 clock run-in detection flag 0 1 : : : clock run-in count value bit initial value r/w clock run-in not detected for line for data slicing (initial value) clock run-in detected for line for data slicing start bit not detected for line for data slicing (initial value) start bit detected for line for data slicing data end not detected for line for data slicing (initial value) data end detected for line for data slicing note: n = 1 to 4 (h8s/2197s and h8s/2196s: n=1 and 0.) h'd22c to h'd232: slice da ta registers 1 to 4 sdat a1 to sdata4: data slicer 15 * note: * undetermined r 14 * r 13 * r 12 * r 11 * r 10 * r 9 * r 8 * r 7 * r 6 * r 5 * r 4 * r 3 * r 2 * r 1 * r 0 * r : : : bit initial value r/w appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1115 of 1174 rej09b0329-0200 h'd240: sync separation input mode register sepimr: sync separator 0 0 1 0 r/w 2 0 r/w 3 0 4 5 6 0 7 r/w r/w vsel ccmpv1 r/w r/w ccmpv0 r/w ccmpsl * r/w synct dlpfon ? frqsel 00 0 digital lpf control 0 1 reference clock frequency select 0 1 vsync input signal select 0 1 csync separation comparator input select note: * when this bit is set to 1, it must be set to 1 by the instruction following the module stop release instruction in the interrupt-prohibited state. orc #b'10000000, ccr interrupt prohibited bclr.b #1, @mstpcrh module stop release bset.b #5, @sepimr sets ccmpsl bit to 1 andc #b'01111111, ccr interrupt permitted 0 1 0 (initial value) 1 sync signal polarity select : : : csync separation comparator slicing voltage select description 0 0 ccmpv1 ccmpv0 1 0 1 1 bit initial value r/w the csync slicing level is 10 ire (initial value) the csync slicing level is 5 ire the csync slicing level is 15 ire the csync slicing level is 20 ire the csync separation comparator input is selected the csync/hsync terminal operates as an output terminal (initial value) the csync schmitt input is selected the csync/hsync terminal operates as an input terminal vsync schmitt input (initial value) csync schmitt input the digital lpf does not operate (initial value) the digital lpf operates 576 times the horizontal sync frequency (initial value) 448 times the horizontal sync frequency appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1116 of 1174 rej09b0329-0200 h'd241: sync separation control register sepcr: sync separator 0 0 1 0 r/w 2 0 r/w 3 0 4 5 6 0 7 r r/w hcksel r/w afcvie r/(w) * afcvif r/w vcksl r/w vcmpon hhkon hhkon2 fld 00 0 hhk forcibly turned on 0 1 field detection flag 0 1 internal csync generator clock source select 0 1 v complement function control 0 1 v complement and mask counter clock source select 0 1 : : : external vsync interrupt flag 0 1 external vsync interrupt enable 0 1 bit initial value r/w note: * only 0 can be written to clear the flag the external vsync interrupt is disabled (initial value) the external vsync interrupt is enabled [clearing condition] 1 is read, then 0 is written (initial value) [setting condition] the v complement and mask counter detects the external vsync signal (afcv signal) double the frequency of the horizontal sync signal (afch signal) for the afc (initial value) double the frequency of the horizontal sync signal (osch signal) for the h complement and mask counter the v complement function is disabled (initial value) the v complement function is enabled 4/2 fsc clock (initial value) afc reference clock the hhk is not operated when complementary pulses are interpolated three successive times (initial value) the hhk is forcibly operated when complementary pulses are interpolated three successive times even field (initial value) odd field hhk forcibly turned on 2 0 1 the hhk is not forcibly operated during the v blanking period (initial value) the hhk is forcibly operated during the v blanking period appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1117 of 1174 rej09b0329-0200 h'd242: sync separation afc control register sepacr: sync separator 0 0 1 0 r/w 2 0 r/w 3 0 4 5 6 0 7 r/w ? ? r/w ndetie r/(w) * ndetif r/w hsel ? ? arst dotcksl dsl32b 01 0 afc reset control 0 1 reference hsync signal select 0 1 : : : noise detection interrupt flag 0 1 noise detection interrupt enable 0 1 bit initial value r/w note: * only 0 can be written to clear the flag. the noise detection interrupt is disabled (initial value) the noise detection interrupt is enabled [clearing condition] 1 is read, then 0 is written (initial value) [setting condition] the noise detection counter value matches the noise detection level register value the external hsync signal is selected (initial value) the internally generated hsync signal is selected the reset function is disabled (initial value) the reset function is enabled dsl32b bit 0 1 16-bit mode is set for the slice operation (initial value) 32-bit mode is set for the slice operation dotcksl bit 0 1 the reference clock of the afc circuit is selected for the dot clock. (initial value) the 4/2 fsc clock is selected for the dot clock. h'd243: horizontal sync signal threshold register hvthr: sync separator 0 1 2 hvth2 3 hvth3 0 4 hvth4 w www 5 ? ? 6 ? ? 7 ? ? hvth1 0 w hvth0 11100 0 horizontal sync signal threshold : : : bit initial value r/w note: refer to section 27.2.4, horizontal sync signal threshold register (hvthr) appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1118 of 1174 rej09b0329-0200 h'd244: vertical sync signal threshold register vvthr: sync separator 0 1 2 vvth2 3 vvth3 0 4 vvth4 w w w w www 5 vvth5 6 vvth6 7 vvth7 vvth1 0 w vvth0 00000 0 : : : vertical sync signal threshold note: refer to section 27.2.5, vertical sync signal threshold register (vvthr) bit initial value r/w h'd245: field detection window register fwidr: sync separator 0 1 2 fwid2 3 fwid3 0 4 ? ? w ww 5 ? ? 6 ? ? 7 ? ? fwid1 0 w fwid0 11110 0 : : : field detection window timing note: refer to section 27.2.6, field detection window register (fwidr) bit initial value r/w h'd246: h complement and mask timing register hcmmr: sync separator 1 0 32 54 7 0 w 6 0 w 9 0 w 8 0 w 11 0 w 10 0 w 0 w 0 w 0 w hc8 hc7 hc6 hc5 hc4 hc3 hc2 hc1 hc0 hm6 w hm5 w hm4 w hm3 w hm2 w hm1 w hm0 0 w 12 13 14 15 0 0 0 0 0 0 : : : hhk clearing timing complementary pulse generation timing note: refer to section 27.2.7, h complement and mask timing register (hcmmr) bit initial value r/w appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1119 of 1174 rej09b0329-0200 h'd248: noise detection counter ndetc: sync separator 0 1 2 nc2 3 nc3 0 4 nc4 r r r r rrr 5 nc5 6 nc6 7 nc7 nc1 0 r nc0 000000 : : : note: refer to section 27.2.8, noise detection counter (ndetc) bit initial value r/w h'd248: noise detection level register ndetr: sync separator 0 1 2 nr2 3 nr3 0 4 nr4 w w w w www 5 nr5 6 nr6 7 nr7 nr1 0 w nr0 00000 0 noise detection level : : : note: refer to section 27.2.9, noise detection level register (ndetr) bit initial value r/w appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1120 of 1174 rej09b0329-0200 h'd249: data slicer detection window register ddetwr: sync separator 0 0 1 0 w 2 0 w 3 0 4 5 6 0 7 w w crwde1 w srwde1 w srwde0 w srwds1 w srwds0 crwde0 crwds1 crwds0 00 0 : : : start bit detection window signal falling timing setting start bit detection window signal rising timing setting clock run-in detection window signal falling timing setting clock run-in detection window signal rising timing setting description 0 0 srwde1 srwde0 1 0 1 1 description 0 0 srwds1 srwds0 1 0 1 1 description 0 0 crwde1 crwde0 1 0 1 1 description 0 0 crwds1 crwds0 1 0 1 1 bit initial value r/w the detection ends about 29.5 s after the slicer start point (initial value) the detection ends about 29.0 s after the slicer start point the detection ends about 30.0 s after the slicer start point this setting must not be used the detection ends about 23.5 s after the slicer start point (initial value) the detection ends about 23.0 s after the slicer start point the detection ends about 24.0 s after the slicer start point this setting must not be used the detection starts about 23.5 s after the slicer start point (initial value) the detection starts about 23.0 s after the slicer start point the detection starts about 24.0 s after the slicer start point this setting must not be used the detection starts about 10.5 s after the slicer start point (initial value) the detection starts about 10.0 s after the slicer start point the detection starts about 11.0 s after the slicer start point this setting must not be used appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1121 of 1174 rej09b0329-0200 h'd24a: internal sync frequency register infrqr: sync separator 0 0 1 0 ? 2 0 ? 3 0 4 5 6 0 7 ? ? ? w vfs2 w vfs1 w hfs ? ???? 00 0 : : : hsync frequency selection bit description pal hfs bit 5 fsc/283.75 (initial value) fsc/283.5 mpal fsc/227.25 (initial value) fsc/227.5 npal fsc/229.25 (initial value) fsc/229.5 0 1 vsync frequency selection bit vfs2 bit 7 0 description pal vfs1 bit 6 fh/313 (initial value) fh/314 mpal fh/263 (initial value) fh/266 npal fh/313 (initial value) fh/314 0 1 fh/310 fh/262 fh/310 10 fh/312 fh/264 fh/312 1 bit initial value r/w appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1122 of 1174 rej09b0329-0200 h'ffb0 to h'ffb2: trap address register 0 tar0: atc h'ffb3 to h'ffb5: trap address register 1 tar1: atc h'ffb6 to h'ffb8: trap address register 2 tar2: atc 0 0 1 0 r/w 2 0 r/w 3 4 5 6 7 r/w a18 a17 a16 0 0 r/w 0 r/w r/w a23 a22 a21 0 0 r/w r/w a20 a19 0 0 1 0 r/w 2 0 r/w 3 4 5 6 7 r/w a10 a9 a8 0 0 r/w 0 r/w r/w a15 a14 a13 0 0 r/w r/w a12 a11 0 1 0 r/w 2 0 r/w 3 4 5 6 7 a2 a1 0 0 r/w 0 r/w r/w a7 a6 a5 0 0 r/w r/w a4 a3 0 bit : initial value : r/w : bit : initial value : r/w : bit : initial value : r/w : ? ? appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1123 of 1174 rej09b0329-0200 h'ffb9: address trap control register atcr: atc 0 0 1 0 r/w 2 0 r/w 3 1 4 1 5 1 6 1 7 r/w trc2 trc1 trc0 1 trap control 0 0 address trap function 0 is disabled (initial value) 1 address trap function 0 is enabled trap control 1 0 address trap function 1 is disabled (initial value) 1 address trap function 1 is enabled trap control 2 0 address trap function 2 is disabled (initial value) 1 address trap function 2 is enabled bit : initial value : r/w : ???? ? ???? ? appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1124 of 1174 rej09b0329-0200 h'ffba: timer mode register a tma: timer a 0 0 1 0 r/w 2 0 r/w 3 0 4 1 5 1 6 0 7 r/w r/w r/w tmaie 0 r/(w) * tmaov tma3 tma2 tma1 tma0 note: * only 0 can be written to clear the flag. [clearing condition] (initial value) when 0 is written to tmaov after reading tmaov = 1 [setting condition] when tca overflows 0 1 timer a overflow flag interrupt request by timer a (tmai) is disabled (initial value) interrupt request by timer a (tmai) is enabled 0 1 timer a interrupt enable bit timer a clock source is pss (initial value) timer a clock source is psw 0 1 clock source, prescaler select bit pss, /16384 (initial value) tma1 tma0 tma2 prescaler frequency division rate (interval timer) or overflow frequency (time-base) operation mode pss, /8192 pss, /4096 pss, /1024 0 tma3 pss, /512 pss, /256 pss, /64 pss, /16 1 s interval timer mode clock time base mode 0.5 s 0.25 s 0.03125 s 0 1 0 1 1 clear psw and tca to h'00 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 clock select bits note: = f osc bit : initial value : r/w : ? ? ? ? appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1125 of 1174 rej09b0329-0200 h'ffbb: timer counter a tca: timera 0 0 1 0 r 2 0 r 3 0 4 5 6 7 r r tca3 0 r tca4 0 r tca5 0 r tca6 0 r tca7 tca2 tca1 tca0 bit : initial value : r/w : h'ffbc: watchdog timer control/status register wtcsr: wdt 7 ovf 0 r/(w) * 6 wt/it 0 r/w 5 tme 0 r/w 4 ? 0 ? 3 rst/nmi 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w note: * only 0 can be written to clear the flag. note: * when ovf is polled and the interval timer interrupt is disabled, ovf=1 must be read at least twice. overflow flag wtcnt is initialized to h'00 and halted (initial value) wtcnt counts 0 1 nmi interrupt request is generated (initial value) internal reset request is generated 0 1 timer mode select bit timer enable bit reset or nmi interval timer mode: sends the cpu an interval timer interrupt request (wovi) when wtcnt overflows (initial value) watchdog timer mode: sends the cpu a reset or nmi interrupt request when wtcnt overflows 0 1 [clearing conditions] (1) write 0 in the tme bit (initial value) (2) read wtcsr when ovf = 1 * , then write 0 in ovf [setting condition] when wtcnt overflows (changes from h'ff to h'00) (when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset.) 0 1 bit : initial value : r/w : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1126 of 1174 rej09b0329-0200 h'ffbd: watchdog timer counter wtcnt: wdt 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit : initial value : r/w : h'ffc0: port data register 0 pdr0: i/o port 0 1 r 2 r 3 4 r r 5 7 pdr04 pdr03 pdr02 pdr01 pdr00 r pdr07 r r r pdr06 pdr05 6 bit : initial value : r/w : ???????? h'ffc1: port data register 1 pdr1: i/o port 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 0 r/w r/w r/w r/w 6 pdr14 pdr13 pdr12 pdr11 pdr10 pdr17 pdr16 pdr15 bit : initial value : r/w : h'ffc2: port data register 2 pdr2: i/o port 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 0 r/w r/w r/w r/w 6 pdr24 pdr23 pdr22 pdr21 pdr20 pdr27 pdr26 pdr25 bit : initial value : r/w : h'ffc3: port data register 3 pdr3: i/o port 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 0 r/w r/w r/w r/w 6 pdr34 pdr33 pdr32 pdr31 pdr30 pdr37 pdr36 pdr35 bit : initial value : r/w : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1127 of 1174 rej09b0329-0200 h'ffc4: port data register 4 pdr4: i/o port 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 0 r/w r/w r/w r/w 6 pdr44 pdr43 pdr42 pdr41 pdr40 pdr47 pdr46 pdr45 bit : initial value : r/w : h'ffc6: port data register 6 pdr6: i/o port 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 6 0 7 pdr64 pdr63 pdr62 pdr61 pdr60 0 r/w pdr67 r/w r/w r/w pdr66 pdr65 bit : initial value : r/w : h'ffc7: port data register 7 pdr7: i/o port 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 6 0 7 pdr74 pdr73 pdr72 pdr71 pdr70 0 r/w pdr77 r/w r/w r/w pdr76 pdr75 bit : initial value : r/w : h'ffc8: port data register 8 pdr8: i/o port 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 6 0 7 pdr84 pdr83 pdr82 pdr81 pdr80 0 r/w pdr87 r/w r/w r/w pdr86 pdr85 bit : initial value : r/w : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1128 of 1174 rej09b0329-0200 h'ffcd: port mode register 0 pmr0: i/o port 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 0 r/w r/w r/w r/w 6 pmr04 pmr03 pmr02 pmr01 pmr00 pmr07 pmr06 pmr05 p07/an7 to p00/an0 pin switching p0n/ann pin functions as p0n input port (initial value) p0n/ann pin functions as ann input port 0 1 note: n = 7 to 0 bit : initial value : r/w : h'ffce: port mode register 1 pmr1: i/o port 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 0 r/w r/w r/w r/w 6 pmr14 pmr13 pmr12 pmr11 pmr10 pmr17 pmr16 pmr15 p17/tmow pin functions as p17 i/o port (initial value) p17/tmow pin functions as tmow output port 0 1 p17/tmow pin function select bit p1n/irqn pin functions as p1n i/o port (initial value) p1n/irqn pin functions as irqn input port 0 1 p15/irq5 to p10/irq0 pin function select bits note: n = 5 to 0 p16/ic pin functions as p16 i/o port (initial value) p16/ic pin functions as ic input port 0 1 p16/ic pin function select bit bit : initial value : r/w : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1129 of 1174 rej09b0329-0200 h'ffd0: port mode register 3 pmr3: i/o port 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 0 r/w r/w r/w r/w 6 pmr34 pmr33 pmr32 pmr31 pmr30 pmr37 pmr36 pmr35 p3n/pwmm pin functions as p3n i/o port (initial value) p3n/pwmm pin functions as pwmm output port 0 1 p36/buzz pin functions as p36 i/o port (initial value) p36/buzz pin functions as buzz output port 0 1 p37/tmo pin functions as p37 i/o port (initial value) p37/tmo pin functions as tmo output port 0 1 p37/tmo pin function select bit notes: if the tmo pin is used for remote control sending, a careless timer output pulse may be output when the remote control mode is set after the output has been switched to the tmo output. perform the switching and setting in the following order. [1] set the remote control mode. [2] set the tmj-1 and 2 counter data of the timer j. [3] switch the p37/tmo pin to the tmo output pin. [4] set the st bit to 1. p36/buzz pin function select bit p35/pwm3 to p32/pwm0 pin function select bit p31/sv2 pin functions as p31 i/o port (initial value) p31/sv2 pin functions as sv2 output port 0 1 p31/sv2 pin function select bit notes: the h8s/2197s and h8s/2196s do not have pwm3 and pwm2 pin functions. n = 5 to 2, m = 3 to 0 p30/sv1 pin functions as p30 i/o port (initial value) p30/sv1 pin functions as sv1 output port 0 1 p30/sv1 pin function select bit bit : initial value : r/w : h'ffd1: port control register 1 pcr1: i/o port 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 0 7 0 w w w w 6 pcr14 pcr13 pcr12 pcr11 pcr10 pcr17 pcr16 pcr15 p1n pin functions as input port (initial value) p1n pin functions as output port 0 1 note: n = 7 to 0 bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1130 of 1174 rej09b0329-0200 h'ffd2: port control register 2 pcr2: i/o port 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 0 7 0 w w w w 6 pcr24 pcr23 pcr22 pcr21 pcr20 pcr27 pcr26 pcr25 p2n pin functions as input port (initial value) p2n pin functions as output port 0 1 note: n = 7 to 0 bit initial value r/w : : : h'ffd3: port control register 3 pcr3: i/o port 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 0 7 0 w w w w 6 pcr34 pcr33 pcr32 pcr31 pcr30 pcr37 pcr36 pcr35 p3n pin functions as input port (initial value) p3n pin functions as output port 0 1 bit initial value r/w : : : note: n = 7 to 0 appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1131 of 1174 rej09b0329-0200 h'ffd4: port control register 4 pcr4: i/o port 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 0 7 0 w w w w 6 pcr44 pcr43 pcr42 pcr41 pcr40 pcr47 pcr46 pcr45 p4n pin functions as input port (initial value) p4n pin functions as output port 0 1 bit initial value r/w : : : note: n = 7 to 0 h'ffd6: port control register 6 pcr6: i/o port 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 pcr64 pcr63 pcr62 pcr61 pcr60 0 w pcr67 w w w pcr66 pcr65 0 0 p6n/rpn pin functions as p6n general purpose input port (initial value) pcr6n pmr6n 1 p6n/rpn pin functions as p6n general purpose output port * 1 p6n/rpn pin functions as rpn realtime output port description legend: * don't care. note: n = 7 to 0 bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1132 of 1174 rej09b0329-0200 h'ffd7: port control register 7 pcr7: i/o port 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 pcr74 pcr73 pcr72 pcr71 pcr70 0 w pcr77 w w w pcr76 pcr75 p7n pin functions as input port (initial value) p7n pin functions as output port 0 1 bit initial value r/w : : : note: n = 7 to 0 h'ffd8: port control register 8 pcr8: i/o port 0 0 1 0 w 2 0 w 3 0 4 0 w 0 w 5 6 0 7 pcr84 pcr83 pcr82 pcr81 pcr80 0 w pcr87 w w w pcr86 pcr85 p8n pin functions as input port (initial value) p8n pin functions as output port 0 1 bit initial value r/w : : : note: n = 7 to 0 h'ffd9: port mode register a pmra: i/o port 0 1 1 1 ? 2 1 ? 3 1 4 1 ? 1 ? 5 7 ????? 0 r/w pmra7 6 0 r/w pmra6 ? ? ? timer b event input edge switching 0 timer b event input falling edge is detected. (initial value) 1 timer b event input rising edge is detected. p67/rp7/tmbi pin switching 0 p67/rp7/tmbi pin functions as a p67/rp7 i/o pin. (initial value) 1 p67/rp7/tmbi pin functions as a tmbi output pin. : : : bit initial value r/w appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1133 of 1174 rej09b0329-0200 h'ffda: port mode register b pmrb: i/o port 0 1 1 1 ? 2 1 ? 3 1 4 0 r/w 0 r/w 5 7 pmrb4 ? ? ? ? 0 r/w pmrb7 6 0 r/w pmrb6 ? ? pmrb5 p77/rpb to p74/rpb pin switching 0 p7n/rpm pin functions as a p7n i/o pin. (initial value) 1 p7n/rpm pin functions as a rpm output pin. : : : bit initial value r/w note: n = 7 to 4, m = b, a, 9, 8 appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1134 of 1174 rej09b0329-0200 h'ffdb: port mode register 4: pmr4: i/o port 0 0 1 1 2 1 3 1 4 1 1 5 1 7 1 r/w 6 pmr40 p40/pwm14 pin functions as p40 i/o port (initial value) p40/pwm14 pin functions as pwm14 output port 0 1 p40/pwm14 pin function select bit note: the h8s/2197s and h8s/2196s do not have pwm14 pin function. p47/rptrg pin functions as p47 i/o port (initial value) p47/rptrg pin functions as rptrg i/o pin 0 1 p47/rptrg pin function select bit pmr47 ? ? ? ? ? ? r/w???? ?? bit initial value r/w : : : h'ffdd: port mode register 6 pmr6: i/o port 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 6 0 7 pmr64 pmr63 pmr62 pmr61 pmr60 0 r/w pmr67 r/w r/w r/w pmr66 pmr65 p6n/rpn pin functions as p6n i/o port (initial value) p6n/rpn pin functions as rpn output port 0 1 p67/rp7 to p60/rp0 pin function select bit note: n = 7 to 0 bit initial value r/w : : : h'ffde: port mode register 7 pmr7: i/o port 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 6 0 7 pmr74 pmr73 pmr72 pmr71 pmr70 0 r/w pmr77 r/w r/w r/w pmr76 pmr75 p77/ppg7 to p70/ppg0 pin function select bit p7n/ppgn pin functions as p7n i/o port (initial value) p7n/ppgn pin functions as ppgn output port 0 1 bit initial value r/w : : : note: n = 7 to 0 appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1135 of 1174 rej09b0329-0200 h'ffdf: port mode register 8 pmr8: i/o port 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 7 pmr84 pmr83 pmr82 pmr81 pmr80 0 r/w pmr87 6 0 r/w pmr86 r/w r/w pmr85 p81/excap pin function select bit 0 p81/excap pin functions as p81 i/o pin (initial value) 1 p81/excap pin functions as excap input pin p80/yco pin function select bit 0 p80/yco pin functions as p80 i/o pin (initial value) 1 p80/yco pin functions as yco input pin p83/c.rotary pin function select bit 0 p83/c.rotary pin functions as p83 i/o pin (initial value) 1 p83/c.rotary pin functions as c.rotary output pin p82/exctl pin function select bit 0 p82/exctl pin functions as p82 i/o pin (initial value) 1 p82/exctl pin functions as exctl input pin p84/h.amp.sw pin function select bit 0 p84/h.amp sw pin functions as p84 i/o pin (initial value) 1 p84/h.amp sw pin functions as h.amp sw output pin p85/comp pin function select bit 0 p85/comp pin functions as p85 i/o pin (initial value) 1 p85/comp pin functions as comp input pin p86/exttrg pin function select bit 0 p86/exttrg pin functions as p86 i/o pin (initial value) 1 p86/exttrg pin functions as exttrg input pin p87/dpg pin function select bit 0 p87/dpg pin functions as p87 i/o pin (initial value) (drum control signals are input as an overlapped signal) 1 p87/dpg pin functions as a dpg input pin (drum control signals are input as separate signal) : : : bit initial value r/w appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1136 of 1174 rej09b0329-0200 h'ffe0: port mode register c pmrc: i/o port 0 1 1 0 r/w 2 1 ? 3 0 4 0 r/w 0 r/w 5 6 7 pmrc4 pmrc3 ? pmrc1 ? 1 ? 1 ? ?? ? r/w pmrc5 p81/ybo pin function select bit 0 p81/ybo pin functions as p81 i/o port (initial value) 1 p81/ybo pin functions as ybo output pin p83/r pin function select bit 0 p83/r pin functions as p83 i/o port (initial value) 1 p83/r pin functions as r output pin p84/b pin function select bit 0 p84/g pin functions as p84 i/o port (initial value) 1 p84/g pin functions as g output pin p85/b pin function select bit 0 p85/b pin functions as p85 i/o port (initial value) 1 p85/b pin functions as b output pin : : : bit initial value r/w h'ffe1: pull-up mos select register 1 pur1: i/o port 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 0 r/w r/w r/w r/w 6 pur14 pur13 pur12 pur11 pur10 pur17 pur16 pur15 p1n pin has no pull-up mos transistor (initial value) p1n pin has pull-up mos transistor 0 1 bit : initial value : r/w : note: n = 7 to 0 appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1137 of 1174 rej09b0329-0200 h'ffe2: pull-up mos select register 2 pur2: i/o port 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 0 r/w r/w r/w r/w 6 pur24 pur23 pur22 pur21 pur20 pur27 pur26 pur25 p2n pin has no pull-up mos transistor (initial value) p2n pin has pull-up mos transistor 0 1 bit initial value r/w : : : note: n = 7 to 0 h'ffe3: pull-up mos select register 3 pur3: i/o port 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 0 r/w r/w r/w r/w 6 pur34 pur33 pur32 pur31 pur30 pur37 pur36 pur35 p3n pin has no pull-up mos transistor (initial value) p3n pin has pull-up mos transistor 0 1 bit initial value r/w : : : note: n = 7 to 0 h'ffe4: realtime output trigger edge select register rtpegr: i/o port 0 0 1 0 r/w 2 1 3 1 4 1 1 5 6 1 7 rtpegr1 rtpegr0 1 r/w 0 0 trigger input is disabled (initial value) rtpegr0 rtpegr1 1 rising edge of trigger input is selected 0 1 rising and falling edges of trigger input is selected 1 falling edge of trigger input is selected realtime output trigger edge select bit description ?????? ?????? bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1138 of 1174 rej09b0329-0200 h'ffe5: realtime output trigger se lect register 1 rtpsr1: i/o port 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 6 0 7 rtpsr14 rtpsr13 rtpsr12 rtpsr11 rtpsr10 0 r/w rtpsr17 r/w r/w r/w rtpsr16 rtpsr15 external trigger (rptrg pin) input is selected (initial value) internal triggfer (hsw) input is selected 0 1 bit initial value r/w : : : note: n = 7 to 0 h'ffe6: realtime output trigger se lect register 2 rtpsr2: i/o port 0 1 1 1 ? 2 1 ? 3 1 4 0 r/w 0 r/w 5 7 rtpsr24 ? ? ? ? 0 r/w rtpsr27 6 0 r/w rtpsr26 ? ? rtpsr25 : : : external trigger rptrg input is selected (initial value) internal trigger hsw input is selected 0 1 bit initial value r/w appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1139 of 1174 rej09b0329-0200 h'ffe8: system control register syscr: system control 0 1 1 0 2 0 3 1 4 0 r/w 5 0 6 0 7 r r intm1 intm0 xrst ?? 0 0 0 0 interrupt is controlled by i bit intm0 intm1 interrupt control mode interrupt control 1 1 interrupt is controlled by i and ui bits and icr 0 1 2 cannot be used in the h8s/2199 group 1 3 cannot be used in the h8s/2199 group reset is generated by watchdog timer overflow reset is generaed by external reset input 0 1 interrupt control mode external reset ?? ? ?? ? ? ? bit initial value r/w : : : h'ffe9: mode control register mdcr: system control 0 ? * 1 0 2 0 3 0 4 0 5 0 6 0 7 r mds0 0 note: * determined by md0 pin. mode select 0 ????? ?? ????? ?? bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1140 of 1174 rej09b0329-0200 h'ffea: standby control regi ster sbycr: system control 0 0 1 0 r/w 2 0 3 0 4 0 r/w 5 0 6 0 7 r/w r/w sts1 r/w sts2 0 r/w ssby sts0 sck1 sck0 transition to sleep mode after execution of sleep instruction in high-speed mode or medium-speed mode transition to subsleep mode after execution of sleep instruction in subactive mode transition to stadby mode, subactive mode, or watch mode after execution of sleep instruction in high-speed mode or medium- speed mode transition to watch mode or high-speed mode after execution of sleep instruction in subactive mode 0 1 software standby system clock select system clock select 0 0 sck0 sck1 1 0 1 bus master is in high-speed mode medium-speed clock is /16 medium-speed clock is /32 1 medium-speed clock is /64 0 0 sts1 sts2 1 standby timer select bits 0 sts0 1 0 standby time 8192 states 16384 states 32768 states 0 1 1 0 1 65536 states 1 * reserved 131072 states 262144 states legend: * don't care. ? ? ? ? bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1141 of 1174 rej09b0329-0200 h'ffeb: low-power control regi ster lpwrcr: system control 0 0 1 0 r/w 2 0 3 0 4 0 5 0 6 0 7 r/w r/w nesel r/w lson 0 r/w dton sa1 sa0 low-speed on flag noise elimination sampling frequency select subactive mode clock select subactive mode clock select sampling at divided by 16 sampling at divided by 4 0 1 ? when a sleep instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, standby mode, or watch mode ? when a sleep instruction is executed in subactive mode, a transition is made to watch mode, or directly to high-speed mode ? when a sleep instruction is executed in high-speed mode or medium-speed mode, a transition is made directly to subactive mode, or a transition is made to sleep mode or standby mode ? when a sleep instruction is executed in subactive mode, a transition is made directily to high-speed mode, or a transition is made to subsleep mode 0 1 direct transfer on flag ? when a sleep instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, standby mode, or watch mode ? when a sleep instruction is executed in subactive mode, a transition is made to watch mode, or directly to high-speed mode ? after watch mode is cleared, a transition is made to high-speed mode ? when a sleep instruction is executed in high-speed mode a transition is made to watch mode, subactive mode, sleep mode or standby mode. ? when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode. ? after watch mode is cleared, a transition is made to subactive mode 0 1 legend: * don't care. 0 0 sa0 sa1 1 0 * 1 operating clock of cpu is w/8 operating clock of cpu is w/4 operating clock of cpu is w/2 ??? ??? bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1142 of 1174 rej09b0329-0200 h'ffec: module stop control register mstpcrh: system control h'ffed: module stop control regist er mstpcrl: system control 7 1 mstp15 r/w mstpcrh 6 1 mstp14 r/w 5 1 mstp13 r/w 4 1 mstp12 r/w 3 1 mstp11 r/w 2 1 mstp10 r/w 1 1 mstp9 r/w 0 1 mstp8 r/w 7 1 mstp7 r/w 6 1 mstp6 r/w 5 1 mstp5 r/w 4 1 mstp4 r/w 3 1 mstp3 r/w 2 1 mstp2 r/w 1 1 mstp1 r/w 0 1 mstp0 r/w mstpcrl module stop module stop mode is released module stop mode is set (initial value) 0 1 bit initial value r/w : : : h'ffee: serial timer control re gister stcr: system control 7 ? 0 ? 6 iicx1 0 r/w 5 iicx0 0 r/w 4 ? 0 ? 3 flshe 0 r/w 2 osrome 0 r/w 1 ? 0 ? 0 ? 0 ? flash memory control register enable bit osd rom enable i 2 c control used combined with cks2 to cks0 in icmr0 * note: * refer to section 23.2.4, i 2 c bus mode register (icmr) osd rom is accessed by osd (initial value) osd rom is accessed by cpu 0 1 flash memory control register is not selected (initial value) flash memory control register is selected 0 1 bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1143 of 1174 rej09b0329-0200 h'fff0: irq edge select register iegr: interrupt controller 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 5 0 0 7 r/w r/w r/w irq4eg r/w irq5eg irq3eg irq2eg irq1eg irq0eg1 irq0eg2 0 6 irq0 pin detected dege select bits description 0 0 interrupt request generaed at falling edge of irq0 pin input (initial value) irq0eg0 irq0eg1 1 0 interrupt request generaed at rising edge of irq0 pin input * 1 interrupt request generaed at bath falling and rising edge of irq0 pin input legend: * don't care. irq5 to irq1 pins detected edge select bits interrupt request generated at falling edge of irqn pin input (initial value) interrupt request generated at rising edge of irqn pin input 0 1 note: n = 5 to 1 : bit initial value : ? ? r/w : h'fff1: irq enable register ienr: interrupt controller 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 5 0 0 7 r/w r/w r/w irq5e irq4e irq3e irq2e irq1e irq0e 0 6 irq5 to irq0 enable bits irqn interrupt is disabled (initial value) irqn interrupt is enabled 0 1 note: n = 5 to 0 ?? ?? bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1144 of 1174 rej09b0329-0200 h'fff2: irq status register irqr: interrupt controller 0 0 1 0 r/(w) * 2 0 r/(w) * 3 0 4 0 r/(w) * 5 0 0 7 r/(w) * r/(w) * r/(w) * irq5f irq4f irq3f irq2f irq1f irq0f 0 6 note: * only 0 can be written to clear the flag. irq5 to irq0 flag [clearing conditions] (1) cleared by reading irqnf set to 1, then writing 0 in irqnf (2) when irqn interrupt exception handling is executed [setting conditions] (1) when a falling edge occurs in irqn input while falling edge detection is set (irqneg = 0) (2) when a rising edge occurs in irqn input while rising edge detection is set (irqneg = 0) (3) when a falling or rising edge occurs in irq0 input while both-edge detection is set (irq0eg1 = 1) 0 1 ?? ?? bit initial value r/w : : : (initial value) note: n = 5 to 0 h'fff3: interrupt control register a icra: interrupt controller h'fff4: interrupt control register b icrb: interrupt controller h'fff5: interrupt control register c icrc: interrupt controller h'fff6: interrupt control register d icrd: interrupt controller 0 0 1 0 r/w 2 0 r/w 3 0 4 0 r/w 0 r/w 5 0 7 icr4 icr3 icr2 icr1 icr0 0 r/w icr7 r/w r/w r/w icr6 icr5 6 interrupt control level corresponding interrupt source is control level 0 (non-priority) (initial value) corresponding interrupt source is control level 1 (priority) 0 1 note: n = 7 to 0 bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1145 of 1174 rej09b0329-0200 h'fff8: flash memory control register 1 flmcr1: flash rom 7 fwe ? * r 6 swe1 0 r/w 5 esu1 0 r/w 4 psu1 0 r/w 3 ev1 0 r/w 0 p1 0 r/w 2 pv1 0 r/w 1 e1 0 r/w note: * determined by the state of the fwe pin. program 1 software write enable 1 writes are disabled (initial value) writes are enabled [setting condition] when fwe = 1 0 1 flash write enable when a low level is input to the fwe pin (hardware-protected state) when a high level is input to the fwe pin 0 1 erase-verify 1 erase-verify mode cleared (initial value) transition to erase-verify mode [setting condition] when fwe = 1 and swe1 = 1 0 1 program-verify 1 program-verify mode cleared (initial value) transition to program-verufy mode [setting condition] when fwe = 1 and swe1 = 1 0 1 program set-up 1 program set-up cleared (initial value) transition to program set-up status [setting condition] when fwe = 1 and swe1 = 1 0 1 erase set-up 1 erase set-up cleared (initial value) transition to erase set-up status [setting condition] when fwe = 1 and swe1 = 1 0 1 erase 1 erase mode cleared (initial value) transition to erase mode [setting condition] when fwe = 1, swe1 = 1, and esu1 = 1 0 1 program mode cleared (initial value) transition to program mode [setting condition] when fwe = 1, swe1 = 1, and psu1 = 1 0 1 bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1146 of 1174 rej09b0329-0200 h'fff9: flash memory control register 2 flmcr2: flash rom flash memory error flash memory is operating normally flash memory program/erase protection (error protection) is disabled [clearing condition] reset (initial value) an error has occurred during flash memeory programming/erasing flash memory program/erase protection (error protection) is enabled [setting condition] see section 7.6.3, error protection 0 1 7 fler 0 r 6 swe2 0 r/w 5 esu2 0 r/w 4 psu2 0 r/w 3 ev2 0 r/w 0 p2 0 r/w 2 pv2 0 r/w 1 e2 0 r/w program 2 software write enable 2 writes are disabled (initial value) writes are enabled [setting condition] when fwe = 1 0 1 erase-verify 2 erase-verify mode cleared (initial value) transition to erase-verify mode [setting condition] when fwe = 1 and swe2 = 1 0 1 program-verify 2 program-verify mode cleared (initial value) transition to program-verufy mode [setting condition] when fwe = 1 and swe2 = 1 0 1 program set-up 2 program set-up cleared (initial value) transition to program set-up status [setting condition] when fwe = 1 and swe2 = 1 0 1 erase set-up 2 erase set-up cleared (initial value) transition to erase set-up status [setting condition] when fwe = 1 and swe2 = 1 0 1 erase 2 erase mode cleared (initial value) transition to erase mode [setting condition] when fwe = 1, swe2 = 1, and esu2 = 1 0 1 program mode cleared (initial value) transition to program mode [setting condition] when fwe = 1, swe2 = 1, and psu2 = 1 0 1 bit initial value r/w : : : appendix b internal i/o registers rev.2.00 jan. 15, 2007 page 1147 of 1174 rej09b0329-0200 h'fffa: erase block select register 1 ebr1: flash rom 7 eb7 0 r/w 6 eb6 0 r/w 5 eb5 0 r/w 4 eb4 0 r/w 3 eb3 0 r/w 0 eb0 0 r/w 2 eb2 0 r/w 1 eb1 0 r/w bit : initial value : r/w : h'fffb: erase block select register 2 ebr2: flash rom 7 eb15 0 r/w 6 eb14 0 r/w 5 eb13 0 r/w 4 eb12 0 r/w 3 eb11 0 r/w 0 eb8 0 r/w 2 eb10 0 r/w 1 eb9 0 r/w bit initial value r/w : : : appendix c pin circuit diagrams rev.2.00 jan. 15, 2007 page 1148 of 1174 rej09b0329-0200 appendix c pin circuit diagrams c.1 pin circuit diagrams circuit diagrams for all pins except power supply pins are shown in table c.1. legend out g in out g in pmos nmos clocked g ate si g nal transmitted when g = 1 si g nal transmitted when g = 0 table c.1 pin circuit diagrams pin states pin names circuit diagram at reset sleep mode power-down modes other than sleep mode p00/an0 to p07/an7 pmr0n rd sch3 to sch0 hi-z retained hi-z an8 to anb hch1, hch0 hi-z retained hi-z appendix c pin circuit diagrams rev.2.00 jan. 15, 2007 page 1149 of 1174 rej09b0329-0200 pin states pin names circuit diagram at reset sleep mode power-down modes other than sleep mode retained pull-up mos: off subactive mode: functions other modes: hi-z p10/ irq0 to p15/ irq5 p16/ ic pur1n pcr1n rd pdr1n pmr1n pcr1n int int = irq0 to irq5 , i c note: n = 0 to 6 pmr1n hi-z when irq0 to irq5 and ic are selected, pin input should be fixed high or low. p17/tmow pur17 pcr17 tmow pdr17 pmr17 pcr17 rd hi-z retained pull-up mos: off subactive mode: functions other modes: hi-z retained pull-up mos: off subactive mode: functions other modes: hi-z p20/si1 pur20 pcr20 rd pdr20 rxe pcr20 si1 rxe le g end: rxe: input control si g nal determined by scr and smr hi-z when si1 is selected, pin input should be fixed high or low. appendix c pin circuit diagrams rev.2.00 jan. 15, 2007 page 1150 of 1174 rej09b0329-0200 pin states pin names circuit diagram at reset sleep mode power-down modes other than sleep mode p21/so1 pur21 pcr21 so1 pdr21 txe pcr21 rd le g end: txe: output control si g nal determined by scr and smr hi-z retained pull-up mos: off subactive mode: functions other modes: hi-z retained pull-up mos: off subactive mode: functions other modes: hi-z p22/sck1 pur22 pcr22 scko scki pdr22 ckoe pcr22 rd ckie le g end: scko: transfer clock output scki: transfer clock input ckoe: transfer clock output control si g nal determined by smr and scr ckie: transfer clock input control si g nal determined by smr and scr hi-z when sck1 is selected, pin input should be fixed high or low. appendix c pin circuit diagrams rev.2.00 jan. 15, 2007 page 1151 of 1174 rej09b0329-0200 pin states pin names circuit diagram at reset sleep mode power-down modes other than sleep mode hi-z retained pull-up mos: off subactive mode: functions other modes: hi-z p23/sda1 p24/scl1 p25/sda0 p26/scl0 pur2n pcr2 n sda/scl pdr2n iice pcr2n rd iice sda/scl le g end: iice = i 2 c bus enable si g nal note: n = 3 to 6 as sda and scl always function, a high level or a low level should always be input to the pins. hi-z retained pull-up mos: off subactive mode: functions other modes: hi-z p27/synci pur27 pcr27 pdr27 rd pcr27 synci as synci always functions, a high level or a low level should always be input to the pin. appendix c pin circuit diagrams rev.2.00 jan. 15, 2007 page 1152 of 1174 rej09b0329-0200 pin states pin names circuit diagram at reset sleep mode power-down modes other than sleep mode p30/svi p31/sv2 p32/pwm0 p33/pwm1 p34/pwm2 p35/pwm3 p36/buzz p37/tmo pur3n pcr3n out pdr3n pmr3n pcr3n rd le g end: out: p30/sv1: servo monitor output p31/sv2: servo monitor output p32/pwm0: 8-bit pwm0 output p33/pwm1: 8-bit pwm1 output p34/pwm2: 8-bit pwm2 output p35/pwm3: 8-bit pwm3 output p36/buzz: timer j buzzer output p37/tmo: timer j timer output note: n = 1 to 7 hi-z retained pull-up mos: off subactive mode: functions other modes: hi-z p40/pwm14 out pdr40 pmr40 pcr40 out pwm14 rd hi-z retained subactive mode: functions other modes: hi-z appendix c pin circuit diagrams rev.2.00 jan. 15, 2007 page 1153 of 1174 rej09b0329-0200 pin states pin names circuit diagram at reset sleep mode power-down modes other than sleep mode hi-z retained subactive mode: functions other modes: hi-z p41/ftia p42/ptib p43/ftic p44/ftid rd pdr4n pcr4n le g end: in = ftia, ftib, ftic, ftid note: n = 1 to 4 in as ftia to ftid always function, a high level or a low level should always be input to the pins. p45/ftoa p46/ptob out pdr4n toe pcr4n rd le g end: out: p45/ftoa: timer x1 output compare output ftoa p46/ftob: timer x1 output compare output ftob toe: output control si g nal determined by tocr note: n = 5, 6 hi-z retained subactive mode: functions other modes: hi-z appendix c pin circuit diagrams rev.2.00 jan. 15, 2007 page 1154 of 1174 rej09b0329-0200 pin states pin names circuit diagram at reset sleep mode power-down modes other than sleep mode hi-z retained subactive mode: functions other modes: hi-z p47/rptrg rd pdr47 pmr47 pcr47 rptrg pmr47 when rptrg is selected, pin input should be fixed high or low. p60/rp0 to p65/rp5 rd note: n = 0 to 5 pdrs6n pcrs6n pmr6n hi-z retained subactive mode: functions other modes: hi-z hi-z retained subactive mode: functions other modes: hi-z p66/rp6/ adtrg rd trge legend: trge: a/d trigger input control signal pdrs66 pcrs66 pmr66 adtrg when adtrg is selected, pin input should be fixed high or low. appendix c pin circuit diagrams rev.2.00 jan. 15, 2007 page 1155 of 1174 rej09b0329-0200 pin states pin names circuit diagram at reset sleep mode power-down modes other than sleep mode hi-z retained subactive mode: functions other modes: hi-z p67/rp7/ tmbi rd pmra7 pdrs67 pmra7 pcrs67 pmr67 tmbi when tmbi is selected, pin input should be fixed high or low. p70/ppg0 to p73/ppg3 ppgn pdr7n pmr7n pcr7n rd note: n = 0 to 3 hi-z retained subactive mode: functions other modes: hi-z p74/ppg4/ rp8 to p77/ ppg7/rp8 ppgn pdrs7n pmrbn pmr7n pcrs7n rd note: n = 4 to 7 hi-z retained subactive mode: functions other modes: hi-z appendix c pin circuit diagrams rev.2.00 jan. 15, 2007 page 1156 of 1174 rej09b0329-0200 pin states pin names circuit diagram at reset sleep mode power-down modes other than sleep mode p80/yco yco pdr80 pmr80 pcr80 rd hi-z retained subactive mode: functions other modes: hi-z p83/ c.rotary/r p84/h.amp sw/g out1 legend: out1: out2: note: n = 3, 4 c.rotary, h.amp sw r, g out2 pdr8n pmrcn pmr8n pcr8n rd hi-z retained subactive mode: functions other modes: hi-z hi-z retained subactive mode: functions other modes: hi-z p82/exctl p86/ exttrg pmr8n legend: in = exctl, exttrg note: n = 2, 6 rd pdr8n pmr8n pcr8n in when exctl and exttrg are selected, pin input should be fixed high or low. appendix c pin circuit diagrams rev.2.00 jan. 15, 2007 page 1157 of 1174 rej09b0329-0200 pin states pin names circuit diagram at reset sleep mode power-down modes other than sleep mode hi-z retained subactive mode: functions other modes: hi-z p81/excap/ ybo p85/comp/ b out pdr8n pmrcn pmr8n pcr8n in rd pmr8n note: n = 1, 5 in = excap, comp out = ybo, b when excap comp is selected, pin input should be fixed high or low. p87/dpg rd pdr87 pcr87 dpg hi-z retained subactive mode: functions other modes: hi-z csync module stop pin input should be fixed high or low. audioff videoff out lpm hi-z hi-z hi-z cappwm drmpwm low output low output low output vpulse lpm 3-level controller 15k typ note: resistance values are reference values. 15k typ low output low output low output appendix c pin circuit diagrams rev.2.00 jan. 15, 2007 page 1158 of 1174 rej09b0329-0200 pin states pin names circuit diagram at reset sleep mode power-down modes other than sleep mode res rst low input (high) (high) md0 fwe ? cfg + - + - + - cfgcomp cfgcomp p250 ref m250 s r f/f o stp vref vref cfg bias res+modulestop ? ? ? dfg dpg rd pcrn pdrn dfg dpg pmrn pcrn dpg sw dpg sw pes+lpm dfg dpg hi-z ? hi-z ctl (+) ctl ( ? ) ctlref ctlbias ctlfb ctlamp (o) ctlsmt (i) + - - + + - ctlgr3 to 1 ctlfb ctlgr0 ampshort (rec-ctl) ampon (pb-ctl) pb-ctl (+) pb-ctl (e) ctlsmt (i) ctlref ctl (+) ctl (-) ctlbias ctlfb ctlamp(o) * note: * connect a capacitor between ctlamp (o), ctlsmt (i) ? ? ? appendix c pin circuit diagrams rev.2.00 jan. 15, 2007 page 1159 of 1174 rej09b0329-0200 pin states pin names circuit diagram at reset sleep mode power-down modes other than sleep mode x2 x1 10m typ note: the resistance value is a reference value. when the subclock is not used, connect x1 to vcl and leave x2 open. oscil- lation oscil- lation oscillation osc2 low output osc1 lpm oscil- lation oscil- lation ? cvin1 sync tip (1.4 v) lpm + ? + ? hi-z hi-z hi-z cvout + ? lpm hi-z hi-z hi-z appendix c pin circuit diagrams rev.2.00 jan. 15, 2007 page 1160 of 1174 rej09b0329-0200 pin states pin names circuit diagram at reset sleep mode power-down modes other than sleep mode 4/2fsc in oscilla- tion oscilla- tion ? 4/2fsc out lpm 4/2fsc in (external input) 4/2fsc in external clock select low output (oscillation stopped) vlpf/csync pin input should be fixed high or low csync/ hsync hi-z hi-z hi-z cvin2 + ? + ? + ? + ? + ? + ? polarity switch signal selection polarity switch i/o switch sync tip (2.0 v) signal selection vsync hsync vsel synct lpm l p m ccmpsl ccmpsl eds lpm hi-z hi-z hi-z appendix c pin circuit diagrams rev.2.00 jan. 15, 2007 page 1161 of 1174 rej09b0329-0200 pin states pin names circuit diagram at reset sleep mode power-down modes other than sleep mode afcosc oscilla- tion oscilla- tion hi-z oscillation stopped afcpc 1/2 ov cc 1/2 ov cc ? afclpf 1/2 ov cc lpm up + down lpm lpm ? phase gain control retained retained ? legend: rd: read signal rst: reset signal lpm: power-down mode signal (1 in standby, watch, subactive, and subsleep modes) hi-z: high impedance sleep: sleep mode signal note: numbers given for resistance values, etc., are reference values. appendix d port states in each processing state rev.2.00 jan. 15, 2007 page 1162 of 1174 rej09b0329-200 appendix d port states in each processing state d.1 pin circuit diagrams table d.1 port states overview port reset active sleep standby watch subactive subsleep p07 to p00 high imped- ance high imped- ance high imped- ance high imped- ance high imped- ance high impedance high impedance p17 to p10 high imped- ance functions retained high imped- ance high imped- ance functions retained p27 to p20 high imped- ance functions retained high imped- ance high imped- ance functions retained p37 to p30 high imped- ance functions retained high imped- ance high imped- ance functions retained p47 to p40 high imped- ance functions retained high imped- ance high imped- ance functions retained p67 to p60 high imped- ance functions retained high imped- ance high imped- ance functions retained p77 to p70 high imped- ance functions retained high imped- ance high imped- ance functions retained p87 to p80 high imped- ance functions retained high imped- ance high imped- ance functions retained appendix e usage notes rev.2.00 jan. 15, 2007 page 1163 of 1174 rej09b0329-0200 appendix e usage notes e.1 power supply rise and fall order figure e.1 shows the order in which the power supply pins rise when the chip is powered on, and the order in which they fall when the chip is powered down. if the power supply voltages cannot rise and fall simultaneously, power supply operatio ns should be carried out in this order. ? at power-on, wait until the microcomputer section power supply (v cc ) has risen to the prescribed voltage, then raise the other analog power supplies. ? at power-down, drop the analog power supplies first, followed by the microcomputer section power supply (v cc ). when powering up and down, the voltage applied to the pins should not exceed the respective power supply voltage. v cc , av cc le g end: v cc av cc sv cc ov cc vin : microcomputer section power supply volta g e : a/d converter power supply volta g e : servo section power supply volta g e : osd section power supply : pin applied volta g e sv cc ,ov cc v cc , av cc sv cc , ov cc vin vin figure e.1 power supply rise and fall order in power-down modes (except sleep mode), the analog power supplies can be controlled at the v ss level to reduce current dissipation. when the microcomputer section power supply (v cc ) is dropped to the backup voltage in a power-down mode, the order shown in figure e.2 should be followed. make sure that the voltage applied to the pins doe s not exceed the respective power supply voltage. the a/d converter power supply (av cc ) should be set to the same potential as the microcomputer section power supply (v cc ). in all power-down modes except sleep mode, av cc is turned off inside the device. at this time, the av cc current dissipation is defined as aistop. appendix e usage notes rev.2.00 jan. 15, 2007 page 1164 of 1174 rej09b0329-200 le g end: v cc av cc sv cc ov cc vin 5 v 2.7 v : microcomputer section power supply volta g e : a/d converter power supply volta g e : servo section power supply volta g e : osd section power supply : pin applied volta g e v cc , av cc sv cc , ov cc vin figure e.2 power supply control in power-down modes when the osd block power supply (ov cc ) is raised or dropped, the following order must be observed. when dropping ov cc , set the osd module stop bit, and sync separation module stop bit to 1 to stop each module before dropping ov cc . when raising ov cc , raise ov cc and wait until the fsc clock settle s before clearing the osd module stop bit, and sync separation module st op bit to 0 to operate each module. appendix e usage notes rev.2.00 jan. 15, 2007 page 1165 of 1174 rej09b0329-0200 settlin g wait time sync separation module stop bit and osd module stop bit 5 v fsc ov cc figure e.3 module stop bit setting order when raising and dropping ov cc end ovcc = off end ovcc = on yes no when droppin g ovcc when risin g ovcc fsc clock settin g osd module stop bit = 1 sync separation module stop bit = 1 osd module stop bit = 0 sync separation module stop bit = 0 figure e.4 timing chart of ovcc when rising or dropping appendix e usage notes rev.2.00 jan. 15, 2007 page 1166 of 1174 rej09b0329-200 e.2 sample external circuits examples of external circuits for the servo section, and sync signal detection circuit are shown in figures e.5and e.6 1. servo section an example of the external circuit for the drmpwm output and cappwm output pins is shown in figure e.5 r 1 drmpwm cappwn c 1 figure e.5 sample external circuit for servo section 2. sync signal detection circuit section in servo circuit figure e.6shows an example of the external circuit for the sync signal detection circuit section in the servo circuit. 33 k csync note: reference values are shown. the board floatin g capacitance and wirin g resistance must also be taken into consideration in determinin g the values. 10 pf figure e.6 example of external circuit fo r sync signal detect ion circuit section appendix e usage notes rev.2.00 jan. 15, 2007 page 1167 of 1174 rej09b0329-0200 3. osd an example of the extern al circuit for the osd is shown in figure e.7 the circuit configuration and values for the filter section will vary according to the wiring capacitance, impedance, etc. when designing the board, an appropriate filter should be configured, taking account of the wiring load. noise prevention measures also need to be taken when designing the board. clamp (=1.4 vtyp) note: reference values are shown. the board floating capacitance and wiring resistance must also be taken into consideration in determining the values. c.vin1 c.vout 4.7 f 470 f + 68 75 driver 1 k 2.7 k 470 k 120 5 pf figure e.7 example of ex ternal circuit for osd 4. sync separator and data slicer examples of the external circuits for the sync separator and data slicer are shown in figures e.8 to e.10. the sync signal separation sources can be selected from the following three: (1) cvin2, (2) csync, and (3) separate hsync and vsync signals. the external circuit configuration will vary depending on the separation source. when the data slicer is used, cvin2 is recommended as the separation source. when csync or hsync and vsync are selected as the source, co nnect to cvin2 the same external circuit as when cvin2 is selected as the separation source. appendix e usage notes rev.2.00 jan. 15, 2007 page 1168 of 1174 rej09b0329-200 4.7 f 4.7 f 8.2 h/15 h 1000 pf 0.01 f 680 pf 680 pf 12 pf/15 pf c.vin2 vlpf/vsync csync/hsync afcosc afcpc afclpf 300 470 k 10 k 470 10 k clamp 2 (=2.0 vtyp) note: reference values are shown. the board floating capacitance and wiring resistance must also be taken into consideration in determining the values. figure e.8 example of ext ernal circuit for sync se parator and da ta slicer ((1) separation from cvin2) appendix e usage notes rev.2.00 jan. 15, 2007 page 1169 of 1174 rej09b0329-0200 4.7 f 0.01 f 1000 pf 10 pf c.vin2 vlpf/vsync csync/hsync afcosc afcpc afclpf 10 k 10 k 33 k 10 k clamp 2 (=2.0 vtyp) 8.2 h/15 h 12 pf/15 pf 470 ov cc figure e.9 example of ext ernal circuit for sync se parator and da ta slicer ((2) separation from csync) appendix e usage notes rev.2.00 jan. 15, 2007 page 1170 of 1174 rej09b0329-200 4.7 f 4.7 f 1000 pf c.vin2 vlpf/vsync csync/hsync afclpf afcosc 10 k clamp 2 (=2.0 vtyp) 8.2 h/15 h 12 pf/15 pf 470 note: reference values are shown. the board floating capacitance and wiring resistance must also be taken into consideration in determining the values. 10 k ov cc figure e.10 example of ext ernal circuit for sync se parator and da ta slicer ((3) separation from hsync and vsync) appendix e usage notes rev.2.00 jan. 15, 2007 page 1171 of 1174 rej09b0329-0200 e.3 handling of pins when osd is not used table e.2 shows the handling of pins when the osd, sync separator, or data slicer is not used. when none of these modules is used, pin handling differs according to whether or not the anb pin is used. table e.2 handling of pins when osd is not used pin handling conditions when anb pin is used when anb pin is not used osd used not used not used not used not used data slicer not used used not used not used not used module used or not used sync separator used used used not used not used osdv cc v cc v cc v cc v cc v ss osdv ss v ss v ss v ss v ss v ss csync/hsync csync/hsync csync/hsync csync/hsync 10 k to v ss v ss vlpf/vsync vlpf/vsync vlpf/vsync vlpf/vsync 10 k to v ss v ss afcosc afcosc af cosc afcosc 10 k to v ss v ss afcpc afcpc afcpc afcpc open v ss afclpf afclpf afclpf afclpf 10 k to v ss v ss cvin1 cvin1 10 k to v ss 10 k to v ss 10 k to v ss v ss cvout cvout open open open v ss 4fsc in 4fsc in v ss v ss v ss v ss 4fsc out 4fsc out o pen open open open pins cvin2 cvin2 or 10 k to v ss cvin2 or 10 k to v ss cvin2 or 10 k to v ss 10 k to v ss v ss note ? ? ? the registers in the osd, sync separator, and data slicer must not be accessed. the registers in the osd, sync separator, and data slicer must not be accessed. appendix f product lineup rev.2.00 jan. 15, 2007 page 1172 of 1174 rej09b0329-200 appendix f product lineup table f.1 product lineup of h8s/2199r group product type part no. mark code package (package code) mask rom version HD6432199R HD6432199R ( *** )f 112-pin qfp (prqp0112ja-a) h8s/2199r f-ztat version hd64f2199r hd64f2199rf 112-pin qfp (prqp0112ja-a) h8s/2198r mask rom version hd6432198r hd6432198r ( *** )f 112-pin qfp (prqp0112ja-a) h8s/2197r mask rom version hd6432197r hd6432197r ( *** )f 112-pin qfp (prqp0112ja-a) h8s/2197s mask rom version hd6432197s hd6432197s ( *** )f 112-pin qfp (prqp0112ja-a) h8s/2196r mask rom version hd6432196r hd6432196r ( *** )f 112-pin qfp (prqp0112ja-a) h8s/2199r group h8s/2196s mask rom version hd6432196s hd6432196s ( *** )f 112-pin qfp (prqp0112ja-a) note: ( *** ) is the rom code. appendix g package dimensions rev.2.00 jan. 15, 2007 page 1173 of 1174 rej09b0329-0200 appendix g package dimensions the package dimention that is shown in the renesas semiconductor package data book has priority. note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. 1.23 1.23 0.10 0.13 0.65 8 ? 0 ? 23.5 23.2 22.9 3.05 0.12 0.17 0.22 0.24 0.32 0.40 0.00 0.30 0.15 0.10 0.25 l 1 z e z d y x c b 1 b p a h d a 2 e d a a c 1 e e l h e 20 1.6 22.9 23.2 23.5 2.70 20 reference symbol dimension in millimeters min nom max 0.5 0.8 1.1 * 1 * 2 * 3 p e d e d 56 57 84 85 29 28 1 112 f ym x z z b h e h d 2 1 1 detail f c l a a a l terminal cross section p 1 1 b c b c p-qfp112-20x20-0.65 2.4g mass[typ.] fp-112/fp-112v prqp0112ja-a renesas code jeita package code previous code figure g.1 package dimensions (prqp0112ja-a) appendix g package dimensions rev.2.00 jan. 15, 2007 page 1174 of 1174 rej09b0329-200 renesas 16-bit single- chip microcomputer hardware manual h8s/2199r group, h8s/2199r f-ztat? publication date: 1st edition, february 2001 rev.2.00, january 15, 2007 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ?2007. renesas technology corp., all rights reserved. printed in japan. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices colophon 6.0 h8s/2199r group, h8s/2199r f-ztat? hardware manual |
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